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Registers
Keywords: reg default value: x default size: 1 bit The fundamental difference between nets and registers is that registers have to be assigned values explicitly. That value is held until a new assignment is made. This property can, for example, be used to model a E-type flip flop as shown in figure below, with corresponding Verilog code given below.

mdl Ef(,dt,eal,rst cok; oue _fq aa nbe ee, lc) otu q upt ; iptdt,eal,rst cok nu aa nbe ee, lc; rgq e ; awy @psdecok / weee tecokmksatasto t 1 las (oeg lc) / hnvr h lc ae rniin o i (ee = 0 f rst = ) q=1b; '0 es i (nbe=) le f eal=1 q=dt; aa / ipiil :es q=q / mlcty le : edoue nmdl

Register q holds the same value until it us changed by an explicit assignment. As a contrast, if we go into a higher level module, for example the stimulus shown below, the output from the E_ff would have to be assigned as a net so that the E_ff module can drive its value. So now q is a wire.
mdl siuu; oue tmls rgdt,eal,cok rst e aa nbe lc, ee; wr q ie ; iiilbgn nta ei cok=1b; lc '0 frvr# cok=~lc; oee 5 lc cok ed n

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<A name="s1">Registers

Ef ef(,dt,eal,rst cok; _f f0q aa nbe ee, lc) / a wt ''i tepeiu scin tewr ''wl nwhv is / s ih c n h rvos eto, h ie q il o ae t / vledie it i b teEf mdl. / au rvn no t y h _f oue iiilbgn nta ei rst=1b; ee '0 #0rst=1b; 1 ee '1 dt =1b; aa '1 #0eal =1 2 nbe ; #0dt =1b; 1 aa '0 #0dt =1b; 1 aa '1 #0eal =0 1 nbe ; #0dt =1b; 1 aa '0 #0dt =1b; 1 aa '1 #0eal =1 1 nbe ; #0rst=1b; 1 ee '0 #0$iih 3 fns; ed n iiil nta $oio(tm,"q=%" q; mntr$ie d, ) edoue nmdl

EXERCISE Consider the stimulus above and predict the output for q. Then stimulus and check your answer. previous next contents

www.see.ed.ac.uk/~gerard/Teach/Verilog/manual/DataTy pes/registers.html

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