A2422 Compal La-4732p HP Presario Cq35 Pavilion Dv3 Montevina Uma Rev1.0 WWW - mycoMP.su

A
/x
/
om
p.
su
Compal confidential
//
m
yc
Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic
3
tt
p:
2009-02-16
REV:1.0
Compal Secret Data
Security Classification
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cover Sheet
Rev
0.1
Montevina UMA
Date:
Wednesday, February 18, 2009
Sheet
E
of
46
Compal confidential
Montevina Consumer UMA

CK505
Mobile Penryn
Thermal Sensor
EMC1402
72QFN
Clock Generator
SLG8SP553V
uFCPGA-478 CPU
P06
P17
P6, 7, 8
Fan conn
P06
H_A#(3..35)
FSB
H_D#(0..63)
CRT
DDR2 800MHz 1.8V

P19
Intel Cantiga MCH
Support V1.3
P9,10, 11, 12, 13, 14
om
p.
su
HDMI
BANK 0, 1, 2, 3
P35
New Card
P26
P26
RJ45/11 CONN
P25
tt
p:
RTC CKT.
P21
CardReader
SATA Slave
5 in1 Slot
P27
Audio CKT
P27
AMP & Audio Jack

TPA6047
P28
P29
LPC BUS
MDC
P28
SATA HDD Connector
P24
ENE
KB926
P32
SATA ODD ConnectorP24
SPI
e-SATA Connector
Int.KBD
P30
P32
P33
P33
P30
Codec_IDT92HD75B
Touch Pad CONN.
LED
Finger print
P20,21,22,23
P26
//
m
P25
P19
SATA Slave
mBGA-676
Mini-Card
WWAN
USB Camera
SATA Master-1
yc
WLAN
P30
Azalia
Intel ICH9-M
Mini-Card
P30
C-Link
PCI-E BUS*4
RTL8103EL
(10/100M)
USB conn x1
BT Conn
USB2.0 X12
DMI X4
P15, 16
Dual Channel
FCBGA 1329
GM47
P18
DDR2 SO-DIMM X2
/x
/
LVDS Panel
Interface
667/800/1066 MHz 1.05V
USB Board Conn

USB port x2
SPI ROM
SST25VF080P31
ACCELEROMETER-1
P24
ST
P30
K/B backlight Conn
Capsense switch Conn
P33
P33
Compal Secret Data
DC/DC Interface CKT.
2006/02/13
Issued Date
2006/03/10
Deciphered Date
Title
P36
Block Diagram
Rev
0.1
Montevina UMA
Date:
Sheet
E
of
46
Voltage Rails
Symbol Note :
O MEANS ON
X MEANS OFF
+1.5V
+5VS
+3VS
+1.5VS
+0.75V
+VCCP
+CPU_CORE
+2.5VS
+1.8V
State
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
1
yc
S0
Cantiga
V
X
X
X
X
V
X
X
X
X
V
X
X
X
V
X
X
X
V
X
LCD
X
X
X
V
p:
ICH9
V
X
X
X
MINI CARD
SODIMM CLK CHIP
tt
KB926
X
X
X
X
SERIAL Thermal
EEPROM Sensor
Cap sensor
board
NEW CARD
X
X
V
X
V
X
X
X
PCIe-1
PCIe-2
PCIe-3
PCIe-4
PCIe-5
PCIe-6
WWAN
X
WLAN
GLAN (Realtek)
X
New Card
I2C / SMBUS ADDRESSING

DEVICE
HEX ADDRESS
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
A0
A4
D2
10100000
10100100
11010010
G sensor
X
X
V
X
SOURCE INVERTER BATT
//
m
SMBUS Control Table
PCIe assignment:
/x
/
+3VALW
@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.
DEBUG@ : means just reserve for debug.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part
ESATA @ : means just reserve for ESATA
GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print
Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot
PA @ : means just reserve for PA
PR @ : means just reserve for PR
om
p.
su
+5VALW
+B
KB926
USB-0 Right side(with eSATA)

USB-1 Left side
USB-2 Left side
USB-3 Cardreader
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X
: means Analog Ground
power
plane
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT
USB assignment:
: means Digital Ground
Compal Secret Data
2007/08/28
Issued Date
Deciphered Date
2006/03/10
Title
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Notes List
Rev
0.1
Montevina UMA
Date:
Sheet
of
46
60mA
50mA
25mA
1A
D
+V_BATTERY
10mA
177mA
ICH9
1.7A
5.89A
+3VALW
3.39A
RT5158
0.3A
0.58A
2.2A
+1.5VS
1.56A
1.3A
+5VALW
3.7A
+1.8V
tt
B+++
12.11A
ICH9
1A
35mA
50mA
4.7A
1.05V_B+
10mA
1.8A
700mA
50mA
800Mhz
CPU_B+
10mA
+VCC_CORE
SPI ROM
New card
ICH9
+LCDVDD
LVDS CON
+3VS_CK505
C
Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)
+VDDA
IDT 9275B
+5VAMP
ODD
SATA
PC Camera(4.75V)
+0.9V
1.17A
1.26A
+VCCP
34A/1.025V
+3VALW_EC
4G x2
2.3A
2A
+3VS_DVDD
ALC268
MCH
DDR2
1.9A
p:
3.7 X 3=11.1V
250mA
1A
yc
//
m
7A
1.5A
ICH_VCC1_5
ICH9
+5VS
B+
BATT
+3VS
om
p.
su
B++
657mA
DC
278mA
LAN
VIN
2A
1A
LVDS CON
/x
/
INVPWR_B+
300mA
AC
Finger printer
20mA
0.3A
+3VAUX_BT
ICH9
MCH
CPU
CPU
Compal Secret Data
Issued Date
2007/08/28
Deciphered Date
2006/03/10
Title
Power delevry
Size
C
Date:

Document Number
Rev
0.1
Montevina UMA
1
Sheet
of
46
om
p.
su
/x
/
tt
p:
//
m
yc
Compal Secret Data
2007/08/28
Issued Date
Deciphered Date
2006/03/10
Title
Custom
Notes List
Rev
0.1
Montevina UMA
Date:
Sheet
of
46
ITP-XDP Connector
+VCCP
XDP_TDI
R2
54.9_0402_1%
XDP_TMS
R3
54.9_0402_1%
XDP_TDO
R4
54.9_0402_1%
XDP_TRST#
R7
54.9_0402_1%
XDP_TCK
R8
54.9_0402_1%
9 H_A#[3..16]
JCPU1A
H_STPCLK#
H_INTR
H_NMI
H_SMI#
D5
C6
B4
A3
A20M#
FERR#
IGNNE#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
H_IERR#
H_INIT#
LOCK#
H4
H_LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
G6
E4
H_HIT#
H_HITM#
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
THERMTRIP#
D21
A24
B25
C7
A22
A21
H_RESET# 9
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9
H_HIT# 9
H_HITM# 9
H_THERMDA_R
H_THERMDC_R
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
XDP_DBRESET# 22
R13
R14
R15
2 56_0402_1%
+VCCP
2 0_0402_5%
2 0_0402_5%
1
1
H_THERMTRIP# 9,21
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
C3
1
+3VS
1
C2
U1
2
1
H_THERMDA
H_THERMDC
2
2200P_0402_50V7K
THERM#
R16
1
2
10K_0402_5%
VDD
SMCLK
DP
SMDATA
DN
ALERT#
THERM#
GND
SMB_EC_CK2
SMB_EC_DA2
R6 1
SMB_EC_CK2 32
SMB_EC_DA2 32
2 10K_0402_5%
+3VS
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
B
Fan Control circuit

SI-1 Change to voltage control circuit
+5VS
+3VS
2.2U_0603_6.3V4Z
C4
@
R17
56_0402_5%
FAN_SPEED
OCP# 22
C1510
1000P_0402_50V7K
U51
2 2
R1209
10K_0402_5%
32 FAN_SPEED
OCP#
3
1
@ Q1
MMBT3904_NL_SOT23-3
+3VS
H_THERMDA
H_THERMDC
+VCCP
H_PROCHOT#
H_THERMDA, H_THERMDC routing

together, Trace width / Spacing = 10 / 10
mil
Penryn
/x
/
H_LOCK# 9
H_PROCHOT#
H CLK
BCLK[0]
BCLK[1]
T1
Place TP with a
GND 0.1" away
0.1U_0402_16V4Z
PROCHOT#
THERMDA
THERMDC
H_BR0# 9
H_INIT# 21
om
p.
su
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
THERMAL
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
D2
D22
D3
F6
H_BR0#
yc
A6
A5
C4
F1
This shall place near CPU
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
//
m
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_A20M#
H_FERR#
H_IGNNE#
H_DEFER#
H_DRDY#
H_DBSY#
D20
B3
HIT#
HITM#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
ICH
21 H_A20M#
21 H_FERR#
21 H_IGNNE#
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
H5
F21
E1
H_ADS# 9
H_BNR# 9
H_BPRI# 9
p:
9 H_ADSTB#1
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
H_ADS#
H_BNR#
H_BPRI#
IERR#
INIT#
BR0#
ADDR GROUP_1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
DEFER#
DRDY#
DBSY#
H1
E2
G5
tt
K3
H2
K2
J3
L1
ADS#
BNR#
BPRI#
CONTROL
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
XDP/ITP SIGNALS
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
RESERVED
9 H_REQ#0
9 H_REQ#1
9 H_REQ#2
9 H_REQ#3
9 H_REQ#4
9 H_A#[17..35]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
ADDR GROUP_0
9 H_ADSTB#0
21
21
21
21
9
8
7
6
5
Thermal Pad VEN

GND
VIN
GND
VO
GND
VSET
GND
C5
0.1U_0402_16V4Z
1
2
3
4
+5VS_FAN
1
G996RD1U_TDFN8_3X3
CONN@
JFAN1
C1509
1
2
3
2.2U_0603_6.3V4Z
ACES_85204-03001
FAN_SPEED
+5VS
1
2
3
G1
G2
4
5
D63
2
3
2
1
32 FAN_SET
+VCCP
A
Vcc
Line to be protected
GND
DLPT05-7-F_SOT23-3
R18
56_0402_5%
Compal Secret Data
H_IERR#
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

Penryn(1/3)-AGTL+/ITP-XDP
Rev
0.1
Montevina UMA
Date:
Sheet
1
of
46
+VCC_CORE
MISC
E5
B5
D24
D6
D7
AE6
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
/x
/
COMP0
COMP1
COMP2
COMP3
DATA GRP 2
R26
U26
AA1
Y1
COMP[0]
COMP[1]
COMP[2]
COMP[3]
H_DPRSTP# 9,21,42
H_DPSLP# 21
H_DPWR# 9
H_PWRGOOD 21
H_CPUSLP# 9
H_PSI# 42
* Route the TEST3 and TEST5 signals through

a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
R25
R26
CPU_BSEL0
166
200
266
//
m
CPU_BSEL1
+VCCP
R19
G21 +VCCPA
+VCCPB
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
1
1
2
2
0_0402_5%
0_0402_5%
R20
1
+ C6
330U_D2E_2.5VM_R7
2
B26
C26
VCCA[01]
VCCA[02]
+1.5VS
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
AF7
VCCSENSE
AE7
VSSSENSE
42
42
42
42
42
42
42
1
C7
2
1
C8
2
Near pin B26
VCCSENSE 42
VSSSENSE 42
Penryn
.
p:
CPU_BSEL2
Length match within 25 mils.

The trace width/space/other is 20/7/25.
tt
CPU_BSEL
Resistor placed within 0.5"

of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
+VCCP
R24
yc
Penryn
R23
0.01U_0402_16V7K
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
27.4_0402_1%
2
1
AD26
C23
D25
C24
AF26
AF1
A26
C3
B22
B23
C21
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
54.9_0402_1%
2
1
T2
T3
T4
T5
T6
17 CPU_BSEL0
17 CPU_BSEL1
17 CPU_BSEL2
+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
om
p.
su
2 1K_0402_5%
2 1K_0402_5%
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
1
1
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
H_D#[48..63] 9
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
R27
1K_0402_1%
+V_CPU_GTLREF
@ R21
@ R22
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
JCPU1C
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
+VCC_CORE
9 H_DSTBN#1
9 H_DSTBP#1
9 H_DINV#1
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
DATA GRP 1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
27.4_0402_1%
2
1
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
DATA GRP 3
9
9
9
9
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 0
+VCC_CORE
H_D#[32..47] 9
JCPU1B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
54.9_0402_1%
2
1
9 H_D#[0..15]
10U_0805_6.3V6M
R28
2 100_0402_1%
VCCSENSE
R30
2 100_0402_1%
VSSSENSE
R29
2K_0402_1%
Close to CPU pin within

500mils.
Close to CPU pin AD26

within 500mils.
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

Rev
0.1
Montevina UMA
Date:
Sheet
1
of
46
+VCC_CORE
Place these capacitors on

L8 (North side,Secondary
Layer)
C9
10U_0805_6.3V6M
C10
10U_0805_6.3V6M
C11
10U_0805_6.3V6M
C12
10U_0805_6.3V6M
C13
10U_0805_6.3V6M
C14
10U_0805_6.3V6M
C15
10U_0805_6.3V6M
C16
10U_0805_6.3V6M
+VCC_CORE
JCPU1D
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

Layer)
C17
10U_0805_6.3V6M
C18
10U_0805_6.3V6M
C19
10U_0805_6.3V6M
C20
10U_0805_6.3V6M
C21
10U_0805_6.3V6M
C22
10U_0805_6.3V6M
C23
10U_0805_6.3V6M
C24
10U_0805_6.3V6M
+VCC_CORE
C25
10U_0805_6.3V6M
C26
10U_0805_6.3V6M
C27
10U_0805_6.3V6M
+VCC_CORE
C33
10U_0805_6.3V6M
10U_0805_6.3V6M
Mid Frequence Decoupling
@
C42
C35
10U_0805_6.3V6M
10U_0805_6.3V6M
C36
10U_0805_6.3V6M
C37
10U_0805_6.3V6M
C30
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
C31
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
C
yc
330U_D2_2VY_R7M
330U_D2_2VY_R7M
//
m
330U_D2_2VY_R7M
+VCC_CORE
C29
ESR <= 1.5m ohm

Capacitor > 1980uF
Near CPU CORE regulator
C41
C34
om
p.
su
10U_0805_6.3V6M
C43
1
+
C44
330U_D2_2VY_R7M

Layer)
C28
/x
/

Layer)
p:
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
tt
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
+VCCP
C45
0.1U_0402_10V6K
Inside CPU center cavity in 2 rows

1
C46
0.1U_0402_10V6K
C47
0.1U_0402_10V6K
C48
0.1U_0402_10V6K
C49
0.1U_0402_10V6K
C50
0.1U_0402_10V6K
Penryn
.
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

Rev
0.1
Montevina UMA
Date:
Sheet
1
of
46
within 100 mils from NB
2 10K_0402_5%
7
7
7
7
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
7
7
7
7
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
11 CFG5
11 CFG6
11 CFG7
11 CFG8
11 CFG9
11 CFG10
11 CFG11
11 CFG12
11 CFG13
11 CFG14
11 CFG15
11 CFG16
11 CFG17
11 CFG18
11 CFG19
11 CFG20
C54
6
6
6
6
6
H_RS#0 6
H_RS#1 6
H_RS#2 6
PLT_RST#
0.1U_0402_16V4Z
tt
R41
R42
22 PM_BMBUSY#
7,21,42 H_DPRSTP#
15 PM_EXTTS#0
16 PM_EXTTS#1
22,32 PM_PWROK
1
2
1
2 100_0402_5%
0_0402_5%
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
THERMTRIP#
DPRSLPVR
1 @
C55
2
+1.8V
R47
R55
C59
V_DDR_MCH_REF
0.1U_0402_16V4Z
15,16 V_DDR_MCH_REF
R48
10K_0402_1%
C57
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R29
B7
N33
P32
AT40
AT11
T20
R32
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
BC28
AY28
AY36
BB36
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
BA17
AY16
AV16
AR13
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
BD17
AY17
BF15
AY13
M_ODT0
M_ODT1
M_ODT2
M_ODT3
SM_RCOMP
SM_RCOMP#
BG22
BH21
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
BF28
BH28
SMRCOMP_VOH
SMRCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
AV42
AR36
BF17
BC36
V_DDR_MCH_REF
SM_PWROK
SM_REXT
TP_SM_DRAMRST#
B38
A38
E41
F41
CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#
F43
E43
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
AE41
AE37
AE47
AH39
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AE40
AE38
AE48
AH40
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AE35
AE43
AE46
AH42
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
AD35
AE44
AF46
AH43
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
PEG_CLK
PEG_CLK#
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
15
15
16
16
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
15
15
16
16
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
15
15
16
16
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
15
15
16
16
M_ODT0
M_ODT1
M_ODT2
M_ODT3
R34
R35
15
15
16
16
+1.8V
1
1
2 80.6_0402_1%
2 80.6_0402_1%
1
1
2 0_0402_5%
2 499_0402_1%
Follow Design Guide

For Cantiga: 80.6ohm
R36
R37
T29
CLK_MCH_DREFCLK 17
CLK_MCH_DREFCLK# 17
MCH_SSCDREFCLK 17
MCH_SSCDREFCLK# 17
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
C
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
AR24
AR21
AU24
AV20
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
ME
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
DMI
R40
GRAPHICS VID
CLKREQ#_7
/x
/
2 10K_0402_5%
om
p.
su
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
B33
B32
G33
F33
E33
T30
T31
C34
T35
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
22
22
22
22
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
22
22
22
22
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
22
22
22
22
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
22
22
22
22
+VCCP
1
2
1
2
R39
R45
10K_0402_1%
0.1U_0402_16V4Z
221_0603_1%
2
1
100_0402_1%
2
1
0.1U_0402_16V4Z
24.9_0402_1%
2
1
1K_0402_1%
1
2
2K_0402_1%
2
1
R54
PM_EXTTS#1
NC
C58
2 10K_0402_5%
T85
T86
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
+V_DDR_MCH_REF generated by DC-DC
+H_SWNG
RESERVED
RESERVED
RESERVED
RESERVED
PM
R52
H_RCOMP
Layout Note: V_DDR_MCH_REF

trace width and spacing is 20/20.
+VCCP
+H_VREF
R38
17 MCH_CLKSEL0
17 MCH_CLKSEL1
17 MCH_CLKSEL2
+VCCP
PM_EXTTS#0
7
7
7
7
20,25,26 PLT_RST#
6,21 H_THERMTRIP#
22,42 DPRSLPVR
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
R46
0.01U_0402_25V7K
2.2U_0603_6.3V4Z
C53
H_ADS# 6
H_ADSTB#0 6
H_ADSTB#1 6
H_BNR# 6
H_BPRI# 6
H_BR0# 6
H_DEFER# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 7
H_DRDY# 6
H_HIT# 6
H_HITM# 6
H_LOCK# 6
H_TRDY# 6
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_AVREF
H_DVREF
Route H_SCOMP and H_SCOMP# with trace

width, spacing and impedance (55 ohm) same as
FSB data traces
T25
T26
T27
T28
BG23
BF23
BH18
BF18
RESERVED
+3VS
CANTIGA ES_FCBGA1329
Layout note:
AY21
R33
1K_0402_1%
AP24
AT21
AV24
AU20
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
AH37
AH36
AN36
AJ35
AH34
CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
+CL_VREF
0621 add CLK and DAT for DVI

DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
N28
M28
G36
E36
K36
H36
B12
T36
T37
HDMICLK_NB
HDMIDAT_NB
CLKREQ#_7
MCH_ICH_SYNC#
TSATN#
R43
1K_0402_1%
CL_CLK0 22
CL_DATA0 22
M_PWROK 22,32
CL_RST# 22
B28
B30
B29 HDA_SDIN2_NB
C29
A28
C56
0.1U_0402_16V4Z
HDMICLK_NB 34
HDMIDAT_NB 34
CLKREQ#_7 17
MCH_ICH_SYNC#
1 R737
H_RS#0
H_RS#1
H_RS#2
T24
RESERVED
RESERVED
RESERVED
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
B6
F12
C8
H_RS#_0
H_RS#_1
H_RS#_2
T22
T23
B31
B2
M1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MISC
H_CPURST#
H_CPUSLP#
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
22
2 56_0402_5% +VCCP
TSATN# 32
HDA_BITCLK_NB 21
R210
HDA_RST#_NB 21
1
HDA_SDOUT_NB 21
HDA_SYNC_NB 21
R44
499_0402_1%
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
DDR CLK/ CONTROL/COMPENSATION
B15
K13
F13
B13
B14
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
SMRCOMP_VOL
yc
H_SWING
H_RCOMP
R32
3.01K_0402_1%
20% of 1.8V VCC_SM
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
CLK
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
80% of 1.8V VCC_SM
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
SMRCOMP_VOH
L10
M7
AA5
AE6
C52
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
2.2U_0603_6.3V4Z
C51
J8
L3
Y13
Y1
R31
1K_0402_1%
//
m
A11
B11
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
+H_VREF
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
C12
E11
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
+1.8V
H_RESET#
H_CPUSLP#
6 H_RESET#
7 H_CPUSLP#
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
C5
E3
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
CFG
+H_SWNG
H_RCOMP
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
p:
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
HOST
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
RSVD
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
0.01U_0402_25V7K
U2A
7 H_D#[0..63]
U2B
H_A#[3..35] 6
HDA
*R44*Follow
Intel feedback
HDA_SDIN2 21
33_0402_5%
0830 Add pull-up and pull-down resistor.
Compal Secret Data
Near B3 pin
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

Cantiga(1/6)-AGTL/DMI/DDR
Rev
0.1
Montevina UMA
Date:
Sheet
1
of
46
16 DDR_B_D[0..63]
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_RAS# 15
DDR_A_CAS# 15
DDR_A_WE# 15
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
15
15
yc
DDR_A_MA[0..14] 15
BC16
BB17
BB33
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
AU17
BG16
BF14
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16
DDR_B_RAS# 16
DDR_B_CAS# 16
DDR_B_WE# 16
DDR_B_DM[0..7] 16
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
16
16
DDR_B_MA[0..14] 16
tt
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
/x
/
15
//
m
MEMORY
DDR_A_DM[0..7]
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
BB20
BD20
AY20
SA_RAS#
SA_CAS#
SA_WE#
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15
MEMORY
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
SYSTEM
BD21
BG18
AT25
SA_BS_0
SA_BS_1
SA_BS_2
p:
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SYSTEM
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
DDR
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U2E
DDR
U2D
om
p.
su
15 DDR_A_D[0..63]
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

Cantiga(2/6)-DDR2 A/B CH
Rev
0.1
Montevina UMA
Date:
Sheet
1
10
of
46
Strap Pin Table
ENBKL
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDS_B0LVDS_B1LVDS_B2LVDS_B3-
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
LVDS_B0+
LVDS_B1+
LVDS_B2+
LVDS_B3+
TV_COMPS
TV_LUMA
TV_CRMA
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
F25
H25
K25
TVA_DAC
TVB_DAC
TVC_DAC
H24
TV_RTN
C31
E32
TV_DCONSEL_0
TV_DCONSEL_1
R67
E28
G28
J28
G29
18 3VDDCCL
18 3VDDCDA
18 CRT_HSYNC
HSYNC
VSYNC
H32
J32
J29
E29
L29
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
R70
1.02K_0402_1%
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_BCLK#
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK
PEGCOMP trace width

and spacing is 20/25 mils.
TMDS_B_HPD#
CFG9 (PCIE Graphics

Lane Reversal)
TMDS_B_HPD# 34
C274
C275
C276
C277
1
1
1
1
2
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
C278
C279
C280
C281
1
1
1
1
2
2
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
TMDS_B_DATA2# 34
TMDS_B_DATA1# 34
TMDS_B_DATA0# 34
TMDS_B_CLK# 34
LVDS_ACLK+
19 LVDS_ACLK+
LVDS_ACLKLVDS_A0+
19 LVDS_ACLK19 LVDS_A0+
19 LVDS_A019 LVDS_A1+
19 LVDS_A119 LVDS_A2+
2
1
LVDS_A0LVDS_A1+
2
1
LVDS_A1LVDS_A2+
2
1
LVDS_A2-
19 LVDS_A2-
@
C60
0.1U_0402_10V6K
@
C61
0.1U_0402_10V6K
@
C62
0.1U_0402_10V6K
@
C63
0.1U_0402_10V6K
CFG[13:12]
(XOR/ALLZ)
CFG[15:14]
CFG16 (FSB Dynamic ODT) 01 ==

Disabled
Enabled
Reserved
CFG[18:17]
19 LVDS_BCLK+
19 LVDS_BCLK19 LVDS_B0+
19 LVDS_B019 LVDS_B1+
19 LVDS_B119 LVDS_B2+
19 LVDS_B2-
LVDS_BCLK+
LVDS_BCLKLVDS_B0+
2
1
LVDS_B0LVDS_B1+
2
1
LVDS_B1LVDS_B2+
2
1
LVDS_B2-
CFG20 (PCIE/SDVO
concurrent)
(Lane number in
Operation
1 = Order)
Reverse Lane
0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.
+3VS
+3VS
@ R71
4.02K_0402_1%
CFG5
9 CFG5
9 CFG16
9 CFG19
@ R74
2.21K_0402_1%
@ R72
1
2
4.02K_0402_1%
@ R73
1
2
4.02K_0402_1%
@R75
1
2
4.02K_0402_1%
9 CFG20
9 CFG11
1
CFG19 (DMI Lane Reversal) 0 = Normal

TMDS_B_DATA2 34
TMDS_B_DATA1 34
TMDS_B_DATA0 34
TMDS_B_CLK 34
tt
For 3G
WWAN
For 3G
WWAN
0 = Reverse Lane,15->0,
114->1
= Normal Operation,Lane Number
in order
0=
Enable
1 = Disable
*
Reserved
00 = Reserved
01 = XOR Mode
10
= All Z Mode
Enabled
11
= Normal
(Default)
Enabled
*
Operation
Reserved
CFG10 (PCIE
Lookback
CFG11 enable)
p:
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
CRT_GREEN
18 CRT_VSYNC
3VDDCCL
3VDDCDA
CRT_HSYNC R68 1
30.1_0402_1%
CRT_VSYNC R69 1
30.1_0402_1%
CRT_BLUE
VGA
R66
150_0402_1%
150_0402_1%
R65
150_0402_1%
Follow Intel DG &

Checklist
2.2K_0402_5%
0_0402_5%
2
2
1
1
18 M_BLUE
18 M_GREEN
18 M_RED
@ R64
R406
M_BLUE
M_GREEN
M_RED
1
2
+3VS
R63
TV
R62
75_0402_1%
R61
75_0402_1%
75_0402_1%
Follow Intel DG &

Checklist
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
000 = FSB
1066MHz
010
= FSB
800MHz
011 = FSB
667MHz
Others =
Reserved
Reserved
CFG[4:3]
0 = DMI x
12 = DMI x
CFG5 (DMI select)
* Interface is
40 = The iTPM Host
CFG6
enable
1 = The iTPM Host Interface is
0disable
=(TLS)chiper suite with no
CFG7 (Intel Management confidentiality
=(TLS)chiper suite with
Engine Crypto strap) 1confidentiality
Reserved
CFG8
CFG[2:0] FSB Freq

select
/x
/
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
T41
T48
T49
T50
H47
E46
G40
A40
T40
LVDS_A0LVDS_A1LVDS_A2LVDS_A3-
T39
LVDS_ACLKLVDS_ACLK+
LVDS_BCLKLVDS_BCLK+
M29
C44
B43
E37
E38
C41
C40
B37
A37
2 4.75K_0402_1%
LVDS
T38
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
T37
T36
om
p.
su
ENAVDD
R60 1
19 ENAVDD
Follow Intel DG &

Checklist
M33
K33
J33
PEG_COMPI
PEG_COMPO
yc
2 10K_0402_5%
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
+VCC_PEG
R57
1
2
49.9_0402_1%
//
m
R59 1
DDC2_CLK
DDC2_DATA
19 DDC2_CLK
19 DDC2_DATA
2 10K_0402_5%
GRAPHICS
19 NB_BKLT_CTRL
32 ENBKL
+3VS
100K_0402_5%
L32
G32
M32
PCI-EXPRESS
NB_BKLT_CTRL
ENBKL
R58 1
U2C
R148
9 CFG12
@
C1500
0.1U_0402_10V6K
9 CFG13
@
C1501
0.1U_0402_10V6K
9 CFG6
9 CFG7
@
C1502
0.1U_0402_10V6K
9 CFG8
@
C1503
0.1U_0402_10V6K
9 CFG9
9 CFG10
1
2
2.21K_0402_1%
2007/08/28
2006/03/10
Deciphered Date
9 CFG14
@ R81
1
2
2.21K_0402_1%
@R83
1
2
2.21K_0402_1%
@R84
1
2
2.21K_0402_1%
9 CFG17
@R86
1
2
2.21K_0402_1%
9 CFG18
Compal Secret Data
Issued Date
@R79
Title
9 CFG15
@R76
1
2
2.21K_0402_1%
@ R77
1
2
2.21K_0402_1%
@ R78
1
2
2.21K_0402_1%
@R80
1
2
2.21K_0402_1%
@R82
1
2
2.21K_0402_1%
@R85
1
2
2.21K_0402_1%
@R87
1
2
2.21K_0402_1%

Cantiga(3/6)-VGA/LVDS/TV
Rev
0.1
Montevina UMA
Date:
Sheet
1
11
of
46
+3VS_DAC_BG
C82
C81
VTT
C80
CRT
PLL
A LVDS
A PEG
/x
/
om
p.
su
A SM
AXF
A CK
yc
SM CK
//
m
+VCC_PEG
AH48
AF48
AH47
AG47
+1.05VS_DMI
+1.05VS_PEGPLL
10U_0805_10V4Z
2
2
+VCCP_D
VTTLF
VTTLF
VTTLF
A8
L1
AB2
D3
2
+VCCP
R105
1
2
10_0402_5%
2006/03/10
Deciphered Date
Title
R108
1
2
0_0603_5%
+1.8V
C116
2007/08/28
+1.8V
Compal Secret Data
Issued Date
+1.8V_TXLVDS
1000P_0402_50V7K
R107
1
2
0_0603_5%
C114
C113
C120
R112
1
2
100_0603_1%
40 mils
1U_0603_10V4Z
10U_0805_10V4Z
+1.5VS
0.1U_0402_16V4Z
C119
0.022U_0402_16V7K
C118
R111
1
2
BLM18PG181SN1D_0603
+3VS_HV
+3VS
+3VS
0.1U_0402_16V4Z
C117
0.022U_0402_16V7K
R106
1
2
0_0402_5%
CH751H-40PT_SOD323-2
0.47U_0603_10V7K
C112
+1.5VS_QDAC
+VCCP
R104
1
2
0_0603_5%
+1.8V_LVDS
+3VS_TVDAC
+1.05VS_DMI
+VCCP
L1
1
2
BLM18PG121SN1D_0603
p:
V48
U48
V47
U47
U46
R102
1
2
0_0805_5%
C100
+3VS_HV
0.47U_0603_10V7K
C111
+1.8V_TXLVDS
0.47U_0603_10V7K
C110
60.31mA
+VCC_PEG
+VCCP
R101
1
2
MBK2012121YZF_0805
456mA
tt
VCCD_LVDS
VCCD_LVDS
DMI
50mA
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
VTTLF
VCCD_PEG_PLL
PEG
HV
TV
HDA
157.2mA
D TV/CRT
+1.8V_LVDS
M38
L37
48.363mA
LVDS
AA47
C85
+1.05VS_PEGPLL
VCCD_HPLL
1732mA
VCC_HV
VCC_HV
VCC_HV
K47
C35
B35
A35
+VCCP
10U_0805_10V4Z
VCCD_QDAC
VCC_TX_LVDS
0.1U_0402_16V4Z
C109
L28
AF1
118.8mA
105.3mA
58.67mA
+1.8V_SM_CK
C101
VCCD_TVDAC
BF21
BH20
BG20
BF20
C108
M25
C99
R99
1
2
0_0805_5%
+V1.05VS_AXF
124mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
10U_0805_10V4Z
50mA
B22
B21
A21
0.1U_0402_16V4Z
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
VCCA_TV_DAC
VCCA_TV_DAC
VCC_AXF
VCC_AXF
VCC_AXF
+1.05VS_MPLL
C107
+1.5VS_QDAC
+1.05VS_HPLL
C79
VCCA_SM_CK
VCCA_SM_CK
26mA
VCCA_SM_CK
VCCA_SM_CK
26mA
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCC_HDA
C106
A32
0.1U_0402_16V4Z
POWER
0.1U_0402_16V4Z
+1.5VS
0.1U_0402_16V4Z
720mA
0.1U_0402_16V4Z
+3VS_TVDAC
+1.5VS_TVDAC
B
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
B24
A24
+1.5VS
220U_D2_4VM
R95
1
2
0_0805_5%
+1.5VS_TVDAC
+VCCP
R98
1
2
MBK2012121YZF_0805
C98
C105
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
+1.05VS_HPLL
321.35mA
0.1U_0402_16V4Z
C104
1U_0603_10V4Z
10U_0805_10V4Z
1U_0603_10V4Z
C103
C102
VCCA_PEG_PLL
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
+1.05VS_A_SM_CK
R103
1
2
0_0603_5%
AA48
C97
2
1U_0603_10V4Z
1U_0603_10V4Z
C93
4.7U_0805_10V4Z
0.022U_0402_16V7K
C96
C92
10U_0805_10V4Z
C95
C94
10U_0805_10V4Z
C91
+1.05VS_A_SM
R100
1
2
0_0805_5%
C90
+VCCP
+1.8V
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VS_PEGPLL
C89
VCCA_PEG_BG
50mA
1
C78
AD48
+1.5VS_PEG_BG
VSSA_LVDS
+VCCP
R94
1
2
10U_FLC-453232-100K_0.25A_10%
C84
R97
1
2
0_0603_5%
VCCA_LVDS
414uA
10U_0805_10V4Z
+1.5VS
J47
+VCCP
R93
1
2
0_0603_5%
+1.8V_SM_CK
+1.05VS_DPLLB
C83
+3VS
C88
1000P_0402_50V7K
2
10U_0805_10V4Z
+1.8V_TXLVDS
10U_0805_10V4Z
J48
1
220U_D2_4VM
139.2mA
VCCA_MPLL
13.2mA
@ R96
1
2
0_0603_5%
VCCA_HPLL
10U_0805_10V4Z
AE1
24mA
C74
+1.05VS_MPLL
64.8mA
VCCA_DPLLB
C87
AD1
C86
L48
+1.05VS_HPLL
1
2
R90
10U_FLC-453232-100K_0.25A_10%
0.1U_0402_16V4Z
+1.05VS_DPLLB
64.8mA
VCCA_DPLLA
2.2U_0805_16V4Z
0.1U_0402_16V4Z
C76
F47
+1.05VS_DPLLA
0.1U_0402_16V4Z
VCCA_DAC_BG
VSSA_DAC_BG
4.7U_0805_10V4Z
R91
1
2
BLM18PG181SN1D_0603
0.022U_0402_16V7K
C75
A25
B25
C72
+3VS_DAC_BG
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
0.47U_0603_10V7K
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCCA_CRT_DAC
VCCA_CRT_DAC
+3VS
+VCCP
+V1.05VS_AXF
C71
+3VS_DAC_CRT
+3VS_DAC_CRT
+1.05VS_DPLLA
C73
852mA
73mA
B27
A26
2.68mA
D
+VCCP
U2H
4.7U_0805_10V4Z
220U_D2_4VM
R88
2
BLM18PG181SN1D_0603
10U_0805_10V4Z
C70
0.1U_0402_16V4Z
C69
0.022U_0402_16V7K
C68
**RED Mark: Means UMA & dis@ Power select**

~It check by INTEL Graphics Disable Guidelines~
+3VS
2
A

Cantiga(4/6)-PWR
Custom
Rev
0.1
Montevina UMA
Date:
Sheet
1
12
of
46
+VCCP
U2G
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
1U_0603_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
+ C135
yc
1
GM47@ C134
+ C1508
330U_D2E_2.5VM_R7
1
C138
10U_0805_10V4Z
1 @
C1491
2
22P_0402_25V8K
1 @
C1490
1
C137
22P_0402_25V8K
//
m
1
C136
1 @
C1492
2
tt
1 @
C1494
2
22P_0402_25V8K
22P_0402_25V8K
22P_0402_25V8K
1 @
C1493
1 @
C1495
2
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
6326.84mA
VCC GFX NCTF
+VCCP
SI-1 Add C for GM47
22P_0402_25V8K
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
330U_D2E_2.5VM_R7
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
Reserve for WWAN
4.7U_0603_6.3V6M
1
C127
0.22U_0402_10V4Z
Compal Secret Data

2007/08/28
2006/03/10
Deciphered Date
Title
1U_0603_10V4Z
1U_0603_10V4Z
C145
0.47U_0402_6.3V6K
C144
C143
0.22U_0603_10V7K
0.22U_0603_10V7K
AV44 VCCSM_LF1
BA37 VCCSM_LF2
AM40 VCCSM_LF3
AV21 VCCSM_LF4
AY5 VCCSM_LF5
AM10 VCCSM_LF6
BB13 VCCSM_LF7
C142
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
Issued Date
C129
D
C128
C141
AJ14
AH14
0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z
PAD T42
PAD T43
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
C139 0.1U_0402_16V4Z
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC GFX
om
p.
su
/x
/
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC SM LF
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
VCC SM
p:
VCC
+VCCP
POWER
T32
0317 change value
VCC NCTF
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC CORE
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
C123
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
10U_0805_10V4Z
C122
C125
0.1U_0402_16V4Z
C133
0.22U_0402_10V4Z
C132
0.22U_0402_10V4Z
C124
10U_0805_10V4Z
C131
220U_D2_4VM
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
10U_0805_10V4Z
C126
+1.8V
0.01U_0402_16V7K
C130
+VCCP
Extnal Graphic: 1210.34mA

integrated Graphic: 1930.4mA
330U_D2E_2.5VM_R7
U2F
POWER
3000mA

Cantiga(5/6)-PWR/GND
Rev
0.1
Montevina UMA
Date:
Sheet
1
13
of
46
U2J
BA16
VSS
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS NCTF
VSS
VSS
VSS
VSS
VSS SCB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
yc
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
/x
/
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
//
m
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
p:
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
tt
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
om
p.
su
U2I
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

Cantiga(6/6)-PWR/GND
Rev
0.1
Montevina UMA
Date:
Sheet
1
14
of
46
+1.8V
+1.8V
V_DDR_MCH_REF
10 DDR_A_DQS#[0..7]
DDR_A_D11
DDR_A_D10
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D29
DDR_A_D24
DDR_A_DM3
om
p.
su
DDR_A_D26
DDR_A_D27
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
9 DDR_CKE0_DIMMA
10 DDR_A_BS2
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
10 DDR_A_CAS#
9 DDR_CS1_DIMMA#
9 M_ODT1
2
C170
C169
C168
C167
C166
C165
C164
C163
C162
C161
C160
C159
yc
10 DDR_A_BS0
10 DDR_A_WE#
//
m
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C158
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
3
4
8
7
6
5
56_8P4R_0.05
56_8P4R_0.05
RP31
RP32
DDR_A_MA8
DDR_A_MA5
DDR_A_MA1
DDR_A_MA3
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DDR_A_MA14
DDR_CKE1_DIMMA
DDR_A_MA6
DDR_A_MA7
DDR_A_MA2
DDR_A_MA4
DDR_A_BS1
DDR_A_MA0
DDR_A_D37
DDR_A_D36
DDR_A_DM5
DDR_A_D47
DDR_A_D46
DDR_A_D49
DDR_A_D48
tt
8
7
6
5
M_ODT1
DDR_A_D45
DDR_A_D44
p:
RP30
1
2
3
4
DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_D39
DDR_A_D38
DDR_A_DQS#6
DDR_A_DQS6
RP29
DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_MA12
DDR_A_MA9
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_DQS#4
DDR_A_DQS4
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
+0.9V
DDR_A_D54
DDR_A_D50
56_8P4R_0.05
56_8P4R_0.05
DDR_A_D61
DDR_A_D60
RP33
RP34
DDR_A_DM7
DDR_A_BS0
DDR_A_MA10
DDR_A_CAS#
DDR_A_WE#
1
2
3
4
8
7
6
5
56_8P4R_0.05
1
2
3
4
8
7
6
5
DDR_A_MA13
M_ODT0
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_D59
DDR_A_D58
16,17,24 CLK_SMBDATA
16,17,24 CLK_SMBCLK
+3VS
56_8P4R_0.05
56_0404_4P2R_5%
RP11
DDR_CS1_DIMMA# 2
M_ODT1
1
3
4
DDR_A_MA11
CLK_SMBDATA
CLK_SMBCLK
2.2U_0603_6.3V4Z
+0.9V
A
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
+0.9V
DDR_CKE0_DIMMA
1
C171 C172
R117 56_0402_5%
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
FOX_ASOA426-M4R-TR
CONN@
SO-DIMM A
DDR_A_D6
DDR_A_D7
2006/02/13
2006/03/10
Deciphered Date
DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR0 9
M_CLK_DDR#0 9
DDR_A_D15
DDR_A_D14
DDR_A_D20
DDR_A_D21
PM_EXTTS#0 9
DDR_A_DM2
DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA
DDR_CKE1_DIMMA 9
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13
DDR_A_BS1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9
M_ODT0 9
DDR_A_D32
DDR_A_D33
DDR_A_DM4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
B
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D43
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 9
M_CLK_DDR#1 9
DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Compal Secret Data
Issued Date
0.1U_0402_16V4Z
VSS
/x
/
DDR_A_D18
DDR_A_D19
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
204
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
203
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_A_D16
DDR_A_D17
1
C150
C157
330U_D2E_2.5VM_R7
0.1U_0402_16V4Z
C149
0.1U_0402_16V4Z
C148
C156
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C155
C154
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C153
2.2U_0805_16V4Z
C147
2.2U_0805_16V4Z
C152
2.2U_0805_16V4Z
VSS
+1.8V
DDR_A_DM0
R116
10K_0402_5%
2
1
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D5
DDR_A_D0
R115
10K_0402_5%
2
1
DDR_A_D8
DDR_A_D9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C151
DDR_A_D2
DDR_A_D3
Layout Note:
Place near
JP3
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C146
DDR_A_DQS#0
DDR_A_DQS0
10 DDR_A_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
0.1U_0402_16V4Z
DDR_A_D4
DDR_A_D1
10 DDR_A_DQS[0..7]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.2U_0805_16V4Z
10 DDR_A_DM[0..7]
V_DDR_MCH_REF 9,16
JDIMM1
10 DDR_A_D[0..63]
Title

DDRII-SODIMM SLOT1
Rev
0.1
Montevina UMA
Date:
Sheet
1
15
of
46
+1.8V
+1.8V
10 DDR_B_DQS#[0..7]
V_DDR_MCH_REF
10 DDR_B_D[0..63]
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
DDR_CKE2_DIMMB
9 DDR_CKE2_DIMMB
DDR_B_BS2
10 DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
+0.9V
56_0404_4P2R_5%
RP24
DDR_CS3_DIMMB# 2
M_ODT3
1
3
4
RP36
1
2
3
4
8
7
6
5
DDR_B_D32
DDR_B_D37
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
4
3
M_ODT3
9 M_ODT3
tt
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
56_8P4R_0.05
56_0404_4P2R_5%
RP16
DDR_B_BS0
1
DDR_B_MA10
2
DDR_B_CAS#
DDR_CS3_DIMMB#
10 DDR_B_CAS#
9 DDR_CS3_DIMMB#
2
p:
RP35
4
3
C196
+0.9V
8
7
6
5
C195
C194
C193
C192
C191
C190
C189
C188
C187
C186
C185
C184
+0.9V
1
2
3
4
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
56_0404_4P2R_5%
RP14
DDR_B_MA3
1
DDR_B_MA1
2
yc
//
m
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
10 DDR_B_BS0
10 DDR_B_WE#
DDR_B_MA4
DDR_B_MA2
DDR_B_BS1
DDR_B_MA0
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D54
DDR_B_D55
56_8P4R_0.05
DDR_B_D60
DDR_B_D61
RP37
DDR_CKE3_DIMMB 1
R120
2
56_0402_5%
1
2
3
4
8
7
6
5
DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13
DDR_B_DM7
DDR_B_D63
DDR_B_D58
56_8P4R_0.05
56_8P4R_0.05
RP39
1
2
3
4
8
7
6
5
DDR_B_MA8
DDR_B_MA5
DDR_B_WE#
DDR_B_CAS#
1
C197
56_8P4R_0.05
FOX_AS0A426-N8RN-7F
CONN@
2006/02/13
SO-DIMM B
2006/03/10
Deciphered Date
M_CLK_DDR2
M_CLK_DDR#2
M_CLK_DDR2 9
M_CLK_DDR#2 9
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
PM_EXTTS#1 9
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D29
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
DDR_B_D27
DDR_CKE3_DIMMB
DDR_CKE3_DIMMB 9
DDR_B_MA14
0612 add
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_BS1 10
DDR_B_RAS# 10
DDR_CS2_DIMMB# 9
M_ODT2
DDR_B_MA13
M_ODT2 9
DDR_B_D36
DDR_B_D33
DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR3 9
M_CLK_DDR#3 9
DDR_B_DM6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D59
DDR_B_D62
R118
1
+3VS
10K_0402_5%
Title
Date:
DDR_B_DM1
Size
5
Compal Secret Data
Issued Date
C198
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
DDR_B_BS2
DDR_CKE2_DIMMB
DDR_B_MA9
DDR_B_MA12
DDR_B_D12
DDR_B_D13
R119
8
7
6
5
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_B_D6
DDR_B_D7
10K_0402_5%
1
2
3
4
CLK_SMBDATA
CLK_SMBCLK
15,17,24 CLK_SMBCLK
+3VS
RP38
VSS
om
p.
su
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
/x
/
DDR_B_DQS#2
DDR_B_DQS2
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
201
C181
C180
0.1U_0402_16V4Z
C179
0.1U_0402_16V4Z
C178
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C177
C183
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C176
2.2U_0805_16V4Z
C175
C174
2.2U_0805_16V4Z
2.2U_0805_16V4Z
202
+1.8V
DDR_B_DM0
DDR_B_D8
DDR_B_D9
DDR_B_D5
DDR_B_D4
DDR_B_D2
DDR_B_D3
Layout Note:
Place near
JP10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
C182
DDR_B_DQS#0
DDR_B_DQS0
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
C173
DDR_B_D0
DDR_B_D1
10 DDR_B_MA[0..14]
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2.2U_0805_16V4Z
10 DDR_B_DQS[0..7]
V_DDR_MCH_REF 9,15
JDIMM2
10 DDR_B_DM[0..7]

DDRII-SODIMM SLOT2
Document Number
Rev
0.1
Montevina UMA
Sheet
1
16
of
46
CLKSEL0
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
DOT_96
MHz
USB
MHz
100
33.3
14.318
96.0
48.0
266
133
100
33.3
14.318
96.0
48.0
200
100
33.3
14.318
96.0
48.0
166
100
33.3
14.318
96.0
48.0
333
100
33.3
14.318
96.0
48.0
100
100
33.3
14.318
96.0
48.0
100
33.3
1
2
1
2
R129
1K_0402_5%
R122
1
2
0_0805_5%
C213
18P_0402_50V8J
9
9
6
6
9 CLKREQ#_7
CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK
R126
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
1
1
1
U3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
20 CLK_PCI_ICH
2 39_0402_1% PCI2_1
PCI2_TME
T83
2 33_0402_1% 27_SEL
PCI_CLK3
2 33_0402_1% ITP_EN
R393 1
32 CLK_PCI_EC
R158
R161
73
@
R163
1K_0402_5%
C204
0.1U_0402_16V4Z
C205
0.1U_0402_16V4Z
C1496
47P_0402_50V8J
10U_0805_10V4Z
0.1U_0402_16V4Z
1
1
1
C209
C210
C211
C208
47P_0402_50V8J
1
1
C212
C1506
C1507
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
2
47P_0402_50V8J
+1.05VS_CK505
R167 1
R1101 1
22 CLK_48M_ICH
27 CLK_48M_CR
9 CLK_MCH_DREFCLK
9 CLK_MCH_DREFCLK#
thm_pad
CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9
CLKREQ#_6 26
CLK_PCIE_MCARD2 26
CLK_PCIE_MCARD2# 26
475_0402_1%
MiniCard_2(WLAN)
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRC_10#
SRC_10
CLKREQ_10#
SRC_11
SRC_11#
CLKREQ_11#
SRC_9#
SRC_9
CLKREQ_9#
VSS_SRC
CLKREQ_4#
SRC_4#
SRC_4
VDD_SRC_IO
CLKREQ_3#
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
H_STP_PCI#
H_STP_CPU#
H_STP_PCI# 22
H_STP_CPU# 22
R_CLKREQ#_10
R146
2 475_0402_1%
CLK_PCIE_MCARD0# 26
CLK_PCIE_MCARD0 26
CLKREQ#_10 26
MiniCard_0
R_CLKREQ#_9
R738
2 475_0402_1%
CLK_PCIE_LAN# 25
CLK_PCIE_LAN 25
CLKREQ#_9 25
LAN
R_CLKREQ#_4
R156
2 475_0402_1%
R_CLKREQ#_C
R162
2 475_0402_1%
CLKREQ#_4 26
CLK_PCIE_NCARD# 26
CLK_PCIE_NCARD 26
New Card
CLKREQ#_C 22
SLG8SP553VTR_QFN72_10x10
B
CLK_PCIE_SATA# 21
CLK_PCIE_SATA 21
SATA
CLK_PCIE_ICH# 22
CLK_PCIE_ICH 22
ICH
MCH_SSCDREFCLK# 9
MCH_SSCDREFCLK 9
NB_SSC (UMA)
+1.05VS_CK505
+3VS
3G_PLL
+1.05VS_CK505
+1.05VS_CK505
tt
NB
(UMA)
R133
FSA
2 22_0402_1%
2 22_0402_1%
p:
MCH_CLKSEL2 9
CKPWRGD/PD#
FS_B/TEST_MODE
VSS_REF
XTAL_OUT
XTAL_IN
VDD_REF
REF_0/FS_C/TEST_
REF_1
SDA
SCL
NC
VDD_PCI
PCI_1
PCI_2
PCI_3
PCI_4/SEL_LCDCL
PCIF_5/ITP_EN
VSS_PCI
+3VS_CK505
SI-1 Using USB_0 for CLK_48M_CR
+3VS
EMI
+3VS
R178
2.2K_0402_5%
22,26 ICH_SMBDATA
SB, MINI
PCI22,26 ICH_SMBCLK
@
R181
10K_0402_5%
Q3B
3
Q3A
R179
@ C1482
5P_0402_50V8C
@ C215
5P_0402_50V8C
C216
12P_0402_50V8J
@ C217
47P_0402_50V8J
@ C218
47P_0402_50V8J
@ C219
47P_0402_50V8J
2.2K_0402_5%
CLK_SMBDATA
2N7002DW-7-F_SOT363-6
CLK_SMBCLK
2N7002DW-7-F_SOT363-6
CLK_48M_CR
CLK_48M_ICH
CLK_14M_ICH
CLK_PCI_ICH
CLK_PCI_EC
CLK_DEBUG_PORT_1
A
R180
10K_0402_5%
2
R_CKPWRGD
FSB
2 33_0402_1% FSC
REF1
CLK_SMBDATA
T44
CLK_SMBCLK
15,16,24 CLK_SMBCLK
26 CLK_DEBUG_PORT_1
+3VS
@
R182
10K_0402_5%
Install C217,C218,C219 for WWAN

noise
PCI_CLK3
1
ITP_EN
1
0.1U_0402_16V4Z
1
C206
C207
yc
MCH_CLKSEL1 9
+3VS
R_CLKREQ#_7
2 475_0402_1%
R147
22 CLK_14M_ICH
R183
10K_0402_5%
2007/08/28
Issued Date
2
Compal Secret Data
2006/03/10
Deciphered Date
Title
PCI_CLK3
0.1U_0402_16V4Z
For WWAN
CLK_XTAL_OUT
CLK_XTAL_IN
@ R141
@ R142
R140
@
R143
1K_0402_5%
0=
SRC8/SRC8#
1=
0ITP/ITP#
= Enable DOT96 &
SRC1(UMA)
1 = Enable SRC0 &
27MHz(DIS)
C203
+3VS_CK505
22,42 VGATE
42 CLK_ENABLE#
22 CK_PWRGD
@
R174
0_0402_5%
ITP_EN
For WWAN
R_CLKREQ#_6
1
7 CPU_BSEL2
0.1U_0402_16V4Z
C214
18P_0402_50V8J
+3VS_CK505
1
2
R165
1K_0402_5%
C202
Place close to U3
2
10U_0805_10V4Z
FSC
+1.05VS_CK505
+VCCP
R164
1
2
10K_0402_5%
R171
1
2
0_0402_5%
0.1U_0402_16V4Z
14.318MHZ_16PF_7A14300083
48.0
NB
CPU
MCH_CLKSEL0 9
@
R157
0_0402_5%
C201
+VCCP
7 CPU_BSEL1
+VCCP
CLK_XTAL_IN
56_0402_5%
CLRP1
NO SHORT PADS
1
2
R150
1K_0402_5%
R154
1
2
0_0402_5%
0.1U_0402_16V4Z
+3VS_CK505
2
+VCCP
FSB
C200
Y1
@
R139
1K_0402_5%
R128
1
2
2.2K_0402_5%
R138
1
2
0_0402_5%
7 CPU_BSEL0
96.0
Routing the trace at least

10mil
CLK_XTAL_OUT
Reserved
R123
1
FSA
14.318
10U_0805_10V4Z
/x
/
400
C199
om
p.
su
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
0_0805_5%
+3VS_CK505
R121
1
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
CLKREQ_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_IO
SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
VDD_SRC
+3VS
VDD_48
USB_0/FS_A
USB_1/CLKREQ_A#
VSS_48
VDD_IO
SRC_0/DOT_96
SRC_0#/DOT_96#
VSS_IO
VDD_PLL3
LCDCLK/27M
LCDCLK#/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRC_2
SRC_2#
VSS_SRC
SRC_3
SRC_3#
FSA
CLKSEL1
//
m
FSB
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CLKSEL2
FSC
Size
Date:

Clock Generator CK505
Document Number
Rev
0.1
Montevina UMA
Sheet
1
17
of
46
BLUE
GREEN
RED
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
RED
GREEN
+5VS
VSYNC_G_A
D_VSYNC
2 0_0603_5%
1 @
C223
1
3
1
1
6
1 @
C224
5P_0402_50V8C
R187
2.2K_0402_5%
R186
2.2K_0402_5%
1
Q5A
5P_0402_50V8C
2N7002DW-7-F_SOT363-6
3
D_DDCCLK
R188
2.2K_0402_5%
3VDDCDA
3VDDCDA 11
3VDDCCL
3VDDCCL 11
Q5B
2N7002DW-7-F_SOT363-6
//
m
yc
R185
2.2K_0402_5%
D_DDCDATA
U5
SN74AHCT1G125GW_SOT353-5
+3VS
2
2
+CRTVDD
R189
1
D_HSYNC
2 0_0603_5%
5
1
CRT_VSYNC
11 CRT_VSYNC
R184
1
+3VS
+CRTVDD
om
p.
su
CRT_HSYNC
Place close to
JCRT1
16
17
SUYIN_070546FR015S263ZR
CONN@
U4
SN74AHCT1G125GW_SOT353-5
HSYNC_G_A
Y 4
P
OE#
11 CRT_HSYNC
C222
0.1U_0402_16V4Z
1
2
+CRTVDD
P
OE#
5
1
C221
0.1U_0402_16V4Z
1
2
/x
/
BLUE
+5VS
0.1U_0402_16V4Z
C220
JCRT1
W=40mils
1.1A_6VDC_FUSE
@ D7
DAN217T146_SC59-3
1
RB491D_SC59-3
F1
1
@ D6
D4
@ D5
+CRTVDD
DAN217T146_SC59-3
+RCRT_VCC
+5VS
DAN217T146_SC59-3
CRT Termination/EMI Filter
150_0402_1%
150_0402_1%
R197
2
1
h
R195
2
GREEN
L4
1
2
HLC0603CSCCR11JT_0603
BLUE
@ C225 @ C226 @ C227
10P_0402_50V8J
L3
1
2
C_BLU
10P_0402_50V8J
C_GRN
10P_0402_50V8J
RED
22P_0402_50V8J
L2
1
2
22P_0402_50V8J
C_RED
22P_0402_50V8J
150_0402_1%
R196
2
1
11 M_BLUE
tt
11 M_RED
11 M_GREEN
p:
C228 C229 C230
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

CRT Connector
Document Number
Rev
0.1
Montevina UMA
Sheet
E
18
of
46
LVDS CONN & USB Camera + Dig Mic

+LCDVDD
DDC2_CLK
DDC2_DATA
INV_PWM 32
BKOFF# 32
DDC2_CLK 11
DDC2_DATA 11
2
R1238
IO1
IO2 GND
USB20_N4
1
0_0402_5%
NB_BKLT_CTRL 11
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
R203
2.2K_0402_5%
2
G
0.1U_0402_16V4Z
R200
2
2
2N7002DW-7-F_SOT363-6
Q8A
4.7U_0805_10V4Z
6 2
1
C234
100K_0402_5%
C238
0.047U_0402_16V7K
Q8B
2N7002DW-7-F_SOT363-6
R201
100K_0402_5%
B+
@ C302
INVPWR_B+
@
L5
0_0805_5%
L6
1
2
FBMA-L11-201209-221LMA30T_0805
@ C303
//
m
R202
2.2K_0402_5%
DDC2_CLK
DDC2_DATA
DMIC_DAT
DMIC_CLK
EMI request
Avoid Panel display garbage after power on.
Must close JLVDS1pin 2426
+3VS
220P_0402_25V8J
2
2
2
2
2
2
@ C1399 1
@ C1400 1
@ C1401 1
@ C1402 1
@ C1504 1
@ C1505 1
C434
680P_0402_50V7K
EMI request.
PRTR5V0U2X_SOT143-4
C232
yc
VIN
11 ENAVDD
1
D61
Limited Current < 1A
+USB_CAM
+5VALW
LVDS_ACLK+
LVDS_ACLKDDC2_CLK
DDC2_DATA
LVDS_BCLK+
LVDS_BCLK-
DMIC_DAT 28
DMIC_CLK 28
+5VS
INV_PWM
1
0_0402_5%
0.1U_0402_16V4Z
BKOFF#
2
2
@ R1237
C231
C233
4.7U_0805_10V4Z
R727
1
100_0805_5%
ACES_88242-4001
CONN@
@ R245
10K_0402_5%
1
1
R199
1M_0402_5%
DMIC_DAT
DMIC_CLK
+3V_LOGO
USB20_P4
R198
100_0805_5%
LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-
+LCDVDD
LVDS_A2- 11
BKOFF#
LVDS_A2+ 11
LVDS_A1- 11
LVDS_A1+ 11
LVDS_A0- 11
LVDS_A0+ 11
LVDS_ACLK- 11
LVDS_ACLK+ 11
+3VS
Q7
SI2301BDS-T1-E3_SOT23-3
11
11
11
11
11
11
LVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2-
LVDS_A2LVDS_A2+
LVDS_A1LVDS_A1+
LVDS_A0LVDS_A0+
LVDS_ACLKLVDS_ACLK+
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
/x
/
LVDS_BCLK+
LVDS_BCLK-
11 LVDS_BCLK+
11 LVDS_BCLK-
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND
om
p.
su
+3VS
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
JLVDS1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
+5VALW
1
+LCDVDD
USB20_P4
USB20_N4
22 USB20_P4
22 USB20_N4
INVPWR_B+
C237
680P_0402_50V7K
1
2
680P_0402_50V7K
C235 C236
D
+LCDVDD
680P_0402_50V7K
+3VS
220P_0402_25V8J
EMI reserver
tt
USB Camera
+USB_CAM
+5VS
IN
GND
OUT
BYP
R1091
215K_0603_1%
1
SHDN
G916-390T1UF_SOT23-5
C1391
10U_0805_6.3V6M
2
R1093
100K_0402_1%
R440
0_0402_5%
1
U42
C1392
10U_0805_6.3V6M
p:
+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm +USB_CAM=1.25(1+R1091/R1093)
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

LCD CONN.
Document Number
Rev
0.1
Montevina UMA
Sheet
1
19
of
46
+3VS
2 8.2K_0402_5%
PCI_IRDY#
R278 1
2 8.2K_0402_5%
PCI_SERR#
R279 1
2 8.2K_0402_5%
PCI_PERR#
U12B
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
+3VS
R281 1
2 8.2K_0402_5%
PCI_PIRQA#
R283 1
2 8.2K_0402_5%
PCI_PIRQC#
R284 1
2 8.2K_0402_5%
PCI_PIRQD#
R286 1
2 8.2K_0402_5%
PCI_PIRQF#
R288 2
1 8.2K_0402_5%
PCI_PIRQH#
R292 1
2 8.2K_0402_5%
PCI_REQ2#
R293 1
2 8.2K_0402_5%
PCI_REQ3#
+3VS
R272 1
2 8.2K_0402_5%
PCI_DEVSEL#
R290 1
2 8.2K_0402_5%
PCI_REQ1#
R273 1
2 8.2K_0402_5%
PCI_STOP#
R276 1
2 8.2K_0402_5%
PCI_PLOCK#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
RP28
1
2
3
4
8
7
6
5
PCI_PIRQE#
PCI_PIRQB#
PCI_PIRQG#
PCI_REQ0#
J5
E1
J6
C4
PCI
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
PLTRST#
PCICLK
PME#
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PCI_REQ0#
PCI_GNT0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_GNT3#
D8
B4
D6
A5
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
C14
D4
R2
Place closely pin D4

CLK_PCI_ICH
PCI_IRDY#
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_RST# 32
H4
K6
F2
G2
PCI_SERR# 32
PLT_RST#
CLK_PCI_ICH
PCI_PME#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
@
R280
10_0402_5%
PLT_RST# 9,25,26
CLK_PCI_ICH 17
PCI_PME# 32
1
R291
2
0_0402_5%
@
C425
8.2P_0402_50V
ACCEL_INT 24
@R294
1
PCI_GNT0#
0
2
1K_0402_5%
1
1
SPI_CS#1
Boot BIOS Location
p:
PCI_GNT3#
Boot BIOS Strap

1
SPI
tt
PCI_GNT3#
Low= A16 swap override Enble

High= Default*
PCI
A16 swap override Strap

B
//
m
yc
8.2K_0804_8P4R_5%
F1
G4
B6
A7
F13
F12
E6
F6
PCI_FRAME#
R277 1
PCI_TRDY#
2 8.2K_0402_5%
/x
/
2 8.2K_0402_5%
R275 1
om
p.
su
R274 1
LPC
*
+3VALW
22 SPI_CS1#_R
SPI_CS1#_R
@ R295
1
PCI_GNT0#
@ R296
1
2
1K_0402_5%
2
1K_0402_5%
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title
Size
Date:

ICH9(1/4)-PCI/INT
Document Number
Rev
0.1
Montevina UMA
Sheet
1
20
of
46
ICH9M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
R300
1
R302
LAN100_SLP
ICH9M LAN100 SLP Strap

(Internal VR for VccLAN1.05 and VccCL1.05)
ICH_INTVRMEN
ICH_SRTCRST#
C426
0.1U_0402_16V4Z
@
R303
ICH_LAN100_SLP
@
R304
B22
A22
INTVRMEN
LAN100_SLP
R207
9 HDA_BITCLK_NB
28 HDA_SYNC_CODEC
33_0402_5%
33_0402_5%
1
2
R316
33_0402_5%
R208
R317
9 HDA_SYNC_NB
28,32 HDA_RST#_CODEC
33_0402_5%
33_0402_5%
R209
9 HDA_RST#_NB
1
1
1
33_0402_5%
2
2
28 HDA_SDIN0
9 HDA_SDIN2
28 HDA_SDOUT_CODEC
9 HDA_SDOUT_NB
R321
R204
33_0402_5%
33_0402_5%
1
1
2
2
PAD T55
PAD T56
P- HDD
SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0
SATA_TXP0
0.01U_0402_16V7K
C431
1
2
C433
1
2
SATA_TXN0
SATA_TXP0
Add 12p on HDA_SDOUT and HDA_SDOUT

Add 12p on HDA_BITCLK_CODE and HDA_BITCLK_NB
12P_0402_50V8J
12P_0402_50V8J
HDA_BITCLK_CODEC
C316 1
12P_0402_50V8J
HDA_BITCLK_NB
C67
12P_0402_50V8J
GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
AE7
HDA_RST#
HDA_SDIN0
HDA_SDIN2
AF4
AG4
AH3
AE5
HDA_SDOUT
AG5
SATA_TXN0_C
SATA_TXP0_C
AG8
AJ16
AH16
AF17
AG17
AH13
AJ13
AG14
AF14
LPC
RTC
B10
FWH4/LFRAME#
K3
LPC_FRAME#
LDRQ0#
LDRQ1#/GPIO23
J3
J1
N7
AJ27
DPRSTP#
DPSLP#
AJ25
AE23
FERR#
AJ26
CPUPWRGD
AD22
IGNNE#
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
Reserve SSC for EMI
R_H_FERR#
R310
H_PWRGOOD
AH27
H_STPCLK#
AG26
THRMTRIP_ICH#
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
H_DPRSTP# 7,9,42
H_DPSLP# 7
H_FERR#
2
56_0402_5%
H_FERR# 6
H_IGNNE# 6
H_INIT#
H_INTR
KB_RST#
H_NMI
H_SMI#
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
R308
56_0402_5%
H_DPRSTP#
2
0_0402_5%
H_PWRGOOD 7
H_IGNNE#
AF23
AF24
within 2" from R379
H_INIT# 6
H_INTR 6
KB_RST# 32
+VCCP
C
H_NMI 6
H_SMI# 6
R315
56_0402_5%
H_STPCLK# 6
R319
2 54.9_0402_1%
H_THERMTRIP# 6,9
placed within 2"

from ICH9M
AG27
AH11
AJ11
AG12
AF12
AH9
AJ9
AE10
AF10
AH18
AJ18
AJ7
AH7
SATA_TXN4_C
SATA_TXP4_C
0.01U_0402_16V7K
2
1 C428
2
1 C429
SATA_RXN4_C 24
SATA_RXP4_C 24
SATA_TXN4 24
SATA_TXP4 24
SATA_TXN4
SATA_TXP4
SATA_TXN5_C
SATA_TXP5_C
2
2
SATA_RXN5_C 30
SATA_RXP5_C 30
SATA_TXN5 30
SATA_TXP5 30
0.01U_0402_16V7K
SATA_TXN5
1 C430
SATA_TXP5
1 C432
0.01U_0402_16V7K
CLK_PCIE_SATA#
CLK_PCIE_SATA
R322
ODD
0.01U_0402_16V7K
e-SATA
De-feature disable
CLK_PCIE_SATA# 17
CLK_PCIE_SATA 17
1
2
24.9_0402_1%
Within 500 mils
ICH9-M ES_FCBGA676
SI-1 Remove SSC
R309
NMI
SMI#
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
+VCCP
PAD
GATEA20 32
H_A20M# 6
H_DPRSTP_R#
H_DPSLP#
AE22
AG25
L3
TP12
HDA_SDOUT
AF25
GATEA20
H_A20M#
INIT#
INTR
RCIN#
STPCLK#
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
T54
A20GATE
A20M#
THRMTRIP#
SATALED#
@ R306
1
2
56_0402_5%
LPC_FRAME# 26,32
Reserve cap on HDA_BITCLK for WWAN noise issue
p:
C66
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
AG7
AE8
H_DPSLP#
tt
C312 1
HDA_SDOUT_NB
D13
D12
E13
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
BATT1
HDA_SDOUT_CODEC
LAN_RXD0
LAN_RXD1
LAN_RXD2
HDARST#
0.01U_0402_16V7K
F14
G13
D14
HDA_BITCLK
HDA_SYNC
SATA_LED#
33 SATA_LED#
24
24
24
24
GLAN_COMP
LAN_RSTSYNC
K5
K4
L6
K2
om
p.
su
R312
28 HDA_BITCLK_CODEC
R311
24.9_0402_1%
1
2
R259
HDABITCLK 1
2
0_0402_5%
2
GLAN_CLK
CPU
+1.5VS
E25
C13
LAN / GLAN
@ R305
1
2
56_0402_5%
ICH_INTVRMEN
LAN100_SLP
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
/x
/
RTCRST#
SRTCRST#
INTRUDER#
IHDA
1U_0603_10V4Z
A25
F20
C22
yc
C427
ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#
SATA
CLRP2
SHORT PADS
+RTCVCC
H_DPRSTP#
LPC_AD[0..3] 26,32
RTCX1
RTCX2
//
m
R307
1
2
20K_0402_5%
R301
1
2
10K_0402_5%
+VCCP
U12A
C23
C24
KB_RST#
Low = Internal VR Disabled

High = Internal VR Enabled(Default)
ICH_RTCX1
ICH_RTCX2
GATEA20
R298
1
2
8.2K_0402_5%
+3VS
Low = Internal VR Disabled

High = Internal VR Enabled(Default)
1
R299
ICH_INTVRMEN
SM_INTRUDER#
0_0402_5%
2
1
R297
2
1M_0402_5%
2
330K_0402_5%
2
330K_0402_5%
2
180K_0402_5%
0_0402_5%
2
1
+RTCVCC
XOR CHAIN ENTRANCE STRAP:RSVD

+3VS
@
+RTCVCC
@ R325
1
@ R326
1
BATT1.1
HDA_SDOUT_CODEC
2
1K_0402_5%
ICH_RSVD
2
1K_0402_5%
ICH_RSVD 22
ICH_RTCX1
W=20mils
R329
1
W=20mils
2
D8
2
3
W=20mils
0_0402_5%
R328
1
A
ICH_RSVD HDA_SDOUT_CODEC
0
0
1
1
ICH_RTCX2
10M_0402_5%
C436
15P_0402_50V8J
0
1
0
1
32.768KHZ_12.5P_MC-146
2006/03/10
Deciphered Date
C435
PV for ESD
Title
JBATT1
1
2
3
4
0.1U_0402_16V4Z
1
2
GND
GND
ACES_85205-02001
CONN@

ICH9(2/4)_LAN,HD,IDE,LPC
Rev
0.1
Montevina UMA
Date:
W=20mils
2
1K_0402_5%
2.2U_0603_6.3V4Z
Compal Secret Data

2007/08/28
Issued Date
R330
1
C438
15P_0402_50V8J
DAN202U_SC70
Place near ICH9
C437
Y2
CR2032 RTC BATTERY
+3VL
Sheet
1
21
of
46
R331 1
R332 1
+3VALW
+3VS
Place closely pin

AF3 CLK_48M_ICH
2 2.2K_0402_5%
2 2.2K_0402_5%
R372
R374
R375
R376
R377
R378
R379
R373
R380
R381
1
2
100K_0402_5%
R225
32 EC_SCI#
32 EC_SMI#
@ R226
GPIO48
GPIO57
+3VS
GPIO49
R364
26 EXP_CPPE#
ICH_LOW_BAT#
ICH_PCIE_WAKE#
ICH_RI#
26
26
26
26
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
C445 1
C444 1
A20
TP11
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
PCIE_RXN1
PCIE_RXP1
2 0.1U_0402_16V4Z PCIE_C_TXN1
2 0.1U_0402_16V4Z PCIE_C_TXP1
ME_EC_CLK1
ME_EC_DATA1
GPIO10
EC_LID_OUT#
WLAN
26
26
26
26
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
C448 1
C449 1
PCIE_RXN3
PCIE_RXP3
2 0.1U_0402_16V4Z PCIE_C_TXN3
2 0.1U_0402_16V4Z PCIE_C_TXP3
LAN
25
25
25
25
GLAN_RXN
GLAN_RXP
GLAN_TXN
GLAN_TXP
C452 1
C453 1
2
2
EC_SMI#
GPIO14
Board ID
New Card
@ R747
10K_0402_5%
26
26
26
26
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
C450 1
C451 1
17/14
R383 1
30 BT_OFF
PCIE_RXN4
PCIE_RXP4
2 0.1U_0402_16V4Z PCIE_C_TXN4
2 0.1U_0402_16V4Z PCIE_C_TXP4
2 0_0402_5%
26 WXMIT_OFF#
R1183
R1184
R1185
R1186
WXMIT_OFF#
USB_OC#5 R1187
USB_OC#10 R1188
USB_OC#11 R1189
R1190
SPI_CS1#_R
E29
E28
F27
F26
C29
C28
D27
D26
D23
D24
F23
D25
E23
USB_OC#0
USB_OC#1
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11
USBRBIAS
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#0
+3VALW
S4_STATE#
G20
PM_PWROK
M2
R348 1
PERN1
PERP1
PETN1
PETP1
Within 500 mils
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
AG2
AG1
DPRSLPVR/GPIO16
B13
ICH_LOW_BAT#
R3
PWRBTN_OUT#
LAN_RST#
D20
RSMRST#
D22
R_EC_RSMRST#
CK_PWRGD
R5
CK_PWRGD
CLPWROK
R6
M_PWROK
R346
1
10K_0402_5%
2
PWRBTN_OUT# 32
R354 1
R355 1
2 100_0402_5%
2 10K_0402_5%
PERN3
PERP3
PETN3
PETP3
F24
B19
CL_DATA0
CL_DATA1
F22
C19
CL_VREF0
CL_VREF1
C25
A19
CL_RST0#
CL_RST1#
F21
D18
CL_RST#
A16
C18
C11
C20
XMIT_OFF
GPIO10
GPIO14
LAN_WOL_EN
CL_CLK0
+3VS
R360
CL_CLK0 9
CL_DATA0
CL_DATA0 9
C442
CL_VREF0_ICH
CL_VREF1_ICH
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
SPI
SPI_MOSI
SPI_MISO
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
3.24K_0402_1%
R363
453_0402_1%
NA lead free
+3VALW
R367
XMIT_OFF 26
C443
R370
1
+3VALW
V27
V26
U29
U28
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
Y27
Y26
W29
W28
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN1 9
DMI_RXP1 9
DMI_TXN1 9
DMI_TXP1 9
AB27
AB26
AA29
AA28
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
DMI_RXN2 9
DMI_RXP2 9
DMI_TXN2 9
DMI_TXP2 9
AD27
AD26
AC29
AC28
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
AF29
AF28
DMI_IRCOMP
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
CL_RST# 9
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
EC_RSMRST# 32
M_PWROK 9,32
CL_CLK0
CL_CLK1
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
4.7P_0402_50V8C
DPRSLPVR 9,42
100K_0402_5%
PERN2
PERP2
PETN2
PETP2
CK_PWRGD 17
B16
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
4.7P_0402_50V8C
R_EC_RSMRST# 38
SLP_M#
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
@ C441
D
PM_PWROK 9,32
2 0_0402_5%
PWRBTN#
BATLOW#
C10
PWROK
S4_STATE#/GPIO26
@ C440
DMI_RXN0 9
DMI_RXP0 9
DMI_TXN0 9
DMI_TXP0 9
3.24K_0402_1%
R368
453_0402_1%
PM_PWROK 2
D22
1
R_EC_RSMRST#
DMI_RXN3 9
DMI_RXP3 9
DMI_TXN3 9
DMI_TXP3 9
CLK_PCIE_ICH# 17
CLK_PCIE_ICH 17
R382
1
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
24.9_0402_1%
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9
30
30
30
30
30
30
27
27
19
19
26
26
30
30
30
30
26
26
26
26
Within 500 mils

+1.5VS
USB-0 Right side(with ESATA)

USB-1 Left side
USB-2 Left side
USB-3 Cardreader
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8
MiniCard(WWAN/WiMAX)
USB-9
Express card
A
USBRBIAS
USBRBIAS#
ICH9-M ES_FCBGA676
R384
22.6_0402_1%
2
1
2
110K_0402_5%
2
110K_0402_5%
2
110K_0402_5%
2
10K_0402_5%
1
2
110K_0402_5%
2
110K_0402_5%
2
110K_0402_5%
2
10K_0402_5%
1
2
10K_0402_5%
1
2
110K_0402_5%
2
110K_0402_5%
2
10K_0402_5%
J29
J28
K27
K26
GLAN_RXN
G29
GLAN_RXP
G28
0.1U_0402_16V4Z GLAN_TXN_C H27
0.1U_0402_16V4Z GLAN_TXP_C H26
R748
10K_0402_5%
R1179
R1180
R1181
R1182
N29
N28
P27
P26
L29
L28
M27
M26
2
1
VRMPWRGD
S4_STATE#
R746
10K_0402_5%
WAKE#
SERIRQ
THRM#
U12D
20 SPI_CS1#_R
USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4
CLKRUN#
ICH9-M ES_FCBGA676
WWAN
XDP_DBRESET#
@ R745
10K_0402_5%
1
R366
Low
High -->No
-->default
boot
LINKALERT#
STP_PCI#
STP_CPU#
D21
OCP#
AG19
CR_CPPE#
AH21
EC_SCI#_SB
1
2 0_0402_5%
AG21
EC_SMI#
A21
EC_SCI#_GPIO12
1
2 0_0402_5%
C12
C21
PAD T46
17/14
AE18
GPIO18
K1
GPIO20
AF8
CR_WAKE#
AJ22
DIS/UMA
A9
D19
PAD T47
CLKREQ#_C
L1
17 CLKREQ#_C
GPIO38
2
AE19
GPIO39
8.2K_0402_5%
AG22
GPIO48
@ R739 1
2
AF21
GPIO49
0_0402_5%
AH24
GPIO57
A8
R366 1
2 1K_0402_5%
SB_SPKR
M7
MCH_ICH_SYNC# AJ24
9 MCH_ICH_SYNC#
ICH_RSVD
B21
21 ICH_RSVD
AH20
AJ20
AJ21
6 OCP#
GPIO37
GPIO39
PAD T59
SMBALERT#/GPIO11
1
SLP_S3# 29,32
SLP_S4# 32
SLP_S5# 32
R353
GPIO36
+3VS
DIS/UMA
L4
VGATE
17,42 VGATE
GPIO21
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
1K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
+3VS
PM_CLKRUN#
A14
E19
SLP_S3#
SLP_S4#
SLP_S5#
10_0402_5%
T58 PAD
GPIO20
+3VS
28 SB_SPKR
R371
H_STP_PCI#
R_STP_CPU#
ICH_PCIE_WAKE# E20
SIRQ
M5
THERM_SCI#
AJ23
25,26 ICH_PCIE_WAKE#
32 SIRQ
32 THERM_SCI#
HDDHALT_LED#
+3VALW
R369
2 0_0402_5%
SYS / GPIO
R345
GPIO18
1
2
@ R365 10K_0402_5%
17 H_STP_PCI#
17 H_STP_CPU#
A17
C16
E16
G17
SLP_S3#
SLP_S4#
SLP_S5#
PMSYNC#/GPIO0
@ R343
10_0402_5%
R362
CR_WAKE#
EC_LID_OUT#
ICH_SUSCLK
SUSCLK
@ R342
@ R361
CR_CPPE#
32 EC_LID_OUT#
P1
SUS_STAT#/LPCPD#
SYS_RESET#
CLK_14M_ICH 17
CLK_48M_ICH 17
0.1U_0402_16V4Z
R359
EC_SCI#
M6
CLK_14M_ICH
CLK_48M_ICH
CLK14
CLK48
Place closely pin

H1 CLK_14M_ICH
HDDHALT_LED# 33
0.1U_0402_16V4Z
R358
R4
G19
PM_BMBUSY#
9 PM_BMBUSY#
H1
AF3
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
/x
/
R357
6 XDP_DBRESET#
@ R340
10K_0402_5%
GPIO21
HDDHALT_LED#
GPIO36
GPIO37
Direct Media Interface
R352
@ R339
10K_0402_5%
AH23
AF19
AE21
AD20
om
p.
su
R351
SUS_STAT#
XDP_DBRESET#
Power MGT
R350
PM_BMBUSY#
T57
MISC
GPIO
Controller Link
R349
PAD
CLKREQ#_C
yc
R356
clocks
PCI - Express
R344
RI#
//
m
R341
F19
p:
@ R338
ICH_RI#
SMB
tt
R337
D
+3VS
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
THERM_SCI#
1
@ R336
OCP#
R335
PM_CLKRUN#
R334
17,26 ICH_SMBCLK
17,26 ICH_SMBDATA
SIRQ
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
1
2
10K_0402_5%
1
2
8.2K_0402_5%
1
2
8.2K_0402_5%
R333
G16
A13
E17
C17
B18
SATA
GPIO
U12C
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

ICH9(3/4)_DMI,USB,GPIO,PCIE
Rev
0.1
Montevina UMA
Date:
Sheet
1
22
of
46
2
2.2U_0603_6.3V4Z
10U_0805_10V4Z
1
ICH_V5REF_RUN
0.1U_0402_10V6K
AC9
VCC1_5_A[17]
VCC1_5_A[18]
VCC1_5_A[19]
AC21
C483
0.1U_0402_16V4Z
1
C484
0.1U_0402_16V4Z
VCC1_5_A[21]
VCC1_5_A[22]
11mA
11mA
AC12
AC13
AC14
+1.5VS
2
VCC1_5_A[20]
G10
G9
+1.5VS
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
AJ5
VCCUSBPLL
T69
T70
A10
A11
VCCLAN1_05[1]
VCCLAN1_05[2]
A12
B12
R390
1
+1.5VS
VCCLAN3_3[1]
VCCLAN3_3[2]
23mA
CHB1608U301_0603
2
C487
2.2U_0603_6.3V4Z
10U_0805_10V4Z
C485
VCC_LAN1_05_INT_ICH_1
VCC_LAN1_05_INT_ICH_2
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
A27
4.7U_0805_10V4Z
2
D28
+1.5VS
D29
CHB1608U301_0603
E26
1
C488
E27
1
VCCGLANPLL
80mA
R391
1
C489
0316 change design
+3VS
2
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
1mA
A26
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCCL1_05
VCCCL1_5
19/78/78mA
VCCGLAN3_3
ICH9-M ES_FCBGA676
GLAN POWER
0.1U_0402_16V4Z
+3VS
USB CORE
AA7
AB6
AB7
AC6
AC7
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
1342mA
AC18
AC19
VCCSUS1_5[2]
212mA
AJ4
(DMI)
R212 @
0_0402_5%
T65
T66
A18
D16
D17
E22
R741
150_0402_1%
0.1U_0402_16V4Z
1
+3VALW
+1.5VS
C474
+3VALW
+1.5VALW
T67
VCCSUS1_5_ICH_2
T68
AF1
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
G22
G23
R740
2 180_0402_1%
0.1U_0402_16V4Z
1
AD8 VCCSUS1_5_ICH_1
F18
C473
0.1U_0402_16V4Z
AJ3
AC8
F17
0.1U_0402_16V4Z
C480
1U_0603_10V4Z
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
VCCSUS1_5[1]
ATX
C481
B
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
C479
+1.5VS
//
m
C477
10U_0805_10V4Z
1U_0603_10V4Z
C476
C478
1U_0603_10V4Z
+1.5VS
C475
VCCSUS1_05[1]
VCCSUS1_05[2]
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
ARX
+3VS
0.1U_0402_16V4Z
VCCSATAPLL
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
+1.5VS
VCCHDA
VCCSUSHDA
p:
C468
AJ19
C467
11mA
B9
F9
G3
G6
J2
J7
K7
+VCCP
0.1U_0402_16V4Z
0316 change design
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
+3VS
308mA
11mA
R389
1
2
CHB1608U301_0603
+1.5VS
AD19
AF20
AG24
AC20
C464
C466
0.1U_0402_10V6K
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
+VCCP
1
0.1U_0402_16V4Z
C472
AG29
AJ6
AC10
2mA
10U_0805_10V4Z
C471
20 mils
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
48mA
+1.5VS
C463
0.1U_0402_16V4Z
ICH_V5REF_SUS
AB23
AC23
C470
V_CPU_IO[1]
V_CPU_IO[2]
C461
C469
10_0402_5%
W23
Y23
0.1U_0402_16V4Z
D10
VCC_DMI[2]
0.1U_0402_16V4Z
R388
R29
R385
1
2
CHB1608U301_0603
0.01U_0402_16V7K
4.7U_0603_6.3V6M
+5VALW +3VALW
VCCDMIPLL
23mA VCC_DMI[1]
VCCPSUS
20 mils
C465
tt
VCCPUSB
22U_0805_6.3VAM
D9
VCCA3GP
R386
100_0402_5%
/x
/
C456
646mA
2mA
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
47mA
10U_0805_10V4Z
C460
V5REF_SUS
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1
1
C457
C455
+1.5VS_SB_B
1
1
+ C459
V5REF
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
AE1
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
1634mA
2mA
om
p.
su
ICH_V5REF_SUS
G3: 6uA
yc
VCCRTC
CORE
A6
VCCP_CORE
A23
ICH_V5REF_RUN
PCI
C458
220U_D2_4VM
+3VS
+5VS
U12E
U12F
20 mils
40 mils
R387
1
2
CHB1608U301_0603
+1.5VS
+VCCP
C454
0.1U_0402_16V4Z
C462
0.1U_0402_16V4Z
+RTCVCC
+3VALW
VCCCL1_05_ICH
C482
4.7U_0603_6.3V6M
T71
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
19/73/73mA
VCCCL3_3[1]
VCCCL3_3[2]
A24
B24
1 @
C486
1U_0603_10V4Z
+3VS
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
ICH9-M ES_FCBGA676
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

ICH9(4/4)_POWER&GND
Rev
0.1
Montevina UMA
Date:
Sheet
1
23
of
46
GND
GND
SATA_RXN0_C 21
SATA_RXP0_C 21
C493
+3VS
+3VS_ACL
D23
2
CLK_SMBCLK
U29
VDDIO absolute man

rating is VDD+0.1
+3VS_ACL_IO
R568
0_0402_5%
1
2
Vdd_IO
GND
Near CONN side.
C512
C513
C514
13
CLK_SMBDATA
SDO
12
Reserved
11
R570
0_0402_5%
1
2
Reserved
GND
GND
10
GND
INT 2
Vdd
INT 1
CLK_SMBDATA 15,16,17
ACCEL_INT 20
CS
LIS302DLTR_LGA14_3x5
2
R569
1
10K_0402_5%
//
m
+5VS
C515
SDA / SDI / SDO
yc
SATA_RXN4_C 21
SATA_RXP4_C 21
10U_0805_10V4Z
SATA_TXP4 21
SATA_TXN4 21
10U_0805_10V4Z
6
5
4
3
2
1
1 C510 SATA_RXN4_C
1 C511 SATA_RXP4_C
1U_0603_10V4Z
SATA_TXP4
SATA_TXN4
0.1U_0402_16V4Z
Placea caps. near ODD CONN.
om
p.
su
+5VS
0.01U_0402_16V7K
SATA_RXN4
2
SATA_RXP4
2
0.01U_0402_16V7K
CLK_SMBCLK 15,16,17
0011101b
14
+5VS
JODD
DP
V5
V5
MD
GND
GND
Near CONN side.
CD-ROM Connector
13
12
11
10
9
8
7
+3VS
+3VS_ACL
GND
A+
AGND
BB+
GND
OCTEK_SAT-22EH1G_RV
+3VS_ACL_IO
R564
0_0603_5%
1
2
C714
C492
C713
0.1U_0402_16V4Z
SATA_TXP0 21
SATA_TXN0 21
1 C494 SATA_RXN0_C
1 C495 SATA_RXP0_C
C491
+3VS_ACL
SCL / SPC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
0.01U_0402_16V7K
SATA_RXN0 2
SATA_RXP0 2
0.01U_0402_16V7K
ACCELEROMETER (ST)
/x
/
24
23
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
SATA_TXP0
SATA_TXN0
10U_0805_10V4Z
1
2
3
4
5
6
7
C490
CONN@
JHDD
GND
A+
AGND
BB+
GND
Pleace near HDD CONN (JP3)
+5VS
0.1U_0402_16V4Z
HDD Connector
10U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SUYIN_127382FR013GX09ZR
CONN@
PR@
ZZZ
PCB-MB
PCB-MB
PA@
ZZZ
tt
p:
Compal Secret Data
2007/08/28
Issued Date
2006/03/10
Deciphered Date
Title

HDD & CDROM
Rev
0.1
Montevina UMA
Date:
Sheet
1
24
of
46
LAN_DI
1
R695
2
R696
LAN_CS
2
+3V_LAN
3.6K_0402_5%
1
1K_0402_1%
LAN Conn.
9/17 RT suggestion: R696 change to 1K ohm
Place Close to Chip
JRJ45
R697
300_0402_5%
2
1
U44
LAN_ACTIVITY#
C241 2
1 0.1U_0402_16V7K PCIE_PTX_IRX_N2
21
22 GLAN_TXP
15
22 GLAN_TXN
16
17 CLK_PCIE_LAN
17 CLK_PCIE_LAN#
17
18
17 CLKREQ#_9
25
9,20,26 PLT_RST#
27
R688 1
2 2.49K_0402_1%
33
34
35
32
LAN_DO
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS
LED0
38
LAN_ACTIVITY#
MDIP0
MDIN0
MDIP1
MDIN1
NC
NC
NC
NC
2
3
5
6
8
9
11
12
LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-
LED3/EEDO
LED2/EEDI/AUX
LED1/EESK
EECS
HSON
HSIP
HSIN
RTL8102EL
REFCLK_P
REFCLK_M
CLKREQB
PERSTB
46
RSET
ISOLATEB
26
28
LANWAKEB
ISOLATEB
LAN_X1
LAN_X2
41
42
CKXTAL1
CKXTAL2
NC
48
VDDTX
DVDD12
DVDD12
DVDD12
DVDD12
19
30
36
13
10
NC
39
NC
VCTRL12D
44
45
VDD33
VDD33
29
37
AVDD33
NC
NC
1
40
43
+3VS
R215
1K_0402_1%
2
ISOLATEB
23
24
NC
NC
7
14
31
47
GND
GND
GND
GND
22
GNDTX
@
D20
PACDN042_SOT23~D
2
VCTRL12
R1162
0_0603_5%
1
2
R1177 0_0603_5%
+3V_LAN_IC 1
2
+3V_LAN
1
R218
2
10K_0402_5%
Q19
0.1U_0402_16V4Z
Close to Pin19
Close to Pin45
+EVDD12
C253
C254
C261
PR1-
PR1+
+3V_LAN
11
LANLED_LINK#
12
DETCET PIN2
10
SHLD1
15
PR2+
Green LED+
Green LEDFOX_JM36113-P1122-7F
CONN@
R698
300_0402_5%
LANGND
1
C271
0.1U_0402_16V4Z
C272
4.7U_0805_10V4Z
U46
1
2
3
4
5
6
7
8
RD+
RDCT
NC
NC
CT
TD+
TD-
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
RJ45_MIDI0+
RJ45_MIDI0RJ45_CT0
RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-
C257 1
C258 1
2 0.01U_0603_100V7-M RJ45_CT0_C
2 0.01U_0603_100V7-M RJ45_CT1_C
1
1
R693
75_0402_1%
2
2
RJ45_GND
R694
75_0402_1%
C259
Y3
@
C265
LAN_X1
@ 1
C262
2
C263
0.1U_0402_16V4Z
RJ45_MIDI0RJ45_MIDI0+
Close to Pin48
10U_0805_10V4Z
C264
10U_0805_10V4Z
0.1U_0402_16V4Z
C267
PR3+
X'FORM_ HD-024A
+LAN_VDD12
1U_0402_6.3V4Z
1U_0402_6.3V4Z
PR3-
1000P_1206_2KV7K
VCTRL12
C266
PR2-
tt
0.1U_0402_16V4Z
C252
0.1U_0402_16V4Z
C251
Close to Pin1,37,29
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C250
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C249
0.1U_0402_16V4Z
+LAN_VDD12
Close to Pin10,13,30,36
+3V_LAN
LAN_CT1
LAN_MDI1+
LAN_MDI1-
PR4+
16
DETECT PIN1
p:
2 0.01U_0402_16V7K
SHLD1
PR4-
//
m
1
32 LAN_POWER_OFF
+3V_LAN
2 0.01U_0402_16V7K
LAN_MDI0+
LAN_MDI0LAN_CT0
Yellow LED-
+LAN_VDD12
yc
+EVDD12
+LAN_VDD12
C248 1
Yellow LED+
RJ45_MIDI1+
C269
0.1U_0402_16V4Z
LAN_SK_LAN_LINK#
+3VALW
40 mils
8
C268
0.1U_0402_16V4Z
RJ45_MIDI1-
C247 1
@
C255
LANLED_LINK#
RTL8103EL-GR_LQFP48_7X7
R216
15K_0402_5%
LANLED_ACT#
VCTRL12A
14
T82
/x
/
22 GLAN_RXN
HSOP
+3V_LAN
LANLED_ACT#
20
1 0.1U_0402_16V7K PCIE_PTX_IRX_P2
C240 2
om
p.
su
22 GLAN_RXP
13
LAN_X2
25MHz_20pF_6X25000017
1
C244
C245
27P_0402_50V8J
2 27P_0402_50V8J
2
9/17 RT suggestion: C267 change to 1uF
Compal Secret Data
Issued Date
2007/08/28
2007/06/30
Deciphered Date
Title

RTL8102EL LAN
Custom
Montevina UMA
Date:
5
Rev
0.1
Sheet
1
25
of
46
+3VALW
+3VS_WLAN
R432
C568
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
1
0_0805_5%
1
C566
C569
C570
C571
R431
2
1
0_0805_5%
1
C572
2
4.7U_0805_10V4Z
47P_0402_50V8J
Reserve for WWAN
ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_6
30 CH_DATA
30 CH_CLK
17 CLKREQ#_6
CLK_PCIE_MCARD2#
CLK_PCIE_MCARD2
17 CLK_PCIE_MCARD2#
17 CLK_PCIE_MCARD2
0.1U_0402_16V4Z
PLT_RST#
SI-1 Connect PLT_RST# to JP7.A17

17 CLK_DEBUG_PORT_1
SIM card Connector

CONN@
JSIM
1
2
3
4
5
6
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
1
2
3
4
5 G1
6 G2
R11
1
+3VS
2 0_0402_5%
2 0_0402_5%
PCIE_C_RXN3
PCIE_C_RXP3
PCIE_TXN3
PCIE_TXP3
22 PCIE_TXN3
22 PCIE_TXP3
10K_0402_5%
CLKREQ#_6
2
R10
1
+3VS
7
8
R423 1
R425 1
22 PCIE_RXN3
22 PCIE_RXP3
UIM_CLK
1
C824 @
18P_0402_50V8J
+3VS_WLAN
10K_0402_5%
CLKREQ#_10
2
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
A21
A23
A25
A27
A29
A31
A33
A35
A37
A39
A41
A43
A45
A47
A49
A51
WAKE#
COEX1
COEX2
CLKREQ#
GND
REFCLKREFCLK+
GND
Reserved
Reserved
GND
PERn0
PERp0
GND
GND
PETn0
PETp0
GND
GND
+3.3Vaux
+3.3Vaux
GND
Reserved
Reserved
Reserved
Reserved
A53
GND
ACES_87212-06G0
UIM_PWR
JMINIB
ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_10
17 CLKREQ#_10
17 CLK_PCIE_MCARD0#
17 CLK_PCIE_MCARD0
@ R400
1
2
0_0603_5%
0.01U_0402_16V7K 4.7U_0805_10V4Z
+3VS
R418
+3VALW
2
32 WWAN_POWER_OFF
0.1U_0402_16V4Z
1 @
C1499
@
Q52
PA@
R419 1
1
R421
PA@
22 PCIE_RXN1
22 PCIE_RXP1
1
2
0_1206_5%
1 PA@
C575
0_0402_5%
2 PCIE_C_RXN1
2 PCIE_C_RXP1
0_0402_5%
PCIE_TXN1
PCIE_TXP1
22 PCIE_TXN1
22 PCIE_TXP1
47P_0402_50V8J
Reserve for WWAN
yc
+3VS_WWAN
//
m
New Card
+1.5VS_WLAN
W_DISABLE#
PERST#
+3.3Vaux
A20
A22
A24
GND
GND
XMIT_OFF# 2
PLT_RST#
@ R424 1
R426 1
A28
A30
A32
+1.5V
SMB_CLK
SMB_DATA
GND
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
D19
2 0_0805_5%
2 0_0805_5%
USB20_N5 22
USB20_P5 22
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V
A42
A44
A46
A48
WL_LED# 33
+1.5VS_WLAN
+3.3Vaux
A52
+3VS_WLAN
GND
A54
GND
GND
+3VS
C579 1
2 0.1U_0402_16V4Z
C580 1
2 0.1U_0402_16V4Z
2
4
17
+3VALW
9,20,25 PLT_RST#
32,35,40 SYSON
32,35,37,39 SUSP#
+3VALW
22 EXP_CPPE#
PLT_RST#
SYSON
20
SUSP#
@ R439 1
2 100K_0402_5%
10
EXP_CPPE#
9
18
1.5Vin
1.5Vin
3.3Vin
3.3Vin
1.5Vout
1.5Vout
AUX_IN
SYSRST#
SHDN#
11
13
+1.5VS_PEC
3
5
+3VS_PEC
15
+3V_PEC
tt
U16
12
14
3.3Vout
3.3Vout
AUX_OUT
OC#
PERST#
STBY#
NC
CPPE#
GND
WAKE#
COEX1
COEX1
CLKREQ#
B11
B13
REFCLKREFCLK+
B17
B19
Reserved
Reserved
B23
B25
B31
B33
B37
B39
B41
B43
B45
B47
B49
B51
+3VALW
+3VS_WLAN
+1.5VS_WLAN
SI-1 For PR
UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R
GND
GND
PERn0
PERp0
GND
GND
PETn0
PETp0
GND
GND
+3.3Vaux
+3.3Vaux
GND
Reserved
Reserved
Reserved
Reserved
+1.5VS_WLAN
UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R
PA@ D11
M_WXMIT_OFF# 2
PLT_RST#
@ R420 1
R422 1
WW_LED#_R
R1227
R1228
R1229
R1230
R1231
R1232
R1233
R1234
R1235
R1236
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PR@
PR@
PR@
PR@
PR@
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP
PA@
PA@
PA@
PA@
PA@
1
WXMIT_OFF# 22
2 0_0805_5% +3VALW
2 0_0805_5% +3VS_WWAN
+1.5VS_WLAN
WW_LED# 33
+3VS_WWAN
R436
R437
2 0_0402_5%
2 0_0402_5%
1
1
USB9USB9+
EXP_CPPE#
ICH_SMBCLK
ICH_SMBDATA
+1.5VS_PEC
+1.5VS_PEC
R438
1
2
0_0402_5%
+3V_PEC
PCIE_PME#_R
PERST#
CLKREQ#_4
EXP_CPPE#
17 CLKREQ#_4
16
22 PCIE_RXN4
22 PCIE_RXP4
22 PCIE_TXN4
22 PCIE_TXP4
CPUSB#
Close to
JEXP
RCLKEN
R12
2
M_WXMIT_OFF#
2
0_0402_5%
+1.5VS_WLAN
17 CLK_PCIE_NCARD#
17 CLK_PCIE_NCARD
PERST#
WW_LED#_R
2
0_0402_5%
XMIT_OFF# 1
PR@ R1226
USB20_N8 22
USB20_P8 22
+3VS_PEC
+3VS
UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R
+3VS_WWAN
ICH_SMBCLK
ICH_SMBDATA
17,22 ICH_SMBCLK
17,22 ICH_SMBDATA
ENE P2231NL E2 QFN 20P
internal pull high to 3.3Vaux-in

EC need setting at Hi-Z & output Low
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
B38
B40
B42
B44
B46
B48
B50
B52
+3.3Vaux
GND
+1.5V
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
GND
W_DISABLE#
PERST#
+3.3Vaux
GND
+1.5V
SMB_CLK
SMB_DATA
GND
USB_DUSB_D+
GND
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V
GND
+3.3Vaux
WL_LED#
1
PR@ R1225
QUASA_CA0416-092N21
19
8
GND
22 USB20_N9
22 USB20_P9
p:
+1.5VS
C576
1
2 0.1U_0402_16V4Z
B1
B3
B5
B7
XMIT_OFF 22
ICH_SMBCLK
ICH_SMBDATA
A36
A38
USB_DUSB_D+
LPC_FRAME# 21,32
LPC_AD3 21,32
LPC_AD2 21,32
LPC_AD1 21,32
LPC_AD0 21,32
Near to Express Card slot.
CONN@
JEXP
Express Card Power Switch
+3VS_WLAN
A6
A8
A10
A12
A14
A16
GND
om
p.
su
+3VS_WWAN
2
1 PA@
C574
A2
+1.5V
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
+3.3Vaux
QUASA_CA0416-092N21
@ R750
1
2 UIM_DATA
47K_0402_5%
+3VS_WWAN
1 PA@
C573
JMINIA
+1.5VS
@
C1498
47P_0402_50V8J
Mini Card Slot ---WLAN,WWAN
Reserve for WWAN
+1.5VS_WLAN
0.01U_0402_16V7K
4.7U_0805_10V4Z
+3VS
1 @
C1497
C567
/x
/
+3VALW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
+3VS_PEC
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
C577
0.1U_0402_16V4Z
C578
4.7U_0805_10V4Z
+1.5VS_PEC
C581
0.1U_0402_16V4Z
C582
4.7U_0805_10V4Z
+3V_PEC
GND
GND
SANTA_130801-5_RT
CLKREQ#_4
C583
0.1U_0402_16V4Z
C584
4.7U_0805_10V4Z
10K_0402_5%
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

WLAN, WWAN, New Card
Document Number
Rev
0.1
Montevina UMA
Sheet
E
26
of
46
+3VS
D
+VCC_4IN1
R1102
100K_0402_5%
0_0402_5%
RST#
1
2
R1105
499K_0402_1%~D
@
17 CLK_48M_CR
2
1
3
7
9
11
33
0.1U_0402_16V4Z
1 C1411
RST#
MODE SEL
R1115
0_0402_5%
1
2
XTLI
2
2
@ C1415
6P_0402_50V8J
0.1U_0402_16V4Z
22 USB20_N3
22 USB20_P3
1
USB20_N3
USB20_P3
CR_LED#
C1409
1U_0603_10V4Z
1
2
AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3
8
44
45
47
48
3V3_IN
RST#
MODE_SEL
XTLO
XTLI
4
5
14
DM
DP
GPIO0
SI-1 Delete Crystall layout location
SI-1 Change LED type

PA@
D54
R1107
1
1.2K_0402_5%
CR_LED#
HT-110TW_WHITE
6.19K_0402_1%
White
MODE SEL
R1111
RREF
12
32
DGND
DGND
VREG
MS_D4
NC
10
22
30
XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
MS_INS#_SP9
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI
43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18
XTAL_CTR
MS_D5
13
24
EEDO
EECS
EESK
SD_CMD
15
16
17
36
D64
2
1
HT-110TW_WHITE
PR@
@ C1412
47P_0402_50V8J
@ R1110
10K_0402_5%
6
46
+5VS
2
0_0402_5%
AGND
AGND
RTS5159E-GR_LQFP48_7X7
Card Reader Connector

CONN@
JREAD1
XD_CLE
XDCE#
XD_ALE
XD_RE#_SDD2
XDWE#_SDD3
XDRDY
XDWP#_SDD4
XDD0_SDD5
XDD1
XDD7_SDD6_MSD3
MSINS#
XDD2_SDD7_MSD2
XDD6_SDD0_MSD0
XDD3_MSD1
XDD5_MSBS
XDD4_SDD1
SDCD#
SDWP
XDCD#
R1112
1
XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7
MSCLK
R1106
SDCLK
R1109
XDWE#_SDD3
XDWP#_SDD4
XD_ALE
XDCD#
XDRDY
XD_RE#_SDD2
XDCE#
XD_CLE
34
33
35
40
39
38
37
36
XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE
11
31
7IN1 GND
7IN1 GND
41
42
7 IN 1 CONN
SD-VCC
MS-VCC
21
28
SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW
20
14
12
30
29
27
23
18
16
25
1
SDCLK
XDD6_SDD0_MSD0
XDD4_SDD1
XD_RE#_SDD2
XDWE#_SDD3
XDWP#_SDD4
XDD0_SDD5
XDD7_SDD6_MSD3
XDD2_SDD7_MSD2
SDCMD
SDCD#
SD-WP-SW
SDWP
MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
26
17
15
19
24
22
13
MSCLK
XDD6_SDD0_MSD0
XDD3_MSD1
XDD2_SDD7_MSD2
XDD7_SDD6_MSD3
MSINS#
XDD5_MSBS
+VCC_4IN1
7IN1 GND
7IN1 GND
TAITW_R015-B10-LM
SDCMD
1
10P_0402_50V8J
@ C1414
tt
p:
//
m
R1114
@ 10_0402_5%
10P_0402_50V8J
@ C1413
2
0_0402_5%
1
2
0_0402_5%
32
10
9
8
7
6
5
4
SDCLK
R1113
@ 10_0402_5%
XD-VCC
XDD0_SDD5
XDD1
XDD2_SDD7_MSD2
XDD3_MSD1
XDD4_SDD1
XDD5_MSBS
XDD6_SDD0_MSD0
XDD7_SDD6_MSD3
0_0402_5%
2
+3VS
MSCLK
+VCC_4IN1
/x
/
0.1U_0402_16V4Z
1
1
C1407
C1408
1
R1104
U47
C1406
1U_0603_16V6K
+3VS
C1410
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
C1404
1
2
+3VS
om
p.
su
2
1
1U_0402_6.3V6K
C1403
0.1U_0402_16V4Z
C1405
yc
R1103
2
Compal Secret Data
Issued Date
2007/08/28
Deciphered Date
2006/10/06
5
Title

USB CardReader&CONN

Custom
Date:
Rev
0.1
Montevina UMA

1
Sheet
27
of
46
CODEC POWER
300mA
R1118
R1122
0_0603_5%
1
3
HDA_BITCLK
HDA_SDI
HDA_SDO
HDA_SYNC_CODEC
HDA_SYNC
HDA_RST#
19 DMIC_CLK
19 DMIC_DAT
22_0603_1%
2
2
0_0603_5%
30
29
SENSE_A
SENSE_B
10
23
PORT_A_L
PORT_A_R
26
27
PORT_B_L
PORT_B_R
VREFOUT_B
13
14
20
MIC_EXTL
MIC_EXTR
VREFOUT_B
PORT_C_L
PORT_C_R
VREFOUT_C
15
16
21
MIC_INL
MIC_INR
VREFOUT_C
DMIC_CLK
DMIC0/GPIO1
PORT_E_L
PORT_E_R
PC_BEEP/MONO
SPDIF_OUT_0
SPDIF_OUT_1/GPIO7
EAPD/GPIO0/SPDIF_OUT 0 or 1
CAP2
VREFFILT
R1128 2
@ C1428 1
SENSEA
1 100K_0402_5%
+VDDA_CODEC_R
1000P_0402_50V7K
HP_IN_L
HP_IN_R
C1430
1
2 2.2U_0603_6.3V6K
1
2 2.2U_0603_6.3V6K
11
12
9
MONO_INR
2
0.1U_0402_16V7K
1
C1434
2
1000P_0402_50V7K
2
1000P_0402_50V7K
2
1000P_0402_50V7K
C1481
MIC_IN_L
2
2.2U_0603_6.3V6K
1
C1432
MIC_IN_L 29
Internal SPKR.
MIC_IN_R
2
2.2U_0603_6.3V6K
1
C1433
R1133 47K_0402_5%
2
1
MONO_IN
MIC_IN_R 29
R1134 10K_0402_5%
2
1
+VDDA_CODEC
C1435
PV-1 For EMI

MIC_EXTR
1
C1459
0.1U_0402_16V7K
R1135
22 SB_SPKR
Q10A
2N7002DW-7-F_SOT363-6
D58
PSOT24C_SOT23-3
C1437
LINE_OUT_L 29
LINE_OUT_R 29
Internal MIC
Q10B
5
4
090212 For PC Beep Noise
C1480
1
Jack MIC
tt
C1479
1
HP Jack
MIC_EXT_L 29
MIC_EXT_R 29
p:
C1478
1
HP_DET# 29
EXTMIC_DET# 29
2 1000P_0402_50V7K
10U_0805_10V4Z
//
m
18
33
92HD75B1X5NLGXYAX8 QFN 32P 1.5V CODEC
MIC_EXTL
22
19
1U_0603_10V4Z
AVSS
TPAD
C1429
+VDDA_CODEC_R
2 2.49K_0402_1%
2 39.2K_0402_1%
2 20K_0402_1%
1
1
1
10K_0402_5%
DVSS
R1124
R1125
R1126
HP_IN_L 29
HP_IN_R 29
MIC_EXT_L
MIC_EXT_R
LINE_OUT_L
LINE_OUT_R
24
25
C1436
MIC_IN_L
C1431
0.1U_0402_16V7K
32
28
31
EAPD_CODEC
32 EAPD_CODEC
17
PORT_D_L
PORT_D_R
C1516
R1132
1
1
R1178
AVDD
4.7K_0402_5%
DVDD_CORE
SI-1 For EMI request
MIC_IN_R
/x
/
HDA_SDOUT_CODEC
HDA_RST#_CODEC
4.7K_0402_5%
0.01U_0402_16V7K
HDA_RST#_CODEC
1
R1120
4.7K_0402_5%
1U_0603_10V4Z
R1121
21 HDA_SDOUT_CODEC
DVDD_LV
C1419 1
2N7002DW-7-F_SOT363-6
HDA_BITCLK_CODEC
33_0402_5%
R1130 1
2 HDA_SDIN0_CODEC
21 HDA_SYNC_CODEC
1U_0603_10V4Z
R1119
21 HDA_SDIN0
U49
1
21 HDA_BITCLK_CODEC
R1239
4.7K_0402_5%
1U_0603_10V4Z
R1117
2
1
1K_0402_5%
C1423
2
0.1U_0402_16V7K
C1422
1
10U_0805_10V4Z
1U_0603_10V4Z
C1426
om
p.
su
C1425
+1.5VS
MIC_EXT_R
+VDDA_CODEC_R
VREFOUT_C
MIC_EXT_L
C1424
0.1U_0402_16V7K
PV-1 ESD request
4.7K_0402_5%
yc
+3VS
C1418 1
R1116
2
1
0_0402_5%
VREFOUT_B
+VDDA_CODEC
(4.75V(4.56~4.94V))
SI-1 Delete CODEC POWER IC
R1123
BLM18BD601SN1D_0603
2
1 +3VS_HDA
2
1000P_0402_50V7K
R1174
1
R1175
1
R1176
1
2
0_0402_5%
2
0_1206_5%
2
0_1206_5%
GNDA 29
GND
GNDA
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Codec_IDT9275B
Date:
Rev
0.1
Montevina UMA
Sheet
E
28
of
46
JSPK1
SPKRSPKR+
SPKLSPKL+
AMP. FOR INTERNAL SPEAKER

GAIN1
GAIN0
R1136 1
R1137 1
R1138 1
R1139 1
2
2
2
2
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
Av(inv)
SPK_RSPK_R+
SPK_LSPK_L+
1
2
3
4
1
C1438
C1439
C1440
5
6
C1441
SPGND
21
SPGND
ROUT+
20
SPKR+
ROUT-
19
SPKR-
SPVDD
18
SPVDD
HPVDD
17
HP_OUTL
SI-1 Add JSPK2 for PA

2
MV-1 For ESD request, close to JMIC2
0.1U_0402_16V4Z
+5VS
D57
PSOT24C_SOT23-3
INTMIC IN
28 MIC_IN_L
R1211
0_0402_5%
CONN@
JMIC2
1U_0603_10V4Z
1
R1153
0_0805_5%
1
1
2
28 MIC_IN_R
//
m
1
2
C1458
1U_0603_10V4Z
2
1U_0603_10V4Z
GND
GND
ACES_88231-02001
+3VS
yc
16
15
14
C1454
LOUT-
HP_OUTR
HPVSS
SPKL-
1U_0603_10V4Z
1
2
100K_0402_5%
1
1
2
3
4
EC_MUTE# 32
R1151
@ C1453
1
2
SPKR_LIN-
SPK_LSPK_L+
D56
PSOT24C_SOT23-3
22
3
HP_EN
330P_0402_50V7K
SPKR_LIN+
1
C1461
CONN@
JSPK2
/x
/
2 1U_0603_10V4Z
om
p.
su
23
GND1
GND2
E&T_3806-F04N-02R
CONN@
HP_IN_L 28
HP_IN_R 28
SLP_S3# 22,32
C1455
HP_INR
25
REG_EN
HP_INL
27
26
HP_INL
HP_INR
GAIN0
29
GAIN1
TML
GAIN1
24
SPKR_EN#
LOUT+
C1449
BYPASS
SPKR_RIN-
HP_IN_L
HP_IN_R
U50
TPA6047A4RHBR QFN 32P
SPKR_RIN+
D55
PSOT24C_SOT23-3
@ R1147
1
2
100K_0402_5%
SPKL+
10U_0805_10V4Z
2
2 2.2U_0805_10V6K
2.2U_0805_10V6K
CPVSS
C1456
R1152
0_0805_5%
1
1
1
C1446
C1447
SPEAKER
9/20 SP02000CW00
10U_0805_10V4Z
2
330P_0402_50V7K
330P_0402_50V7K
10U_0805_10V4Z
2
1U_0603_10V4Z
2
0.1U_0402_16V7K
2
C1N
+5VS
0_0402_5%
LINE_L_OUTR
1
0.47U_0402_6.3V6K
CPVDD
28 LINE_OUT_L
0_0402_5%
LINE_R_OUTR
1
0.47U_0402_6.3V6K
1
C1451
2
0.47U_0402_6.3V6K
R1148
LINE_C_OUTR
1
2
C1450
2
0.47U_0402_6.3V6K
R1150
LINE_C_OUTL
1
2
C1452
2
C1457
C1448
2
28 LINE_OUT_R
2
R1144
1
2
0_0603_5%
+VDDA_CODEC_IC
0_0402_5%
2 GAIN1
0_0402_5%
2 GAIN0
33
31
1
R1145
GAIN0
@ R1143
C1443
1
C1444
1
C1445
1
C1442 1U_0603_10V4Z
28
2
100K_0402_5%
21.6dB
Close to Pin29
SGND
1
R1142
C1P
2
100K_0402_5%
10
1
@ R1141
REG_OUT
V 15.6dB
TPA6047 LDO OUTPUT 4.7V

+VDDA_CODEC
R1140
0_0805_5%
2
1
32
+5VS
+5VS
13
12dB
12
30
2
330P_0402_50V7K
VDD
10dB
CPGND
11
1
2
3
4
3
4
1
2
GND
GND
ACES_88231-02001
HP_OUTL
HP_OUTR
tt
p:
SI-1 Add Audio board connector
Audio connector
JAUDIO
28 MIC_EXT_R
28 MIC_EXT_L
HP_OUTL
HP_OUTR
SI-1 Change IR1 to SCR00000E00

+5VL
1
2
3
4
5
6
7
8
9
10
MIC_EXT_R
MIC_EXT_L
28 EXTMIC_DET#
28 HP_DET#
EXTMIC_DET#
HP_DET#
Consumer IR
1
2
3
4
5
6
7
8
9
10
R1158
100_0805_5%
11
12
IR1
1
32 CIR_IN
CIR_IN
VCC
GND
4
C1466
Vout
GND
IRM-V536/TR1_3P
Compal Secret Data
4.7U_0805_10V4Z
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
AMP & Audio Jack
Date:
GND1
GND2
ACES_87213-1000G
CONN@
Rev
0.1
Montevina UMA
Sheet
E
29
of
46
Right side USB Power Switch
Right side ESATA/USB combination Connector
+5VALW
USB_VCCC
USB_VCCC
U41
C1381
TPS2061IDGNR_MSOP8
2
4.7U_0805_10V4Z
1
+
2
JESAT
C1383
1000P_0402_50V7K
USB_EN#
W=100mils
8
7
6
5
OUT
OUT
OUT
OC#
C1382
0.1U_0402_16V4Z
GND
IN
IN
EN#
C1380
150U_B_6.3VM_R40M
1
2
3
4
R1080 1
R1081 1
22 USB20_N0
22 USB20_P0
2 10K_0402_5%
1 0.01U_0402_16V7K SATA_RXN5
1 0.01U_0402_16V7K SATA_RXP5
C1385 2
C1384 2
+5VALW
D45
/x
/
4
VIN
IO1
IO2 GND
USB20_N0_R
D46
+5VALW
SATA_TXN5
om
p.
su
PRTR5V0U2X_SOT143-4
Finger printer
GND
GND
GND
GND
TYCO_1759576-1
CONN@
USB20_P0_R
GND
A+
ESATA
AGND
BB+
GND
12
13
14
15
+5VALW
USB
VBUS
DD+
GND
5
6
7
8
9
10
11
SATA_TXP5
SATA_TXN5
21 SATA_TXP5
21 SATA_TXN5
21 SATA_RXN5_C
21 SATA_RXP5_C
R1083
1
2
3
4
USB20_N0_R
USB20_P0_R
2 0_0402_5%
2 0_0402_5%
VIN
IO1
IO2 GND
SATA_TXP5
PRTR5V0U2X_SOT143-4
BT Connector
JBT
10
R628
0_0805_5%
1
0.1U_0402_16V4Z
D30
IO1
IO2 GND
USB20_P7_R
@
+5VALW
USB20_N6_R
1
2
3
4
GND
GND
+3VS
2
1
USB20_P6_R
+3VAUX_BT
0_0603_5%
Q105
@
1
2
0_0603_5%
R236
C1386 @
1U_0603_10V4Z
0.1U_0402_16V4Z
R1090
100K_0402_5%
C1387
22 BT_OFF
R1092 1
2 10K_0402_5%
C1388
0.01U_0402_16V7K
USB cable connector for Right side
IO1
IO2 GND
PRTR5V0U2X_SOT143-4
+3VALW
p:
PRTR5V0U2X_SOT143-4
VIN
P-TWO_161011-04021
D47
R235
1
VIN
USB20_P6 22
USB20_N6 22
BT_LED 33
CH_DATA 26
CH_CLK 26
1K_0402_5%
1K_0402_5%
2
2
USB20_N7_R
1 0_0402_5%
1 0_0402_5%
2
2
+5VALW
R1084
R1085
@ R1086 1
@ R1087 1
2
B
+3VAUX_BT
USB20_P6_R
USB20_N6_R
ACES_87213-0800G
CONN@
tt
C756
1
2
3
4
5
6
8
7
6
5
4
3
2
1
1
+3VS_FP
2 0_0402_5% USB20_N7_R
2 0_0402_5% USB20_P7_R
R634 1
R635 1
22 USB20_N7
22 USB20_P7
//
m
CONN@
JFPR
yc
+3VS
GND 8
7
6
5
4
3
2
GND 1
C1389
2
4.7U_0805_10V4Z
C1390
1
2
0.1U_0402_16V4Z
JUSB
+5VALW
32 USB_EN#
22 USB20_N2
22 USB20_P2
22 USB20_N1
22 USB20_P1
USB_EN#
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND1
GND2
ACES_87213-1000G
CONN@
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

USB, BT, eSATA
Document Number
Rev
0.1
Montevina UMA
Sheet
1
30
of
46
SPI ROM
+3VL
U27
20mils
C712
0.1U_0402_16V4Z
32 SPI_CLK
32 FWR#
1
R553
1
R554
1
R556
VCC
2
32 FSEL#
SPI_FSEL#
2
10_0402_5%
SPI_CLK_R
2
10_0402_5%
SPI_FWR#
2
10_0402_5%
VSS
HOLD
SPI_SO 1
R555
FRD#
2
0_0402_5%
FRD# 32
WIESON G6179 8P SPI
R231
SPI_CLK_R 2
SPI_FWR#
R232
2
C308
2
22P_0402_50V8J
33_0402_5%
22P_0402_50V8J
33_0402_5%
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH

WIESO_G6179-100000_8P
/x
/
33_0402_5%
C307
2
C309
2
om
p.
su
R230
SPI_FSEL# 2
22P_0402_50V8J
//
m
yc
EMI request
tt
p:
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

BIOS ROM
Document Number
Rev
0.1
Montevina UMA
Sheet
1
31
of
46
+1.5VS
C301
+3VL_EC
+3VS
C715
C716
C717
C718
+3VL
C719
2
2
1000P_0402_50V7K
+3VL_EC
R572
1
+EC_AVCC
2
0_0805_5%
15P_0402_50V8J
17 CLK_PCI_EC
20 PCI_RST#
2
47K_0402_5%
R578
1
0.1U_0402_16V4Z
2
C721
22 EC_SCI#
1
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
JOPEN
+3VALW
+3VL
+3VS
1
1
R713
100K_0402_5%
@ R124
10K_0402_5%
R583
10K_0402_5%
R721
10K_0402_5%
AD
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
LID_SW#
TP_BTN#
BATT_TEMP
BATT_OVP
ADP_I
ADP_ID
TP_BTN#
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
FAN_SET
VCTRL
IREF
AC_SET
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
EC_MUTE#
USB_EN#
I2C_INT
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
PS2 Interface
33,36
33,36
6
6
SPI Flash ROM
C325
0.1U_0402_16V4Z
CRY2
Y5
NC
EMI request
NC
OSC
OSC
CRY1
@ R233 2
+EC_AVCC
@ C795 1
2 100P_0402_50V8J
DIM_LED 35
ACOFF 37
KSO13
@ C796 1
2 100P_0402_50V8J
KSO12
@ C797 1
2 100P_0402_50V8J
KSO3
@ C798 1
2 100P_0402_50V8J
KSO6
@ C799 1
2 100P_0402_50V8J
KSO8
@ C800 1
2 100P_0402_50V8J
KSO7
@ C801 1
2 100P_0402_50V8J
KSO4
@ C802 1
2 100P_0402_50V8J
KSO2
@ C803 1
2 100P_0402_50V8J
KSI0
@ C804 1
2 100P_0402_50V8J
KSO1
@ C805 1
2 100P_0402_50V8J
KSO5
@ C806 1
2 100P_0402_50V8J
KSI3
@ C807 1
2 100P_0402_50V8J
KSI2
@ C808 1
2 100P_0402_50V8J
KSO0
@ C809 1
2 100P_0402_50V8J
KSI5
@ C810 1
2 100P_0402_50V8J
KSI4
@ C811 1
2 100P_0402_50V8J
KSO9
@ C812 1
2 100P_0402_50V8J
KSI6
@ C813 1
2 100P_0402_50V8J
KSI7
@ C814 1
2 100P_0402_50V8J
KSI1
@ C815 1
2 100P_0402_50V8J
0.01U_0402_16V7K
ECAGND
2
EC_MUTE# 29
USB_EN# 30
I2C_INT 33
R582
+5V_TP
R579 1
R580 1
2 10K_0402_5%
2 10K_0402_5%
TP_CLK 33
TP_DATA 33
2 0_0402_5%
AC_LED# 36
R227
R228
R229
1
1
1
2
2
2
L30
0_0603_5%
73
74
89
90
91
92
93
95
121
127
2 10K_0402_5%
CIR_IN
VCC1_PWRGD
FSTCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN
V18R
124
KB926QFD2_LQFP128_14X14
SLP_S4#
ENBKL
EAPD_CODEC
THERM_SCI#
SUSP#
PWRBTN_OUT#
NMI_DBG#
FRD# 31
FWR# 31
SPI_CLK 31
FSEL# 31
SPI_CLK
1
BKOFF# 19
M_PWROK 9,22
TP_LED# 33
R254
1
NMI_DBG#
CONN.( TYPE "D"

KB)
CONN@
JKB
SLP_S4# 22
ENBKL 11
EAPD_CODEC 28
THERM_SCI# 22
SUSP# 26,35,37,39
PWRBTN_OUT# 22
C724
4.7U_0603_6.3V6K
14" INT_KBD
PM_PWROK 9,22
100_0402_5%
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1
+3VL
ADP_ID
For C
Revision
C327
22P_0402_50V8J
1
10K_0402_5%
EC_RSMRST# 22
EC_LID_OUT# 22
EC_ON 38
WL_BLUE_LED# 33
+3VL
PV-1 For WWAN noise
+5VL
CIR_IN 29
T84
FSTCHG 37
STD_ADP 37
CAPS_LED# 33
BAT_LED# 33
ON/OFFBTN_LED# 33
SYSON 26,35,40
VR_ON 42
2
R586
EC_RSMRST#
100
101 R588 1
2
EC_ON
0_0402_5%
102
WL_BLUE_LED#
103
PM_PWROK_R
104
BKOFF#
105
M_PWROK
106
TP_LED#
107
108
FRD#
FWR#
SPI_CLK
FSEL#
33_0402_5%
47_0402_5%
33_0402_5%
D16
1
R714
10K_0402_5%
D14
1
+3VL
2 PCI_SERR#
PCI_SERR# 20
R715
150K_0402_5%
1
2
0_0805_5%
R443
1
1
C726
LAN_POWER_OFF_R
2
0.1U_0402_16V4Z
L31
1
AC_IN
2
0_0603_5%
D13
1
ACIN
0_0402_5%
+3VL
+3VL
R1099
4.7K_0402_5%
1
R1100
4.7K_0402_5%
33 ESB_CLK
33 ESB_DAT
C791
2
R731
R732
1
1
2 0_0402_5%
2 0_0402_5%
@
C315
10P_0402_25V8K
ESB_CLK_R
ESB_DAT_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
ACIN 37
25 LAN_POWER_OFF
GPI
EC DEBUG port
UTX
TP_CLK
TP_DATA
119
120
126
128
110
112
114
115
116
117
118
+3VL_EC
C725
15P_0402_50V8J
KSO14
FAN_SET 6
VCTRL 37
IREF 37
AC_SET 37
97
98
99
109
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
XCLK1
XCLK0
@
R595
20M_0402_5%
32.768KHZ_12.5PF_9H03200413
1
122
123
NUM_LED#
11
24
35
94
113
C324
0.1U_0402_16V4Z
C723
15P_0402_50V8J
1
2
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
GND
GND
GND
GND
GND
33 NUM_LED#
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
tt
SM Bus
PCI_RST#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
//
m
SLP_S3#
SLP_S5#
EC_SMI#
2
LID_SW#
0_0402_5%
ESB_CLK_R
ESB_DAT_R
EC_PME#
@ R591 2 0_0603_5%
1
9 TSATN#
FAN_SPEED
6 FAN_SPEED
WWAN_POWER_OFF
26 WWAN_POWER_OFF
UTX
LAN_POWER_OFF_R
R5931
2
+3VL
ON/OFFBTN
4.7K_0402_5%
33 ON/OFFBTN
SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
EC_PME#
GPIO
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
EC_PME#
22,29
22
22
33
R190 1
OPP@
33 WL_BLUE_BTN
77
78
79
80
2 100P_0402_50V8J
INV_PWM 19
BATT_TEMP 36
BATT_OVP 36
ADP_I 37
ADP_ID 36
TP_BTN# 33
R720
p:
@ R589 1
0_0402_5%
20 PCI_PME#
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
DIM_LED
ACOFF
SPI Device Interface
yc
R191
10K_0402_5%
@ C794 1
C720
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
+3VALW
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
2 100P_0402_50V8J
KSO11
AVCC
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
63
64
65
66
75
76
PWM Output
J1
R581
8.2K_0402_5%
2
R213
8.2K_0402_5%
R403 1
PCI_RST#
SUSP#
SYSON
HDA_RST#_EC
12
13
37
20
2 0_0402_5% 38
@ C793 1
+3VL
CLK_PCI_EC
PCI_RST#
ECRST#
INV_PWM
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
MISC
2 100P_0402_50V8J
KSO10
/x
/
2
33_0402_5%
@ C792 1
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
21
23
26
27
@ R576
2
1
2
3
4
5
7
8
10
om
p.
su
@ C722
1
21 GATEA20
21 KB_RST#
22 SIRQ
21,26 LPC_FRAME#
21,26 LPC_AD3
21,26 LPC_AD2
21,26 LPC_AD1
21,26 LPC_AD0
GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
KSO15
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
4.7K_0402_5%
AGND
2
2
2
2
69
1
1
1
1
For EMI
HDA_RST#_EC
Q21
MMBT3904_NL_SOT23-3
ECAGND
R573
R577
R574
R575
VCC
VCC
VCC
VCC
VCC
VCC
SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2
67
9
22
33
96
111
125
U30
EC recommend
R251
10K_0402_5%
+3VS
100P_0402_50V8J
R250
56_0402_5%
+3VL
BATT_OVP
HDA level shift
2
2
0.1U_0402_16V4Z
1000P_0402_50V7K
0.1U_0402_16V4Z
1
2 2
0.1U_0402_16V4Z
1
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
ACES_85202-24051
SI-1 Reverse KB connector
2
100P_0402_50V8J
Vendor
Recommend
Compal Secret Data
Issued Date
2007/08/28
Deciphered Date
2006/07/26
Title
Size
Date:

EC KB926/KB Conn.
Document Number
Rev
0.1
Montevina UMA
Sheet
32
of
46
Power Button
MV-1 For ESD request, close to JTPSW
for debug only
SI-1 Delete SW2
TP_LED#
TP_BTN#
+5VS
D65
SM05_SOT23
1
2
3
4
GND
GND
ACES_87213-0800G
+5VS_LED
1
2
3
4
5
6
0_0805_5%
CAPS_LED# 32
32 ON/OFFBTN_LED#
32 ESB_CLK
32 ESB_DAT
32 I2C_INT
+5VALW
32 LID_SW#
32 ON/OFFBTN
/x
/
2
JCSB CONN@
1
2
3
4
5
6
7
8
9
10
11
12
ESB_CLK_CAP
ESB_DAT_CAP
2 FBMA-11-100505-801T 0402
2 FBMA-11-100505-801T 0402
Close to JP59
2
1.8K_0402_5%
0.1U_0402_16V4Z
2
TP_DATA
TP_CLK
@ D60
D28
SM05_SOT23
+5VALW
+5V_TP
+5V_TP
R691 1
2 0_0603_5%
1
CONN@
JTP
1
2
3
4
GND
GND
D67
SM05_SOT23
C729
0.1U_0402_16V4Z
2
1
2
3
4
5
6
TP_CLK
TP_DATA
TP_CLK 32
TP_DATA 32
P-TWO_161011-04021
@ C730
100P_0402_50V8J
@ C731
100P_0402_50V8J
MV-1 For ESD request, close to JTP

3
Mini card LED
p:
2 0_0402_5%
C1518
1
1
2
3
4
5
6
7
8
9
10
GND
GND
TP_LED# 32
TP_BTN# 32
P-TWO_161021-10021
+3VS
R193
10K_0402_5%
tt
R1192 1
OPP@
1
2
R238 1K_0402_1%
32 NUM_LED#
C313
+5VS
TP_LED#
TP_BTN#
T/P Board Conn
+5V_TP
4.7U_0603_6.3V6K
+5VS
2 0_0402_5%
2 0_0402_5%
1
1
2 0_0402_5%
2 0_0402_5%
1
2
3
4
5
6
P-TWO_161011-04021
R151
R1191
1
2
3
4
GND
GND
SM05_SOT23
ENE@
R56 1
R149 1
ENE@
main@1
R169
OPP@
OPP@
WL_BLUE_LED#
R53
0_0805_5%
OPP@
yc
32 WL_BLUE_BTN
R51
0_0805_5%
Main@
//
m
Cypress@
R729 1
R730 1
Cypress@
32,36 SMB_EC_CK1
32,36 SMB_EC_DA1
+5VALW
+3VL
SWITCH BOARD.
CONN@
JTPSW
1
2
3
4
GND
GND
om
p.
su
ENE@
C326
33P_0402_50V8K
ESB_CLK_CAP 2
1
1
2
3
4
5
6
P-TWO_161011-04021
P-TWO_161011-04021
SI-1 Change Cap board power rail to +3VL
T/P Board (Inculde T/P_ON/OFF)
CONN@
JKBL
R205
1
ON/OFFBTN_LED#
+5VS
CONN@
JCAP
White
AMBER
+3VS
32 BAT_LED#
21 SATA_LED#
22 HDDHALT_LED#
Keyboard backlight Conn
Caps-Lock Conn
CONN@
JLED
10
8 GND
7
6
5
4
3
2
1 GND
8
7
6
5
4
3
2
1
+5VALW
+5VS
System LED Conn
D66
SM05_SOT23
MV-1 For ESD request, close to JCSB
WL_BLUE_LED# 32
Q11
2N7002_SOT23-3
2
G
30 BT_LED
R716
100K_0402_5%
D24
26 WL_LED#
26 WW_LED#
WL_BLUE_LED#
PSOT24C_SOT23-3
4
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

KBD, ON/OFF, SW, CIR
Document Number
Rev
0.1
Montevina UMA
Sheet
E
33
of
46
HDMI_TX_0+
1
@ R1215
2
0_0402_5%
@ R1216
1
0_0402_5%
2
HDMI_TX0-
WCM-2012-900T_0805
HDMI_TX0+
3
HDMI_TX_1+
1
@ R1217
2
0_0402_5%
@ R1218
1
0_0402_5%
2
HDMI_TX1-
WCM-2012-900T_0805
HDMI_TX1+
3
HDMI_TX_2-
4.7K ohm
R1244
R653
R1206
0 ohm
X
X
X
0 ohm
0 ohm
4.7K ohm
0 ohm
X
R1249
0 ohm
0 ohm
R1245
0 ohm
0 ohm
R1203
R1241
HDMI_TX2-
R1205
R1202
1
@ R1219
2
0_0402_5%
C773
R1207
R1208
X
0 ohm
X
24
23
22
HDMI Connector
+5VS
@
1
0 ohm
HDMI_DETECT
R665
1
2
1K_0402_1%
L40
1
FBML10160808121LMT_0603 1
D32
SKS10-04AT_TSMA
C774
330P_0402_50V7K 2
X
4.7K ohm
1
0.1U_0402_16V4Z
C773
C314 @
2200P_0402_25V7K
18
16
15
19
HDMI_CLKHDMI_CLK+
HDMI_TX0HDMI_TX0+
HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+
12
10
9
7
6
4
3
1
+5V
SDA
SCL
HP_DET
CKCK+
D0D0+
D1D1+
D2D2+
CEC
Reserved
GND
GND
GND
GND
GND
GND
GND
GND
DDC/CEC_GND
13
14
2
5
8
11
20
21
22
23
17
SUYIN_100042MR019S153ZL
CONN@
X
X
0.1uF
1uF
1uF
Issued Date
+5VS_HDMI
HDMIDAT
HDMICLK
2
JHDMI1
2
2200P_0402_25V7K
4.7K ohm
4.7K ohm
C273
RB411D T146 _SOT23-3

D31
X
X
10U_0805_6.3V6M
HDMI_TX_1+
R1251
0 ohm
HDMI_TX_1-
@C772
4.7K ohm
R1246
39
37
GND
GND
OUT_D1-
OUT_D1+
OUT_D2-
VCC3V
21
@ R659
1
2
68_0402_5%
2.2uF
WCM-2012-900T_0805
HDMI_TX2+
3
HDMI_TX_0+
0.5P_0402_50V8B
3.9K ohm 499 ohm 499 ohm
R1247
HDMI_TX_0-
R1250
R1252
38
C321
4.7K ohm
4.7K ohm
R1248
L42
HDMI_TX_2+
R1243
C1517
L41
HDMI_TX_1-
X
4.7K ohm
2N7002_SOT23-3
@C770
2
68_0402_5%
R1204 4.7K ohm
L39
HDMI_TX_0-
Parade
8171
0 ohm
Q108
0_0402_5%
2
Parade
8101T
2
G
0.5P_0402_50V8B
ST
0 ohm
R654
10K_0402_5%
@ R1214
1
R1242
R1201
+3VS_LS
S IC STHDLS101TQTR QFN 48P HDMI SHIFTER
+3VS_LS
0.5P_0402_50V8B
4.7K_0402_5%
1
+3VS_LS
1
2
R1249 0_0402_5%
1
0_0402_5%
HDMI_DETECT
2
68_0402_5%
+3VS_LS
R50
3.9K_0402_1%
2
0_0402_5%
2
R655
@ R657
2
68_0402_5%
0_0402_5%
0_0402_5%
4.7K_0402_5%
0_0402_5%
1
@ R1213
25
@ R1247
2
+3VS_LS
p:
R1240
OE*
+3VS_LS
tt
WCM-2012-900T_0805
HDMI_CLK+
3
VCC3V
1
1
1
1
//
m
HDMI_CLK-
27
26
2
2
2
2
20
OUT_D2+
thm_pad
19
GND
49
GND
12
18
VCC3V
@ R658
1
GND
ANALOG2
11
0_0402_5%
2
IN_D1-
HDMICLK
R1205
R49
3.9K_0402_1%
2
1
2
HDMICLK+
B
IN_D1+
28
To option use ST or Parade
41
SCL_SINK
SI-1 Use ST only
L38
40
HDMIDAT
SCL_SOURCE
HDMI_TX_2-
IN_D2-
HDMI_DETECT
29
+3VS_LS
@C771
R1208
7.5K_0402_1%
VCC3V
43
44
42
IN_D2+
GND
45
IN_D3+
IN_D3-
46
VCC3V
30
SDA_SINK
R1203
R1245
@ R1246
R651
@ R652
33
HPD_SINK
0.5P_0402_50V8B
HDMI_TX_2+
SDA_SOURCE
1 TMDS_B_HPD
0_0402_5%
om
p.
su
0_0402_5%
yc
HDMICLK-
R9
TMDS_B_HPD#
0_0402_5%
34
HPD_SOURCE
@ R656
1
35
31
@C769
HDMICLK+
1 4.7K_0402_5% +3VS_LS
GND
2
0_0402_5%
R1207
20K_0402_5%
@ R1202
36
1 4.7K_0402_5% +3VS_LS
/x
/
4.7K_0402_5%
2
1
R1252
+3VS_LS
47
ANALOG1(REXT)
OUT_D3-
@ R1251
1
HDMICLK-
+3VS_LS
32
OUT_D3+
0_0402_5%
2
4.7K_0402_5%
2
2.2U_0603_6.3V4Z
+3VS_LS
@ R1212
1
0_0603_5%
@ R1241
DDC_EN
13
10
R1248
1
@ R1250
1
+3VS_LS
@C1517
GND
VCC3V
17
2
0_0402_5%
OUT_D4-
9 HDMICLK_NB
FUNCTION3
PC1
FUCNTION2
OUT_D4+
TMDS_B_HPD
FUNCTION4
PC0
FUNCTION1
14
R653 3.9K_0402_1%
2
1
VCC3V
16
GND
VCC3V
GND
15
2
4.7K_0402_5%
2
0_0402_5%
1
R1206
48
IN_D4+
+3VS_LS
2
1
R1204
2
1
@ R1244
R1242
1
2
0_0402_5%
IN_D4-
U43
9 HDMIDAT_NB
11 TMDS_B_HPD#
R648
1
+3VS
0.1U_0402_10V6K
C318
TMDS_B_DATA0 11
TMDS_B_DATA0# 11
1
@ R1201
4.7K_0402_5%
@ R1243
4.7K_0402_5%
11 TMDS_B_CLK#
11 TMDS_B_CLK
@ R1240
4.7K_0402_5%
R650
2.2K_0402_5%
2
TMDS_B_DATA1 11
TMDS_B_DATA1# 11
+3VS_LS
+3VS_LS
+3VS_LS
R649
2.2K_0402_5%
+3VS_LS
11 TMDS_B_DATA2#
11 TMDS_B_DATA2
+3VS_LS
EQUALIZATION SETTING:
[PC1,PC0]=00,8dB
[PC1,PC0]=01,4dB (Recommanded)
[PC1,PC0]=10,12dB
[PC1,PC0]=11,0dB
0.1U_0402_10V6K
C319
+3VS_LS
0.01U_0402_16V7K
C320
4.7K ohm
Compal Secret Data

2007/08/28
2006/03/10
Deciphered Date
Title

HDMI LS & Conn.
Rev
0.1
Montevina UMA
Date:
Sheet

1
34
of
46
Q13A
SYSON
100K_0402_5%
SUSP
C1512
SUSP 41
C1513
C1514
C1515
Q13B
5
SUSP#
SUSP# 26,32,37,39
H9
HOLEA
H8
HOLEA
H7
HOLEA
H6
HOLEA
H5
HOLEA
H4
HOLEA
H13
HOLEA
H12
HOLEA
470_0402_5%
@ R647
470_0402_5%
H11
HOLEA
R646
SUSP
1
2
3
Q12B
SUSP
H10
HOLEA
2
6
Q12A
SYSON#
H3
HOLEA
+1.8VS
2N7002DW-7-F_SOT363-6
p:
3
H2
HOLEA
R643
tt
Q9B
SUSP
+0.9V
470_0402_5%
2
6
Q9A
SUSP
470_0402_5%
2N7002DW-7-F_SOT363-6
2
3
Q6B
SUSP
R645
470_0402_5%
2N7002DW-7-F_SOT363-6
2
6
1
2N7002DW-7-F_SOT363-6
R644
470_0402_5%
R642
Q6A
SUSP
1
R641
470_0402_5%
+1.8V
1
+VCCP
+1.5VS
+3VS
2N7002DW-7-F_SOT363-6
+5VS
B
H1
HOLEA
2N7002DW-7-F_SOT363-6
Discharge circuit
//
m
yc
26,32,40 SYSON
0.1U_0402_16V4Z
SYSON#
0.1U_0402_16V4Z
R640
100K_0402_5%
41 SYSON#
+1.8V
1
R639
SI-1 For EMI DDR issue

SI-R 2 caps and change to GND
0.1U_0402_16V4Z
+3VL
om
p.
su
2
RUNON
@ C768
@ C767
10U_0805_10V4Z
10U_0805_10V4Z
+3VL
1
2
3
0.1U_0402_16V4Z
@ C766
+1.8VS
U34 @
0.1U_0402_16V4Z
SI7326DN-T1-E3_PAK1212-8
+1.8V
0.01U_0402_16V7K
/x
/
+1.8V to +1.8VS
Transfer
Q35
2N7002_SOT23-3
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
4
3
2
C765
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2
C65
4700P_0402_25V7K
DIM_LED#
D
2
G
Q34B
Q34A
1
4
SUSP
DIM_LED
32 DIM_LED
470_0402_5%
SUSP
R224
470_0402_5%
C294
0.1U_0402_16V4Z
R638
RUNON
RUNON_3VS
R637
10K_0402_5%
2
10U_0805_10V4Z
C764
3
10U_0805_10V4Z
1
330K_0402_5%
+5VS_LED
Q15
0.1U_0402_16V4Z
R636
10U_0805_10V4Z
C762
C761
4
R223
330K_0402_5%
10U_0805_10V4Z
+5VS
C760
SI7326DN-T1-E3_PAK1212-8 +3VS
+3VALW
U33
1
2
5
3
1
1
C759
C763
B+
0.1U_0402_16V4Z
+5VALW
B+
DIM LED
+3VALW to +3VS
Transfer
+5VS
SI7326DN-T1-E3_PAK1212-8
U32
1
2
5
3
+5VALW to +5VS
Transfer
@ Q44
FM1
1
FM2
1
FM3
FM4
1
2
G
2N7002_SOT23-3
T21
T33
T45
T52
T60
T62
T64
T73
T75
T32
T34
T51
T53
T61
T63
T72
T74
T76
For ICT
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

DC/DC Interface
Document Number
Rev
0.1
Montevina UMA
Sheet
1
35
of
46
+3VALW
3
PQ3
TP0610K-T1-E3_SOT23-3
+3VL
BATT
1 PR9
2
100K_0402_5%
connect to KBC pin97
PL1
HCB2012KF-121T50_0805
2
PL2
HCB2012KF-121T50_0805
1
2
8
P
/x
/
1
PC10
0.22U_0603_10V7K
+3VL
EN0 38
PR10
200K_0402_1%
1
2
2
PR11
150K_0402_1%
PR12
2.49K_0402_1%
PR15
150K_0402_1%
+5VALW
37
PR16
6.49K_0402_1%
1
2
SMB_EC_CK1 32,33
SMB_EC_CK1
BAT_ID
SMB_EC_DA1 32,33
tt
SMB_EC_DA1
PH1
10K_TH11-3H103FT_0603_1%
2
2
p:
PR14
100_0402_5%
PR13
100_0402_5%
1
1
PJSOT24C_SOT23-3
0
G
PJSOT24C_SOT23-3
1
2
PR7
604K_0402_1%
1
2
+5VS
CPU
yc
PC9
0.01U_0402_50V4Z
PQ1
SSM3K7002FU_SC70-3
2
G
PU1B
LM358ADT_SO8
PC11
1000P_0402_50V7K
SUYIN_200045MR006G101ZR
PC8
1000P_0402_50V7K
PD3
PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
PD2
//
m
EC_SMD
EC_SMC
BATT
PL3
HCB2012KF-121T50_0805
2
PL4
HCB2012KF-121T50_0805
1
2
1
2
3
4
5
6
7
8
1
2
3
4
5
6
GND
GND
0.01U_0402_25V7K
PC6
VMB
JBATT
PU1A
LM358ADT_SO8
BATT_OVP 32
PR5
10K_0402_5%
2
1
om
p.
su
1
PC3
1000P_0402_50V7K
PJSOT24C_SOT23-3
PD1
2
1
PC2
100P_0402_50V8J
ACES_87302-0441
105K_0402_1%
PR6 1
2
ADPIN
VIN
RLZ3.6B_LL34
1
2
PR3
10K_0402_5%
ADP_SIGNAL
PC5
1000P_0402_50V7K
2
1
6
5
4
3
2
1
@1000P_0402_50V7K
PC4
100P_0402_50V8J
2
1
GND
GND
4
3
2
1
PR2
10K_0402_5%
+5VALW
499K_0402_1%
PR4 1
2
PD4
JDC1
PC12
PR8
2K_0402_5%
<BOM Structure>
2 1
ADP_ID 32
<BOM Structure>
0.01U_0402_25V7K
PC1
340K_0402_1%
PR1 1
2
AC_LED# 32
PR17
1K_0402_5%
BATT_TEMP 32
Compal Secret Data
Issued Date
2007/05/29
Deciphered Date
2008/05/29
A
Title

DC Connector/CPU_OTP
Size
Document Number
Rev
0.1
Montevina Consumer Discrete

Date:
W ednesday, February 18, 2009

D
Sheet
36
of
46
P4
B+
BATT
P2
PQ102
AO4433 1P SO8
PR102
1
1
5
6
7
8
3
2
1
1
2
PC128
4.7U_0805_25V6-K
1
2
BQ24740VREF
21
20
19
18
47K_0402_5%
PR119
BAT_ID 36
2
G
IREF 32
PR121
200K_0402_1%
PR120
2
1
133K_0402_1%
PC124
0.1U_0603_25V7K
1
1
yc
BATT
PR122
681K_0402_1%
1
2
17
PQ111
SSM3K7002FU_SC70-3
PC118
0.1U_0402_10V7K
1U_0603_10V6K
PC121
100P_0402_50V8J
2
1
1
2
PC105
4.7U_0805_25V6-K
PC135
@470P_0603_50V8J
om
p.
su
DPMDET
CELLS
SRP
SRN
BAT
SRSET
IADAPT
PR141
@4.7_1206_5%
S
FSTCHG#
1
PR126
100K_0402_1%
PACIN
LM393DG_SO8
PR134
10K_0402_5%
2
PD103
RLZ4.3B_LL34
PR136
60.4K_0402_1%
1
2 VIN_1
<BOM
Structure>
PQ113
SSM3K7002FU_SC70-3
3
STD_ADP 32
PU102B
PR133
10K_0603_0.1%
PC126
0.047U_0402_16V7K
PR130
2.15K_0402_1%
1
2
ACIN 32
PR127
10K_0402_1%
2
G
PR124
1K_0402_5%
1
2
VIN
VIN
PQ112
SSM3K7002FU_SC70-3
32 FSTCHG
1.24VREF
PQ110
PC119
tt
PR132
100K_0402_5%
2
1
1
G
PU102A
LM393DG_SO8
2
G
PR135
10K_0603_0.1%
O
-
4
S TR AO4468 1N SO8
22
p:
PR128
10K_0402_5%
2
1
PR129
10K_0402_1%
2
1
1
2
+3VL
CHGEN#
1
1SS355_SOD323-2
<BOM Structure>
//
m
1
1VIN_1
2
+3VL
PC125
0.1U_0603_25V7K
23
DL_CHG
PR117
100K_0402_5%
1
2
IADAPT
15
2
PC120
0.22U_0603_10V7K
2
1
PC123
0.1U_0402_10V7K
+3VL
PR131
133K_0402_1%
REGN
PR123
1M_0402_5%
1
2
VIN
LX_CHG
24
PC116
4.7U_0805_25V6-K
PGND
VIN
PR125
47_1206_5%
25
PR112
0.015_1206_1%
1
2
LODRV
ISYNSET
PR118
10K_0402_5%
1
2
PD104
1SS355_SOD323-2
PL102
10U_LF919AS-100M-P3_4.5A_20%
1
2
2 2
EXTPWR
PR116
15K_0402_1%
PR115
100K_0402_1%
Charge Detector
BATT
0.1U_0402_10V7K
REGN
PQ106
DTC115EUA_SC70-3
PH
VADJ
32
/x
/
VDAC
14
32 ADP_I
26
12
13
PR114
@0_0402_5%
1
2
PC117
1U_0603_10V6K
HIDRV
PD102
VADJ
PR113
143K_0402_1%
16
32 VCTRL
PU101
BQ24740RHDR_QFN28_5X5
VREF
AO4466_SO8
PC111
1
+3VL
11
SSM3K7002FU_SC70-3
2
1SS355_SOD323-2
<BOM Structure>
10
27
PC114
4.7U_0805_25V6-K
28
ACOFF
PQ108
BTST
PC110
1U_0805_25V6K
1
2
PR142
0_0402_5%
BST_CHG1
2
PR139
0_0402_5%
DH_CHG
1
2
CHGEN
PVCC
AGND
29
5
6
7
8
ACN
TP
IADSLP
BQ24740VREF
PR108
10_1206_5%
1
2
1U_0603_6.3V6M
PQ109
2
G
PD101
ACOFF#
PACIN
PR111
3K_0402_1%
1
2
ACOFF#
3
2
1
PC112
1
2
PACIN_1 38
VIN
CHG_B+
PC113
4.7U_0805_25V6-K
2
1
PC104
4.7U_0805_25V6-K
2
ACN
1
2
ACP
3
4
LPMD
5
ACDET
LPREF
8
PR103
47K_0402_5%
1
2
PR105
10K_0402_5%
SUSP#
8
7
6
5
CHG_B+
CHGEN#
7
26,32,35,39
PR110
0_0402_5%
1
2
0.012_2512_1%
1
2
3
PL101
HCB2012KF-121T50_0805
2
PC102
1U_0603_6.3V6M
PC108
0.1U_0603_25V7K
1
2
PR140
100K_0402_5%
<BOM Structure>
ACDET
ACSET
PC107
@0.01U_0402_16V7K
1
PR109
150K_0402_5%
2
S
PR104
0_0402_5%
2
ACSET
PQ105
DTC115EUA_SC70-3
3
1
2
PR106
200K_0402_5%
PQ104
DTA144EUA_SC70-3
2
1
1
2
PQ107
SSM3K7002FU_SC70-3
2
G
8
7
6
5
32 AC_SET
PC106
0.47U_0603_16V7K
2 Structure>
1
<BOM
PR107
47K_0402_1%
1
2
1
2
3
PR101
47K_0402_5%
1
2
PC101
47P_0402_50V8J
1
2
3
8
7
6
5
PC103
4.7U_0805_25V6-K
PQ103
AO4433
ACP
PQ101
AO4433
PC115
4.7U_0805_25V6-K
2
1
VIN
S
PU104
4
ACDET
PC127
1
2
CATHODE
NC
22P_0402_50V8J
2
100K_0402_1%
PR138
PR137
20K_0402_1%
REF
1.24VREF
ANODE
NC
2
1
LMV431ACM5X_SOT23-5
Compal Secret Data
Issued Date
2007/05/29
Deciphered Date
2008/05/29
Title
Charger
Size
Document Number
Rev
0.1
LA-4481P
Date:

D
Sheet
37
of
46
PC302
0.22U_0603_10V7K
2VREF_51125
PR304
20K_0402_1%
2
0.1U_0402_25V6
PC313
2
1
1
2
1
1
3
2
1
PR317
2
R_EC_RSMRST# 22
PC310
150U 6.3V B2 R45M
PC311
10U_0805_10V6K
0_0402_5%
PQ304
S TR AON7702L 1N DFN
yc
VL
+5VALWP
1
2
VCLK
18
VIN
GND
VREG5
17
16
13
PU301
RT8205AGQW WQFN 24P
PC315
@680P_0603_50V8J
LG_5V
PR316
@4.7_1206_5%
19
3
2
1
DRVL1
PL303
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2
5
LX_5V
DRVL2
PC305
10U_1206_25V6M
PC304
2200P_0402_50V7K
2
1
/x
/
1
ENTRIP1
VFB1
VREF
20
B++
PC312
0.1U_0603_25V7K
tt
+3VL
+3VLP
PJP301
PJP302
1
+5VALWP
+5VALW
(4.5A,180mils ,Via NO.= 9)
+3VALW
(3A,120mils ,Via NO.= 6)
1
PAD-OPEN 2x2m
PAD-OPEN 4x4m
PJP303
VL
LL1
+3VALWP
+5VL
VL
PJP304
PAD-OPEN 4x4m
EC_ON 32
1
PAD-OPEN 2x2m
1
3
22
21
PR314
100K_0402_5%
2
PC318
0.047U_0603_16V7K
PR313
100K_0402_5%
2
PQ307
SSM3K7002FU_SC70-3
2
G
p:
PQ306
SSM3K7002FU_SC70-3
1
2
1
PQ308
@SSM3K7002FU_SC70-3
1
2
2
G
PR318
604K_0402_1%
<BOM Structure>
VBST1
DRVH1
LL2
PR308
PC308
2.2_0402_5% 0.1U_0402_10V7K
BST_5V 1
PR310
2 1
2
0_0402_5%
UG_5V
1
2
DRVH2
//
m
ENTRIP2
1
2
G
24
23
PQ302
2VREF_51125
2
G
PR312
1M_0402_5%
1 <BOM Structure>
2
36 EN0
1
2
3
37 PACIN_1
B++
PR311
191K_0402_1%
PQ305
SSM3K7002FU_SC70-3
12
VO1
PGOOD
VBST2
15
9
10
11
LG_3V
1
2
PC309
PC314
@680P_0603_50V8J
PR315
@4.7_1206_5%
UG_3V
PQ303
S TR AON7406L
ENTRIP1
150U 6.3V B2 R45M
BST_3V
SKIPSEL
VREG3
EN0
PR307
2 1
2
0_0402_5%
PC307
0.1U_0402_10V7K
LX_3V
PR309
0_0402_5%
2
+3VALWP
VO2
om
p.
su
PL302
4.7UH_SIQB74B-4R7PF_4A_20%
2
1
TONSEL
P PAD
2
1
2
3
UG1_3V
VFB2
ENTRIP2
25
14
PC306
10U_0805_6.3V6M
PQ301
B++
PR306
90.9K_0402_1%
2
1
2
PC303
4.7U_0805_25V6-K
PC301
2200P_0402_50V7K
2
1
PR305
115K_0402_1%
1
ENTRIP1
PR303
20K_0402_1%
1
2
+3VLP
PC316
0.1U_0402_25V6
2
1
PR302
30.9K_0402_1%
2
PL301
HCB2012KF-121T50_0805
ENTRIP2
B++
B+
PR301
13.7K_0402_1%
1
Compal Secret Data
2007/08/02
Issued Date
2008/08/02
Deciphered Date
Title

3.3VALWP/5VALWP
Date:
Rev
0.1
LA-4481P
Sheet
E
38
of
46
PR501
29.4K_0402_1%
+1.05V_VCCP
B+++
PR502
75K_0402_1%
PR503
10.2K_0603_0.1%
1
2
PR504
10.2K_0603_0.1%
+1.5VSP
1
2
19
LG_1.5V
3
2
1
UG1_1.5V
PC521
0.1U_0402_25V6
1
2
2200P_0402_50V7K
PC505
1
2
1
2
PC504
@4.7U_0805_25V6-K
AO4466_SO8
+1.5VSP
PL501
3.3UH 30% MSCDRI-7030AB-3R3N 4.1A
1
2
PQ503
PR516
@4.7_1206_5%
TPS51124RGER_QFN24_4x4
PC510
4.7U_0805_6.3V6K
220U_B2
DR VL1
1
PR509
0_0402_5%
PC508
LX_1.5V
PC516
4.7U_0805_25V6-K
5
6
7
8
/x
/
1
VO1
VFB1
3
GND
TONSEL
V5FILT
V5IN
PC519
@680P_0603_50V7K
AO4468_SO8
PR511
9.53K_0402_1%
3
2
1
16
15
LL1
20
yc
PR510
15.8K_0402_1%
1
2
IRF8707TRPBF_SO8
PR513
0_0402_5%
2
//
m
26,32,35,37 SUSP#
PGND2
13
1 2
PC518
820P_0603_50V7K
<BOM Structure>
UG_1.5V
DR VL2
BST_1.5V
21
12
22
DR VH1
PC507
0.1U_0402_10V7K
5
6
7
8
LG_1.05V
VBST1
PR507
0_0402_5%
2
1
LL2
23
1 2
11
LX_1.05V
24
EN1
om
p.
su
DR VH2
PGOOD1
PGND1
VBST2
10
UG_1.05V
PR515
4.7_1206_5%
1
2
3
220U 2.5V B2
<BOM Structure>
2
1
PC517
PC509
4.7U_0805_6.3V6K
VO2
BST_1.05V
TRIP1
1
PR508
PQ501
18
2
0_0402_5%
EN2
8
7
6
5
PQ504
PL502
HCB2012KF-121T50_0805
2
1
17
UG1_1.05V
PGOOD2
TRIP2
PL503
2.2UH_PCMC063T-2R2MN_8A_20%
2
1
14
1
2
3
+1.05V_VCCP
PC506
PR506
0.1U_0402_10V7K
0_0402_5%
2
1 2
1
P PAD
VFB2
PU501
25
4
B+
PQ502
AO4466_SO8
B+++
PR505
0_0402_5%
8
7
6
5
0.1U_0402_25V6
PC520
2200P_0402_50V7K
PC502
1
2
1
2
PC503
4.7U_0805_25V6-K
PC501
4.7U_0805_25V6-K
PR512
0_0402_5%
2
SUSP# 26,32,35,37
+5VALW
+1.5VS
(7A,280mils ,Via NO.=14)
PAD-OPEN 4x4m
PJP502
+1.05V_VCCP
+VCCP
1
2
1
2
PC512
@0.1U_0402_16V7K
PC515
4.7U_0805_10V6K
tt
PJP501
+1.5VSP
p:
PC514
1U_0603_10V6K
PC513
@0.1U_0402_16V7K
PR514
3.3_0402_5%
PAD-OPEN 4x4m
Compal Secret Data
2007/05/29
Issued Date
Deciphered Date
2008/05/29
5
Title

1.5VP/1.05V_VCCP
Size
Document Number
Rev
0.1

Date:
Sheet
1
39
of
46
PR401
0_0402_5%
1
2
PL401
2
+
2
PC412
180P_0402_50V8J
yc
3
2
1
DL_1.8V
2200P_0402_50V7K
PC405
PC415
4.7U_0805_10V6K
TPS51117RGYR_QFN14_3.5x3.5
S TR AON7702L
PC410
15
TP
PR408
1
2
14.3K_0603_0.1%
+1.8VP
+1.8VP
220P_0603_50V8J
DRVL
+5VALW
PR407
4.7_1206_5%
PQ402
10
2
PR406
10K_0402_1%
V5DRV
4.7U_0805_6.3V6K
PC407
2
1
11
3
2
1
TRIP
PC406
@680P_0402_50V7K
PL402
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
LX_1.8V
PC408
220U_2.5V _B2
PGOOD
12
B+
LL
PR411
1
2
0_0402_5%
2 2
VFB
DH_1.8V
13
DH1_1.8V
V5FILT
DRVH
/x
/
VOUT
PC402
0.1U_0402_10V7K
om
p.
su
VBST
TON
PC409
1U_0603_10V6K
PGND
2
1
0_0402_5%
EN_PSV
PR404
255K_0402_1%
1
2
GND
PU401
PR405
BST1_1.8V 1
14
1
PR403
316_0402_1%
+1.8VP
PR402
0_0402_5%
4.7U_0805_25V6-K
PC404
2
1
PQ401
BST_1.8V1
4.7U_0805_25V6-K
PC403
2
1
+5VALW
0.1U_0402_25V6
PC414
2
1
PC401
@1000P_0402_50V7K
HCB1608KF-121T30_0603
1
2
1.8V_B+
26,32,35 SYSON
//
m
PR409
10K_0603_0.1%
PJP401
+1.8VP
tt
p:
+1.8V (7A,280mils
,Via NO.=14)
PAD-OPEN 4x4m
Compal Secret Data
Issued Date
2007/05/29
Deciphered Date
2008/05/29
A
Title

+1.8VP
Size
Document Number
Rev
0.1

Date:

D
Sheet
40
of
46
+1.8V
GND
VCNTL
NC
NC
+5VALW
VOUT
NC
TP
VREF
/x
/
PR601
1K_0402_1%
VIN
2
3
1
2
PC602
@10U_0805_10V4Z
PC601
10U_0805_10V4Z
PU601
1
PC603
1U_0603_16V6K
2
1
PR602
@0_0402_5%
+0.9VP
2
G
1
PR604
0_0402_5%
35 SUSP
PR603
1K_0402_1%
om
p.
su
PQ601
SSM3K7002FU_SC70-3
2
1
PC604
0.1U_0402_16V7K
S IC RT9173DPSP SO 8P
35 SYSON#
PC605
10U_0805_6.3V6M
PJP601
1
+0.9V
//
m
+0.9VP
PAD-OPEN 3x3m
tt
p:
yc
PC606
@0.1U_0402_16V7K
Compal Secret Data
Issued Date
2006/11/23
Deciphered Date
2007/11/23
5
Title

0.9VP
Size
Document Number
Rev
0.1

Date:

1
Sheet
41
of
46
+5VS
OCSET
27
BOOT2
26
NC
25
BOOT_CPU2
1
PR227
2.2_0603_5%
PR239
10_0603_5%
1
2
VCC_PRM
PC231
0.22U_0603_10V7K
PC240
@2200P_0402_50V7K
1
2
PC208
@1000P_0402_50V7K
2
1
PC239
@100U_25V_M
PC204
100U_25V_M
PC243
@47P_0402_50V8J
2
1
PC207
2200P_0402_50V7K
2
1
PC206
4.7U_0805_25V6-K
2
1
PC205
4.7U_0805_25V6-K
2
1
PC234
4.7U_0805_25V6-K
2
1
<BOM Structure>
PC244
47P_0402_50V8J
2
1
PR220
10K_0402_1%
2
1
PR219
3.65K_0805_1%
2
1
3
2
1
5
3
2
1
VCC_PRM
ISEN2
CPU_B+
p:
PR244 3.57K_0402_1%
PC230 0.1U_0402_16V7K
1
2
2
0.22U_0603_10V7K
2.61K_0402_1%
PR243 1K_0402_1%
PR242
PC229 180P_0402_50V8J
1
2
1
PR241
7 VSSSENSE
PC223
1
2
PC228
1000P_0603_50V7K
PC227
330P_0603_50V8
VSUM
@0_0603_5%
2
VSUM
7 VCCSENSE
1_0402_5%
PR233
1
tt
PC226 330P_0603_50V8
1
2
PQ206
TPCA8036-H 1N SOP-ADV
PR232
PC225
0.1U_0603_25V7K
PR238 1
PR240 1K_0402_1%
11K_0402_1%
PC224 2200P_0402_50V7K
1
2
1
100_0402_1%
1
0.36UH +-20% PCMC104T-R36MN1R17

2
1
PL203
10KB_0603_5%_ERTJ1VR103J
PH201
100P_0402_50V8J
+5VS
PR234 1_0603_5%
PC221
1U_0402_6.3V6K
270P_0402_50V7K
2
ISEN1
ISEN2
2
UGATE_CPU2-2
PC217
0.22U_0603_10V7K
//
m
2 PR237 1
1K_0402_1%
1
PC222
1
2
0_0603_5%
2
1
2
yc
24
PU201
PC218 1000P_0402_50V7K
PR235 97.6K_0402_1% PC220
1
2
2
PR225
PR229
2.2_1206_5%
1 2
1
PR246
PC219 @4.7_1206_5%
680P_0603_50V7K
2
1
UGATE2
UGATE_CPU2-1
ISEN1
PHASE2
PHASE_CPU2
PQ204
29
28
ISEN2
VDD
IRF8714TRPBF 1N SO8
LGATE_CPU2
PGND2
23
22
GND
21
VIN
20
VSUM
19
DFB
VO
18
DROOP
FB2
17
12
16
FB
RTN
COMP
11
13
10
15
1
2
1000P_0402_50V7K PC216
PR228 13K_0402_1%
1
2
VW
VSEN
13K_0402_1%
1
2
VDIFF
PR226
31
30
<BOM Structure>
PVCC
LGATE2
PC245
47P_0402_50V8J
2
1
SOFT
NTC
CPU_B+
LGATE_CPU1
PC238
2200P_0402_50V7K
32
LGATE1
VR_TT#
+
2
VCC_PRM
PC236
4.7U_0805_25V6-K
2
1
ISEN1
0.22U_0603_10V7K
PC214
1000P_0402_50V7K
2
1
PC235
4.7U_0805_25V6-K
2
1
33
PR231
10K_0402_1%
2
1
PGND1
PC213
4.7U_0805_25V6-K
2
1
RBIAS
14
0.022U_0603_25V7K PC215
1
2
+
2
+VCC_CORE
PR223
1_0402_5%
PR224
@0_0603_5%
1
2
PC211
1
2
VSUM
34
PR230
3.65K_0805_1%
PHASE_CPU1
PHASE1
PC212
4.7U_0805_25V6-K
2
1
UGATE_CPU1-1
PMON
PC241
2200P_0402_50V7K
36
35
PR218
2.2_1206_5%
2
1 2
1
PR245
PC210 @4.7_1206_5%
680P_0603_50V7K 2
1
/x
/
BOOT1
UGATE1
S IC ISL6266AHRZ-T QFN 48P PW M
3
2
1
5
PL202
0.36UH +-20% PCMC104T-R36MN1R17
2
1
3
2
1
37
PQ203
1
2
0_0603_5%
PR217
TPCA8036-H 1N SOP-ADV
4
VID0
38
VID1
VID2
39
PC233
4.7U_0805_25V6-K
2
1
5
6
7
8
PC242
470P_0402_50V7K
2
1
1
1
PR213
PR205
PR212
PR211
40
VID3
41
VID4
42
VID5
44
43
VID6
45
DPRSLPVR
47
46
DPRSTP#
48
3V3
CLK_EN#
PSI#
PC237
1000P_0402_50V7K
7
CPU_VID2
7
CPU_VID1
7
CPU_VID0
7
7
CPU_VID3
CPU_VID4
2.2_0603_5% 0.22U_0603_10V7KUGATE_CPU1-2
PR214
PC209
1
2 1
2
5
6
7
8
VR_TT#
PQ201
om
p.
su
0_0402_5%
1 PR221 2
@0_0402_5% PR222 147K_0402_1%
1
2
PR210
1
PGOOD
PSI# 2
32
CPU_VID5
2
C
PR247
2
7 H_PSI#
PC203
2.2U_0603_6.3V6K
PR216
49
GND
1
17,22 VGATE
PL201
SMB3025500YA_2P
2
1
IRF8714TRPBF 1N SO8
4
BOOT_CPU1
@499_0402_1%
1.91K_0402_1%
PR215
0_0402_5%
2
PC201
1U_0603_6.3V6M
+3VS
+3VS
0_0402_5%
2
PC202
0.022U_0402_16V7K
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
PR204
1
PR206
1
VR_ON
7,9,21 H_DPRSTP#
17 CLK_ENABLE#
0_0402_5%
2
PR209
PR203
1
PR208
9,22 DPRSLPVR
499_0402_1%
1
2
PR207
PR201
CPU_VID6
VR_ON
B+
CPU_B+
PR202
1_0603_5%
PC232 0.22U_0402_6.3V6K
2
1

Title
+CPU_CORE
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISIONCustom
OF R&D
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:
5
Rev
0.1
Sheet
1
42
of
46
Version Change List ( P. I. R. List ) for Power Circuit

Item Page#
Title
Date Request
Owner
Issue Description
Rev.
Solution Description
om
p.
su
/x
/
//
m
yc
tt
p:
Compal Secret Data
2007/08/02
Issued Date
2008/08/02
Deciphered Date
Title

Power Changed-List History-1
Date:
Rev
0.1
LA-4111P
Sheet
E
43
of
46
Modify List
Date
Phase
CardReader clock issue
17
Using USB_0 for CLK_48M_CR
2008/10/08
SI-1
Debug Card issue
26
Connect PLT_RST# to JP7.A17
2008/10/08
SI-1
SMT issue
29
Change IR1 to SCR00000E00
2008/10/08
SI-1
Add Audio board
29
Add JAUDIO for audio board
2008/10/08
SI-1
SW2 is for DB1 debug
33
Delete SW2
2008/10/08
SI-1
Cap board issue
33
Change Cap board power rail to +3VL
2008/10/08
SI-1
Support GM47
13
Add C1503 for GM47
2008/10/08
SI-1
Change FAN control circuit to voltage control
Add U51,D63
2008/10/08
SI-1
Delete HDA SSC
21
Remove U8 for layout spacing
2008/10/08
SI-1
10
For PR mini card connector
26
Add R1225 -- R1236
2008/10/08
SI-1
11
PA/PR CardReader LED
27
D54 for PA, D64 for PR
2008/10/08
SI-1
12
EMI request
28
Change R1132 to bead
2008/10/08
SI-1
13
Use audio board
29
Add audio board connector, change MIC to 2pin and add SPK connector
2008/10/08
SI-1
14
Change JFPR to 6 pin connector
30
Add Q109, C1518, R1210
2008/10/08
SI-1
15
EMI request
35
Add C1512 -- C1517
2008/10/08
SI-1
16
Change JFPR to 4 pin connector
30
Delete Q109, C1518, R1210
2008/11/21
SI-R
17
Delete resistor for Debug card
26
Delete R1220-R1224
2008/11/21
SI-R
18
EMI request
35
Delete C1516,C1517 and connect to GND
2008/11/21
SI-R
19
For Intel DPST
19
Add R1237,R1238
2008/11/25
SI-R
20
EMI and WWAN request
17
21
28
Install C217, C218, C219, C435, C312, C316, C66, C67, C1478, C1479, C1480, C1481, D58, C1516, R1239, C327
2008/12/18
PV-1
21
Audio board connector
29
Change pin define
2008/12/18
PV-1
22
ST and Parade level shift
34
2008/12/18
PV-1
23
ESD request
33
Add C1518,D65,D66,D67
2008/1/19
MV-1
24
ESD/ EMI request
25
32
C217-C219, D5-D7, D45-D47, D20, C792-C815 no stuff
2008/2/13
MV-1
25
AUDIO issue
29
C1446, C1447 change to 0805 size
2008/2/13
MV-1
26
PC Beep issue
28
change to analog GND and add separate diode
2008/2/13
MV-1
17
18
30
om
p.
su
yc
/x
/
//
m
PAGE
p:
(Reason for change)
tt
Fixed Issue
Item
Add R for Parade
27
28
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

PIR
Document Number
Rev
0.1
Montevina UMA
Sheet
1
44
of
46
Item
Fixed Issue
(Reason for change)
PAGE
Modify List
Date
Phase
29
30
D
31
32
33
34
35
/x
/
36
37
38
39
om
p.
su
40
41
42
43
yc
44
//
m
45
46
B
47
p:
48
tt
49
50
51
52
53
54
A
55
56
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

PIR 2
Document Number
Rev
0.1
Montevina UMA
Sheet
1
45
of
46
Item
Fixed Issue
(Reason for change)
PAGE
Modify List
Date
Phase
57
58
D
59
60
61
62
63
/x
/
64
65
66
67
om
p.
su
68
69
70
71
yc
72
//
m
73
74
B
75
p:
76
tt
77
78
79
80
81
82
A
83
84
Compal Secret Data
2007/08/28
Issued Date
2006/07/26
Deciphered Date
Title
Size
Date:

HW PIR 3
Document Number
Rev
0.1
Montevina UMA
Sheet
1
46
of
46

A2422 Compal La-4732p HP Presario Cq35 Pavilion Dv3 Montevina Uma Rev1.0 WWW - mycoMP.su

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A2422 Compal La-4732p HP Presario Cq35 Pavilion Dv3 Montevina Uma Rev1.0 WWW - mycoMP.su

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A

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 18, 2009

Montevina Consumer UMA

DDR2 800MHz 1.8V

Intel Cantiga MCH

P9,10, 11, 12, 13, 14

AMP & Audio Jack

SATA HDD Connector

SATA ODD ConnectorP24

Touch Pad CONN.

667/800/1066 MHz 1.05V

USB Board Conn

K/B backlight Conn

Capsense switch Conn

Compal Secret Data

DC/DC Interface CKT.

Compal Electronics, Inc.

Wednesday, February 18, 2009

S5 S4/ Battery only

S5 S4/AC & Battery

SODIMM CLK CHIP

I2C / SMBUS ADDRESSING

SOURCE INVERTER BATT

SMBUS Control Table

@ : means just reserve , no build

USB-0 Right side(with eSATA)

: means Analog Ground

: means Digital Ground

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 18, 2009

Mini card (WLAN)

Compal Secret Data

Compal Electronics, Inc.

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 18, 2009

Fan Control circuit

H_THERMDA, H_THERMDC routing

This shall place near CPU

Thermal Pad VEN

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 18, 2009

* Route the TEST3 and TEST5 signals through

Near pin B26

Length match within 25 mils.

Resistor placed within 0.5"

Close to CPU pin within

Close to CPU pin AD26

Compal Secret Data

Compal Electronics, Inc.

Wednesday, February 18, 2009

Place these capacitors on

Place these capacitors on

Mid Frequence Decoupling

ESR <= 1.5m ohm

Near CPU CORE regulator

Place these capacitors on

Place these capacitors on

RED Mark: Means UMA & dis@ Power select