Scribd Logo
Upload

Welcome to Scribd!

  • ADSD Lesson Plan

    Uploaded by

    anand_kkr
    10 views4 pages
    This document outlines a lesson plan for a course on sequential circuit design. It is divided into 5 units covering topics such as sequential circuit analysis and modeling, state diagrams, state tables, asynchronous circuit design, fault diagnosis algorithms, synchronous design using programmable devices, and system design using VHDL. Each unit spans several lecture hours and includes tutorials. The plan lists the topics to be covered in each lecture along with spaces to record the actual date taught and initials to confirm approval by faculty, head of department, and principal.

    Original Description:

    qw

    Copyright

    © © All Rights Reserved

    Available Formats

    DOC, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document outlines a lesson plan for a course on sequential circuit design. It is divided into 5 units covering topics such as sequential circuit analysis and modeling, state diagrams, state tables, asynchronous circuit design, fault diagnosis algorithms, synchronous design using programmable devices, and system design using VHDL. Each unit spans several lecture hours and includes tutorials. The plan lists the topics to be covered in each lecture along with spaces to record the actual date taught and initials to confirm approval by faculty, head of department, and principal.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    10 views4 pages

    ADSD Lesson Plan

    Uploaded by

    anand_kkr
    This document outlines a lesson plan for a course on sequential circuit design. It is divided into 5 units covering topics such as sequential circuit analysis and modeling, state diagrams, state tables, asynchronous circuit design, fault diagnosis algorithms, synchronous design using programmable devices, and system design using VHDL. Each unit spans several lecture hours and includes tutorials. The plan lists the topics to be covered in each lecture along with spaces to record the actual date taught and initials to confirm approval by faculty, head of department, and principal.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 4

    SRI ESHWAR COLLEGE OF ENGINEERING

    COIMBATORE 641 202


    LESSON PLAN
    Lecture
    Hours
    Unit No Topics to be Covered
    Actual Date
    of Coverage
    Initial of the
    faculty
    member
    Initial of
    the HOD
    Initial of
    the rincipal
    1
    I
    SEQUENTIAL CIRCUIT DESIGN
    Analysis of cloc!ed synchronous se"uential circuits and
    modeling
    2
    Analysis of cloc!ed synchronous se"uential circuits and
    modeling
    3
    #tate diagram
    4
    Tutorial I
    5
    #tate table
    6
    #tate table assignment and reduction
    7
    Design of synchronous se"uential circuits
    8
    Tutorial II
    9
    Design of iterative circuits
    10
    A#$ chart
    11
    A#$ chart and reali%ation using A#$
    12
    Tutorial III
    13
    II
    ASYNCHRONOUS SEQUENTIAL CIRCUIT
    DESIGN
    Analysis of asynchronous se"uential circuit
    14
    &lo' table reduction
    15
    (aces) state assignment
    16
    Tutorial I
    17
    Transition table and problems in transition table
    18
    Design of asynchronous se"uential circuit
    19
    #tatic) dynamic and essential ha%ards
    20
    Tutorial II
    21
    Data #ynchroni%ers
    22
    $i*ed operating mode asynchronous circuits
    23
    Designing vending machine controller
    24
    Tutorial III
    25
    III FAULT DIAGNOSIS AND TESTABILITY
    ALGORITHMS
    &ault table method
    26
    ath sensiti%ation method
    27
    +oolean difference method
    28
    Tutorial I
    29
    D algorithm
    30
    Tolerance techni"ues
    31
    The compact algorithm
    32
    Tutorial II
    33
    &ault in LA
    34
    Test generation) D&T scheme
    35
    +uilt in self test
    36
    Tutorial III
    37
    IV
    SYNCHRONOUS DESIGN USING
    PROGRAMMABLE DEVICES
    rogramming logic device families
    38 rogramming logic device families
    39
    Designing a synchronous se"uential circuit using
    LA
    40
    Tutorial I
    41
    Designing a synchronous se"uential circuit using
    AL
    42
    (eali%ation of finite state machine using LD
    43
    (eali%ation of finite state machine using LD
    44
    Tutorial II
    45
    &,A
    46
    -ilin* &,A
    47 -ilin* .///
    48
    Tutorial III
    49
    V
    SYSTEM DESIGN USING VHDL
    0HDL operators) Arrays
    50 Concurrent and se"uential statements
    51
    ac!ages) Data flo'
    52
    Tutorial I
    53
    +ehavioral) structural modeling
    54
    Compilation and simulation of 0HDL code
    55
    Test bench
    56 Tutorial II
    57
    (eali%ation of combinational and se"uential circuits
    using HDL
    58
    (egisters) counters ) se"uential machine) serial
    adder ) $ultiplier)Divider
    59
    Design of simple microprocessor
    60
    Tutorial III
    STAFF INCHARGE HOD PRINCIPAL
    Form no. AC 08 R!" 02 R!" #$. 01%05%12

    You might also like