EE539: Analog Integrated Circuit Design

Opamp-summary
Nagendra Krishnapura
Department of Electrical Engineering
Indian Institute of Technology, Madras
Chennai, 600036, India
7 April 2010
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair opamp
inp inn
out
V
dd
I
ref
M
1
M
2
M
3
M
4
M
0
I
0
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair opamp
G
m
g
m1
G
out
g
ds1
+g
ds3
A
o
g
m1
/(g
ds1
+g
ds3
)
A
cm
g
ds0
/g
m3
C
i
C
gs1
/2

u
g
m1
/C
L
p
k
, z
k
p
2
= g
m3
/(C
db1
+C
db3
+2C
gs3
); z
1
= 2p
2
S
vi
16kT/3g
m1
(1 +g
m3
/g
m1
)

2
Vos

2
VT1
+(g
m3
/g
m1
)
2

2
VT3
V
cm
V
T 1
+V
DSAT
1
+V
DSAT
0
V
dd
V
DSAT
3
V
T 3
+V
T 1
V
out
V
cm
V
T 1
V
dd
V
DSAT
3
SR I
0
/C
L
I
supply
I
0
+I
ref
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Cascode output resistance
V
biasc
G
s
R
out
= g
mc
/g
dsc
G
s
+ 1/G
s
+ 1/g
dsc
V
biasc
G
s
=g
ds1
R
out
= g
mc
/g
dsc
g
ds1
+ 1/g
dsc
+ 1/g
ds1
V
bias1
M
c
M
c
M
1
(negligible)
V
biasc
G
s
=g
m1
R
out
= g
mc
/g
dsc
g
m1
+ 1/g
dsc
+ 1/g
m1
M
c
M
1
(negligible)
V
bias1
R
out
= 1/g
dsc
(1+g
mc
/g
m1
)
Vdd
differential pair: M
c
degenerated
by M
1
s source impedance (g
m1
)
Output resistance looking into one side of the differential
pair is 2/g
ds1
(g
m
1
= g
m
c
in the gure)
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Opamp: dc small signal analysis
Bias values in black
Incremental values in red
Impedances in blue
Total quantity = Bias + increment
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair: Quiescent condition
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3
(by symmetry)
V
dd
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3

V
dd
+

zero current
M
1
M
2
M
3
M
4
M
1
M
2
M
3
M
4
I
0
/2
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair: Transconductance
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3

V
dd
+

g
m
v
d
M
1
M
2
+v
d
/2 -v
d
/2
g
m
v
d
/2
g
m
v
d
/2
g
m
v
d
/2
v
x
~ 0
M
3
M
4
I
0
/2
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair: Output conductance
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3

V
dd
+

M
1
M
2
+v
T
v
T
g
ds1
/2
v
T
g
ds1
/2
v
T
g
ds1
/2
v
T
g
ds1
/2 + v
T
g
ds3
M
3
M
4
I
0
/2
v
T
(g
ds1
+ g
ds3
)
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode: Quiescent condition
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3

V
dd
+

zero current
M
1
M
2
M
3
M
4
I
0
/2
V
biasp2
V
biasn2
M
5
M
6
M
7
M
8
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode: Transconductance
M
1
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3

V
dd
+

M
2
M
3
M
4
+v
d
/2
v
x
~ 0
-v
d
/2
g
m
v
d
/2
g
m
v
d
/2
g
m
v
d
g
m
v
d
/2
g
m
v
d
/2
g
m
v
d
/2
I
0
/2
V
biasp2
V
biasn2
M
5
M
6
M
7
M
8
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode: Output conductance
M
1
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
-V
GS3

V
dd
+

M
2
M
3
M
4
I
0
/2
+v
T
g
ds1
/2
g
ds5
g
ds1
/2g
m5
v
T
g
ds5
g
ds1
/2g
m5
v
T
g
ds5
g
ds1
/2g
m5
v
T
g
ds5
g
ds1
/2g
m5
v
T
g
ds5
g
ds1
/2g
m5
v
T
g
ds5
g
ds1
/2g
m5
+ v
T
g
ds7
g
ds3
/g
m7
v
T
(g
ds5
g
ds1
/g
m5
+ g
ds7
g
ds3
/g
m7
)
V
biasp2
V
biasn2
M
5
M
6
M
7
M
8
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode: Quiescent condition
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
I
1
I
1
I
1
I
1
I
0
/2+I
1
I
0
/2+I
1
V
GS3

+

zero current
M
9
M
10
M
5
M
6
M
7
M
8
V
biasp1
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode: Transconductance
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
I
1
I
1
I
1
I
1
I
0
/2+I
1
I
0
/2+I
1
V
GS3

+

M
9
M
10
M
5
M
6
M
7
M
8
+v
d
/2
v
x
~ 0
-v
d
/2
g
m
v
d
/2 g
m
v
d
/2
V
biasp1
g
m
v
d
/2
g
m
v
d
/2
g
m
v
d
/2 g
m
v
d
/2
g
m
v
d
/2
g
m
v
d
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode: Output conductance
V
cm
V
cm
I
0
/2 I
0
/2
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
I
1
I
1
I
1
I
1
I
0
/2+I
1
I
0
/2+I
1
V
GS3

+

zero current
M
9
M
10
M
5
M
6
M
7
M
8
V
biasp1
+v
T
g
ds1
/2
v
T
g
ds5
g
ds1
/2g
m5
+ v
T
g
ds7
g
ds3
/g
m7
v
T
g
ds5
(g
ds1
/2+gds
9
)/g
m5
v
T
(g
ds5
(g
ds1
+g
ds9
)/g
m5
+ g
ds7
g
ds3
/g
m7
)
v
T
g
ds5
g
ds1
/2g
m5

v
T
g
d
s
5
g
d
s
1
/
2
g
m
5

v
T
g
d
s
5
g
d
s
1
/
2
g
m
5

Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair: Noise
+

V
cm
V
cm
V
dd
-V
GS3
i
n1
i
n3
i
n2
i
n4
i
n0
i
n0
/2+i
n1
/2-i
n2
/2+i
n3
i
n0
/2-i
n1
/2+i
n2
/2
i
n0
/2+i
n1
/2-i
n2
/2
i
n0
/2+i
n1
/2-i
n2
/2+i
n3
i
n1
-i
n2
+i
n3
-i
n4
i
n0
i
n0
/2+i
n1
/2-i
n2
/2 i
n0
/2-i
n1
/2+i
n2
/2
Carry out small signal linear analysis with one noise
source at a time
Add up the results at the output (current in this case)
Add up corresponding spectral densities
Divide by gain squared to get input referred noise
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode opamp
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
M
5
M
6
M
7
M
8
out
inp inn
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode opamp
G
m
g
m1
G
out
g
ds1
g
ds5
/g
m5
+g
ds3
g
ds7
/g
m7
A
o
g
m1
/(g
ds1
g
ds5
/g
m5
+g
ds3
g
ds7
/g
m7
)
A
cm
g
ds0
/g
m3
C
i
C
gs1
/2

u
g
m1
/C
L
p
k
, z
k
p
2
= g
m3
/(C
db1
+C
db3
+2C
gs3
)
p
3
= g
m5
/C
p5
p
4
= g
m7
/C
p7
p
2,4
appear for one half and cause mirrror zeros
S
vi
16kT/3g
m1
(1 +g
m3
/g
m1
)

2
Vos

2
VT1
+(g
m3
/g
m1
)
2

2
VT3
V
out
V
biasn1
V
T 5
V
biasp1
+V
T 7
SR I
0
/C
L
I
supply
I
0
+I
ref
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode opamp
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
M
9
M
10
M
5
M
6
M
7
M
8
V
biasp1
out
inp inn
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode opamp
G
m
g
m1
G
out
(g
ds1
+g
ds9
)g
ds5
/g
m5
+g
ds3
g
ds7
/g
m7
A
o
g
m1
/((g
ds1
+g
ds9
)g
ds5
/g
m5
+g
ds3
g
ds7
/g
m7
)
A
cm
g
ds0
/g
m3
C
i
C
gs1
/2

u
g
m1
/C
L
p
k
, z
k
p
2
= g
m3
/(C
db1
+C
db3
+2C
gs3
)
p
3
= g
m5
/C
p5
p
4
= g
m7
/C
p7
p
2,4
appear for one half and cause mirrror zeros
S
vi
16kT/3g
m1
(1 +g
m3
/g
m1
+g
m9
/g
m1
)

2
Vos

2
VT1
+(g
m3
/g
m1
)
2

2
VT3
+(g
m9
/g
m1
)
2

2
VT9
V
out
V
biasn1
V
T 5
V
biasp1
+V
T 7
SR min{I
0
, I
1
}/C
L
I
supply
I
0
+I
1
+I
ref
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Body effect
All nMOS bulk terminals to ground
All pMOS bulk terminals to V
dd
A
cm
has an additional factor g
m1
/(g
m1
+g
mb1
)
g
m5
+g
mb5
instead of g
m5
in cascode opamp results
g
m7
+g
mb7
instead of g
m7
in cascode opamp results
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Two stage opamp
R
c
C
c
R
L
C
L
V
outbias
inn inp
V
dd
I
ref
M
1
M
2
M
3
M
4
M
0
I
0
M
12
M
11
stage 1 stage 2 bias
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Two stage opamp

+
Vdd
R
c
C
c
I
1
single stage
opamp
out
inp
inn
M
11
g
m1
First stage can be Differential pair, Telescopic cascode, or
Folded cascode; Ideal g
m1
assumed in the analysis
Second stage: Common source amplier
Frequency response is the product of frequency responses
of the rst stage g
m
and a common source amplier driven
from a current source
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common source amplier: Frequency response
V
o
(s)
V
d
(s)
=

g
m
1
g
m
11
G
1
G
L

sC
c
(R
c
1/g
m
11
) +1
a
3
s
3
+a
2
s
2
+a
1
s +1
(1)
a
3
=
R
c
C
1
C
L
C
c
G
1
G
L
(2)
a
2
=
C
1
C
c
+C
c
C
L
+C
L
C
1
+R
c
C
c
(G
1
C
L
+C
1
G
L
)
G
1
G
L
(3)
a
1
=
C
c
(g
m
11
+G
1
+G
L
+G
1
G
L
R
c
) +C
1
G
L
+G
1
C
L
G
1
G
L
(4)
G
1
: Total conductive load at the input
G
L
: Total conductive load at the output
C
1
: Total capacitive load at the input
C
L
: Total capacitive load at the output
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common source amplier: Poles and zeros
p
1

G
1
C
c
(
g
m
11
G
L
+1 +
G
1
G
L
+G
1
R
c
) +C
1
(1 +
G
1
G
L
)
(5)
p
2

g
m
11
C
c
C
1
+C
c
+G
L
+G
1
C
c
+C
L
C
1
+C
C
+G1G
L
R
c
C
c
C
1
+C
c
C
1
C
c
C
1
+C
c
+C
L
+
R
c
C
c
(G
1
C
L
+G
L
C
1
)
C
c
+C
L
(6)
p
3

1
R
c

1
C
L
+
1
C
c
+
1
C
1

+
G
1
C
1
+
G
L
C
L

(7)
z
1
=
1
(1/g
m
11
R
c
)C
c
(8)
Unity gain frequency

u

g
m
1
C
c

1 +
G
L
g
m
11
+
G
1
g
m
11
+
G
1
G
L
R
c
g
m
11

+C
1

G
L
g
m
11
+
G
1
g
m
11

(9)
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common source amplier: Frequency response
Pole splitting using compensation capacitor C
c
p
1
moves to a lower frequency
p
2
moves to a higher frequency (For large C
c
,
p
2
= g
m
11
/C
L
)
Zero cancelling resistor R
c
moves z
1
towards the left half s
plane and results in a third pole p
3
z
1
can be moved to with R
c
= 1/g
m
11
z
1
can be moved to cancel p
2
with R
c
> 1/g
m
11
(needs to
be veried against process variations)
Third pole p
3
at a high frequency
Poles and zeros from the rst stage will appear in the
frequency responseY
m1
(s) instead of g
m
1
in V
o
/V
i
above
Mirror pole and zero
Poles due to cascode ampliers
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Compensation cap sizing
p
2

g
m
11
C
c
C
1
+C
c
C
1
C
c
C
1
+C
C
+C
L
(10)

u

g
m1
C
c
(11)
Phase margin(Ignoring p
3
, z
1
, . . .)

M
= tan
1
|p
2
|

u
(12)
|p
2
|

u
= tan
M
(13)
g
m11
g
m1

C
c
C
L

2
=
C
c
C
L

1 +
C
1
C
L

tan
M
+
C
1
C
L
tan
M
(14)
For a given
M
, solve the quadratic to obtain C
c
/C
L
If C
1
is very small, p
2
g
m2
/C
L
; further simplies
calculations
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Two stage opamp
A
o
g
m1
g
m11
/(g
ds1
+g
ds3
)(g
ds11
+g
ds12
)
A
cm
g
ds0
g
m11
/g
m3
(g
ds11
+g
ds12
)
C
i
C
gs1
/2

u
g
m1
/C
c
p
k
, z
k
See previous pages
S
vi
16kT/3g
m1
(1 +g
m3
/g
m1
)

2
Vos

2
VT1
+(g
m3
/g
m1
)
2

2
VT3
V
cm
V
T 1
+V
DSAT
1
+V
DSAT
0
V
dd
V
DSAT
3
V
T 3
+V
T 1
V
out
V
DSAT
12
V
dd
V
DSAT
11
SR+ I
0
/C
c
SR- min{I
0
/C
c
, I
1
/(C
L
+C
c
)}
I
supply
I
0
+I
1
+I
ref
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Opamp comparison
Differential Telescopic Folded Two
pair cascode cascode stage
Gain ++ + ++
Noise = = high =
Offset = = high =
Swing + ++
Speed ++ + +
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential pair
inp inn
out
V
dd
I
ref
M
1
M
2
M
3
M
4
M
0
I
0
Low accuracy (low gain) applications
Voltage follower (capacitive load)
Voltage follower with source follower (resistive load)
In bias stabilization loops (effectively two stages in
feedback)
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Telescopic cascode
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
M
5
M
6
M
7
M
8
out
inp inn
Low swing circuits
Switched capacitor circuits
Capacitive load
Different input and output common mode voltages
First stage of a two stage opamp
Only way to get high gain in ne line processes
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Folded cascode
V
bias0
V
dd
M
1
M
2
M
3
M
4
V
biasp2
V
biasn2
M
9
M
10
M
5
M
6
M
7
M
8
V
biasp1
out
inp inn
Higher swing circuits
Higher noise and offset
Lower speed than telescopic cascode
Low frequency pole at the drain of the input pair
Switched capacitor circuits (Capacitive load)
First stage of a two stage class AB opamp
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Two stage opamp
R
c
C
c
R
L
C
L
V
outbias
inn inp
V
dd
I
ref
M
1
M
2
M
3
M
4
M
0
I
0
M
12
M
11
stage 1 stage 2 bias
Highest possible swing
Resistive loads
Capacitive loads at high speed
Standard opamp: Miller compensated two stage opamp
Class AB opamp: Always two(or more) stages
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Opamps: pMOS versus nMOS input stage
nMOS input stage
Higher g
m
for the same current
Suitable for large bandwidths
Higher icker noise (usually)
pMOS input stage
Lower g
m
for the same current
Lower icker noise (usually)
Suitable for low noise low frequency applications
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Fully differential circuits
M
1
M
3
M
0
M
2
M
4
v
op
v
ip
v
im
v
om
bias
v
ip
v
im
v
op
v
om
half circuits
bias
Two identical half circuits with some common nodes
Two arms of the differential input applied to each half
Two arms of the differential output taken from each half
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Differential half circuit
M
1
M
3
M
0
V
cm
+v
d
/2
M
2
M
4
Line of symmetry
V
cm
-v
d
/2
M
1
M
3
v
d
/2
zero increment
due to symmetry
and linearity
v
o
/2 -v
o
/2 -v
o
/2
Differential
half circuit
Symmetrical
linear (or small signal linear) circuit under fully
differential (antisymmmetric) excitation
Nodes along the line of symmetry at 0V(symmetry,
linearity)
Analyze only the half circuit to nd the transfer function
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common mode half circuit
M
1
M
3
M
0
V
cm
M
2
M
4
V
cm
v
ocm
v
ocm
M
1,2
M
3,4
M
0
V
cm
nbias
pbias
v
ocm
pbias
nbias
Symmetrical
circuit (maybe nonlinear) under common mode(symmmetric)
excitation
Nodes in each half at identical voltages (symmetry)
Fold over the circuit and analyze the half circuit
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common mode feedback
M
1
M
3
M
0
M
2
M
4
v
op
v
ip
v
im
v
om
pbias
nbias
m
o
d
e
d
e
t
e
c
t
o
r
c
o
m
m
o
n
v
op
v
om
v
op
+v
om
2

+
V
o,cm
Fully differential opamp Common mode feedback circuit
Common mode feedback circuit for setting the bias
Detect the output common mode and force it to be V
o,cm
via feedback
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Common mode feedback loop
M
1
M
3
M
0
M
2
M
4
v
op
v
ip
v
im
v
om
pbias
nbias
v
op
+v
om
2

+
V
o,cm
mode
common
detector
break the loop for
analyzing cmfb loop gain
C
gs3,4
Common mode feedback loop has to be stable
Analyze it by breaking the loop and computing the loop
gain with appropriate loading at the broken point
Apply a common mode step/pulse in closed loop and
ensure stability
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Fully differential circuits: Noise
CMFB
M
1
M
3
M
0
V
cm
M
1
M
3
v
n,half
M
2
M
4
V
cm
i
n1
i
n3
i
n1
i
n3
i
n2
i
n4
+ -
v
n,full
S
n,full
= 2S
n,half
half circuit(small signal)
Calculate noise spectral density of the half circuit
Multiply by 2
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Fully differential circuits: Offset
M
1
M
3
v
off,half
v
2
off,full
= 2v
2
off,half
+
+
V
T1
V
T3
M
1
M
3
v
off,full
+
+
V
T1
V
T3
M
2
M
4
+
+
V
T2
V
T4
M
0
V
cm
V
cm
+ -
half circuit(small signal)
V
dd
Calculate mean squared offset of the half circuit
Multiply by 2 if mismatch(e.g. V
T
) wrt ideal device is
used
Nagendra Krishnapura EE539: Analog Integrated Circuit Design
Fully differential circuits: Offset
M
1
M
3
v
off,half
v
2
off,full
= v
2
off,half
+
+
V
T12
V
T34
M
1
M
3
v
off,full
+
+
V
T12
V
T34
M
2
M
4
M
0
V
cm
V
cm
+ -
half circuit(small signal)
V
dd
Calculate mean squared offset of the half circuit
Multiply by 1 if mismatch between two real devices is
used
Nagendra Krishnapura EE539: Analog Integrated Circuit Design