EEL 6713 - Analog Integrated Circuit Design 1

n IV.1 Introduction
n IV.2 Performance parameters
n IV.3 OTA (single-stage op amp)
n IV.4 Cascode and folded-cascode amplifiers
n IV.5 Cascade amplifiers
n IV.6 Fully-differential amplifiers and common-mode
feedback
Chap. IV CMOS Operational Amplifiers
EEL 6713 - Analog Integrated Circuit Design 2
IV.1 Introduction
The ideal op amp
+
v
i
-
+
-
+
Av
i
-
R
S
+
v
o
-
A
R
S
=0
+
v
i
-
+
-
G
m
v
i
G
S
+
v
o
-
G
m
=AG
S
EEL 6713 - Analog Integrated Circuit Design 3
IV.1 Introduction
2 2
1 1
2
1
1
1 1
1
1 1
o
i
v R R
v R R
R
A R

= + +



+ +


Applications of op amps - 1
+
v
i
-
-
+
R
2
R
1
+
v
o
-
Inverting amplifier
2 2
1 1
2
1
1
1
1 1
o
i
v R R
v R R
R
A R
=

+ +


-
+
R
2
R
1
+
v
i
-
+
v
o
-
Noninverting amplifier
EEL 6713 - Analog Integrated Circuit Design 4
IV.1 Introduction
Applications of op amps - 2
Transimpedance amplifier
2 2 2
1
1
1
o
v A
R R R
i A A

=

+

-
+
R
2
i
+
v
o
-
- Continuous-time filters
- SC filters
- D/A & A/D converters
- Sensor signal conditioning
- Voltage & current references
- Comparators
- Nonlinear analog functions,
- .......
EEL 6713 - Analog Integrated Circuit Design 5
IV.1 Introduction
P. Allen and D. Holberg CMOS Analog Circuit
Design, 2nd. Ed., Oxford, New York, 2002.
Op amp design:
Choice of architecture;
Bias currents &
Transistors dimensions;
Compensation;
Simulation;
Layout;
Post-layout simulation
Op amp requirements:
Technology;
Supply voltage;
Gain, GBW, output swing,
noise, offset voltage, PSRR,
ICMR, ....
EEL 6713 - Analog Integrated Circuit Design 6
IV.2 Performance parameters - 1
W.-C. S. Wu et al., Digital-Compatible High-
Performance Operational Amplifier with Rail-
to-Rail Input and Output Ranges, IEEE JSSC,
vol. 29, no. 1, pp. 63-66, Jan. 1994.
Gate channel capacitances are
used for compensation capacitors.
EEL 6713 - Analog Integrated Circuit Design 7
IV.2 Performance parameters - 2
L. Moldovan and H. H. Li, A Rail-to-Rail, Constant Gain, Buffered Op-Amp for
Real Time Video Applications, IEEE JSSC, vol. 32, no. 2, pp. 169-176, Feb. 1997
Op Amp fabricated by MOSIS service in 2-m, n-well CMOS, DPDM
EEL 6713 - Analog Integrated Circuit Design 8
IV.2 Performance parameters - 3
J. F. Duque-Carrillo et al., 1-V Rail-to-Rail Operational Amplifiers in Standard
CMOS Technology, IEEE JSSC, vol. 35, no. 1, pp. 33-44, Jan. 1990
EEL 6713 - Analog Integrated Circuit Design 9
IV.2 Performance parameters - 4
V
id
(mV)
V
od
(V)
V
OS
Offset voltage
Systematic offset results from circuit design and is present even when all
supposedly identical devices are matched (usually can be set to a low value).
Random offset results from mismatches in supposedly identical pairs of
devices (depends on area and bias).
P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design A Tutorial Overview, IEEE
JSSC, vo. 17, n0. 6, pp. 969-982, Dec. 1982.
EEL 6713 - Analog Integrated Circuit Design 10
IV.2 Performance parameters - 5
P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design A Tutorial Overview, IEEE
JSSC, vo. 17, n0. 6, pp. 969-982, Dec. 1982.
Differential voltage gain
d
dB
A
Extrapolated unity-
gain frequency
1
p
0 dB
EEL 6713 - Analog Integrated Circuit Design 11
IV.2 Performance parameters - 6
P. Allen and D. Holberg CMOS Analog Circuit Design, 2nd. Ed., Oxford, New York, 2002.
Settling time
EEL 6713 - Analog Integrated Circuit Design 12
IV.2 Performance parameters - 7
CMRR, PSRR, Slew rate, Noise, Common-Mode Input Range,
Output Swing, Power, Silicon Real State, ....
Dynamic Range (DR)
,max
,min
20log
in
in
v
DR
v

=



Noise (distinguish between
signal and noise)
Distortion (within acceptable
level: application-dependent).
EEL 6713 - Analog Integrated Circuit Design 13
IV.3 OTA (single-stage op amp) - 1
Or current-mirror op amp (Johns & Martin)
/symmetric OTA (Laker & Sansen)
V
SS
I
T
+
v
G1
-
M
1
M
2
I
1
I
2
+
v
G2
-
1:B CM 1:B CM
1:1 CM
C
L
BI
1
BI
2
BI
1
I
o
= B(I
2
-I
1
)
EEL 6713 - Analog Integrated Circuit Design 14
IV.3 OTA (single-stage op amp) - 2
K. Laker and W. Sansen: Design of
Analog Integrated Circuits and
Systems, McGraw-Hill, 1994
Fig. AP6-1
Bias circuitry
Cascode output
Low-gain
diff. amp.
EEL 6713 - Analog Integrated Circuit Design 15
IV.3 OTA (single-stage op amp) - 3
D. Johns and K. Martin, Analog
Integrated Circuit Design, Wiley,
1997.
EEL 6713 - Analog Integrated Circuit Design 16
IV.3 OTA (single-stage op amp) - 4
Input common-mode range: see diff. amp.
( )
T
L P
BI
SR
C C
=
+
1 2 id g g
v v v =
C
L
+C
P
1 m id
Bg v
o
R
+
v
o
-
( )
( )
1
1
m o
d
o L P
Bg R
A s
sR C C
=
+ +
( )
1
1
( )
2
m
L P
Bg
GBW Hz
C C
=
+
I
o
= B(I
2
-I
1
)
V
SS
I
T
+
v
G1
-
M
1
M
2
I
1
I
2
+
v
G2
-
1:B CM 1:B CM
1:1 CM
BI
1
BI
2
BI
1
C
L
CM delays were neglected
asymmetry
EEL 6713 - Analog Integrated Circuit Design 17
IV.4 Cascode & folded-cascode amplifiers - 1
Telescopic diff. amp. with
self-biased cascode CM
Telescopic diff. amp. with
high-swing cascode CM
- Reduced output swing;
-Doublet !
- Not applicable to low
supply voltage.
EEL 6713 - Analog Integrated Circuit Design 18
IV.4 Cascode & folded-cascode amplifiers - 2
D. Johns and K. Martin, Analog Integrated
Circuit Design, Wiley, 1997.
Low-gain diff. amp. High-gain diff. amp.
EEL 6713 - Analog Integrated Circuit Design 19
IV.4 Cascode & folded-cascode amplifiers - 3
P.R. Gray, P.J. Hurst, S.H. Lewis, and
R.G. Meyer, Analysis and Design of
Analog Integrated Circuits, 4th. Ed.,
Wiley, 2001.
EEL 6713 - Analog Integrated Circuit Design 20
IV.4 Cascode & folded-cascode amplifiers - 4
I
T
I
T
/2
I
T
I
T
/2
I
T
/2
I
T
/2
I
T
i
i i
i
i
2i
P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G.
Meyer, Analysis and Design of Analog
Integrated Circuits, 4th. Ed., Wiley, 2001.
Can be changed to
increase positive
output swing
Folded-cascode amplifier - 1
EEL 6713 - Analog Integrated Circuit Design 21
IV.4 Cascode & folded-cascode amplifiers - 5
0
0
1
d
d
L
A
A
sC R

+
P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G.
Meyer, Analysis and Design of Analog
Integrated Circuits, 4th. Ed., Wiley, 2001.
Folded-cascode amplifier - 2
ICMR : Exercise
Output swing : Exercise
Note: The output swing can be around
-V
SS
+2V
DSsatp
to V
DD
-2V
SDsatp
for high-
swing current mirror and optimized bias.
R
o
T
L
I
SR
C

=
0 d m o
A G R =
& doublet
1 m m
G g =
( )
4
4
4
2
12 2
2
1
ds A
o ds
o ms A
ds A
ds ds
ms A
g
G g
R g
g
g g
g
= =
+ +
High-swing current mirror
EEL 6713 - Analog Integrated Circuit Design 22
IV.4 Cascode & folded-cascode amplifiers - 6
K. Bult & G.J.G.M. Geelen, A fast-settling CMOS op
amp for SC circuits with 90-dB DC gain, IEEE JSSC,
no.6, pp. 1379-1384, Dec. 1990.
The gain-boost technique - 1
Stacked devices reduce output swing.
Cascade amplifiers: stability?
1 2
2
2
2
2 1 2 1
1 1
ds ds
mg dd
mg
dd mg
o
ds ds ds ds
g g
g n A
g
A g
R
g g g g

+
+ +



=
EEL 6713 - Analog Integrated Circuit Design 23
IV.4 Cascode & folded-cascode amplifiers - 7
The gain-boost technique - 2
P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G.
Meyer, Analysis and Design of Analog
Integrated Circuits, 4th. Ed., Wiley, 2001.
EEL 6713 - Analog Integrated Circuit Design 24
IV.4 Cascode & folded-cascode amplifiers - 8
The gain-boost technique - 3
P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G.
Meyer, Analysis and Design of Analog
Integrated Circuits, 4th. Ed., Wiley, 2001.
EEL 6713 - Analog Integrated Circuit Design 25
IV.5 Cascade amplifiers
Two-stage amplifiers - 1
ICMR: see diff. amp.
V
DD
Output swing:
4 5 DD DSsat o SS DSsat
V V V V V > > +
Low-voltage gain:
1 6
2 2 6 7
o m m
do
i ds ds ds ds
LF
v g g
A
v g g g g
= =
+ +
C
L
V
SS
M
4
M
3
M
1
M
2
M
8
M
5
M
7
M
6
I
T
v
i
+
-
C
C
v
o
1:1 1:B
1:1
1:2B
inv
noninv
For systematic offset 0.
Early effect at the output
1:2B
EEL 6713 - Analog Integrated Circuit Design 26
IV.5 Cascade amplifiers
( )
1
2 1
2 1
o x
o o T
o C C
C
o o o o
o o L
L
d v v
dv dv I
I C C
dt dt dt C
dv dv I I
I I C
dt dt C

= =

= + =
Two-stage amplifiers - 2
C
C
C
L
v
o
G
mI
-A
dII
I
o1
I
o2
v
i
+
-
v
x
T
C
I
SR
C

=
6max
( 1)
B
ext
L
I B I
SR SR
C
+ +
+
>
( 1)
T
ext
L
B I
SR
C

=
The output node can be the SR limiting node*
*For a discussion, see Laker & Sansen, pp. 510-512
EEL 6713 - Analog Integrated Circuit Design 27
IV.5 Cascade amplifiers
0 0
max
; sin ;
o o
o
dv dv
SR v A t A SR
dt dt
= =
Two-stage amplifiers - 3
Amplitude x frequency limitation due to SR
J. Dostl, Operational Amplifiers, 2nd.
Ed., Butterworth-Heinemann, Boston,
1993.
Amplitude limitation
SR-limited slope
EEL 6713 - Analog Integrated Circuit Design 28
IV.5 Cascade amplifiers
Two-stage amplifiers - 4
( )
( )
( ) ( )
1
=
+
o
in
A s
V
s
V A s F s
Determines the poles of
the closed-loop system
Allen & Holberg, 1st ed.
EEL 6713 - Analog Integrated Circuit Design 29
IV.5 Cascade amplifiers
Two-stage amplifiers - 5
x x x x
1
I I
R C

1
II II
R C

1
p
2
p
j

s-plane
The op amp design must
take into account both load
and feedback loop

M
Allen & Holberg, 1st ed.
EEL 6713 - Analog Integrated Circuit Design 30
IV.5 Cascade amplifiers
Two-stage amplifiers - 6
Response of second order system with various phase margins
Allen & Holberg, 1st ed.
EEL 6713 - Analog Integrated Circuit Design 31
IV.5 Cascade amplifiers
Two-stage amplifiers - 7
Equivalent differential circuit
+
v
in
-
R
I gm
I
v
in
C
I
+
v
I
-
gm
II
v
I
R
II
C
II
+
v
o
-
C
C
1 mI m
g g =
( )
1
2 4
2 4 6 6
I ds ds
I db db gb gs
R g g
C C C C C

= +
= + + +
6 mII m
g g =
( )
1
6 7
6 7
II ds ds
II db db L
R g g
C C C C

= +
= + +
If C
C
0, then
( )
( ) ( )
1 1
o mI mII I II
in I I II II
V g g R R
s
V sR C sR C

+ +
Poles relatively close phase margin
can be low or even negative !!!
Exercise: Derive the transfer function A
d
(s)
of the compensated operational amplifier
EEL 6713 - Analog Integrated Circuit Design 32
IV.5 Cascade amplifiers
Two-stage amplifiers - 8
( ) ( )
( )
( )( )
0
1 2
1
1 / 1 /
d
o
d
in
A s z
V
A s s
V s p s p

= =

Compensated operational amplifier
0 d mI mII I II
A g g R R =
( ) ( )
1
1 1
I I C II II C mII I II c mII I II c
p
R C C R C C g R R C g R R C

+ + + +
( )
2
mII c
I II
mII
I I I C I I
g C
p
C C C C C
g
C

+ +
mII
c
g
z
C
=
x x x x
s plane
pole splitting
mII
c
g
z
C
=
1
I I
R C

1
II II
R C

1
p
2
p
j

Note:
0 1
2 /
d mI C
GBW A p g C = =
/
T C
SR I C =
( )
( )
/ 1 1
2
T mI t f
SR
I g n i
GBW

= = + +
EEL 6713 - Analog Integrated Circuit Design 33
IV.5 Cascade amplifiers
Two-stage amplifiers - 9
x
















x
s-plane
mII
c
g
z
C
=
1
p
2
p
j

To avoid low phase margin,

choose
2
, 2 > p z GBW
1
2
m
C
g
GBW
C
1 1
2
2 2
tan tan
2

M
GBW GBW
p z
1 1
6 6
( / )

+ +


m I II C I II m
m C m
g C C C C C g
g C g
EEL 6713 - Analog Integrated Circuit Design 34
IV.5 Cascade amplifiers
Two-stage amplifiers - 10
Laker & Sansens book
Simplified model for noise analysis
(input-referred noise current source not accounted for)
2 2
2
2 2
2
oI nI
d
oII nII
vII
v e
A
f f
v e
A
f f
=

=

A
d
is the op amp voltage gain
A
vII
is the voltage gain relative to the second noise source. For the
calculation, account for the output impedance of the first stage and
compensation network)
2
nI
e
compensation
2
nII
e
o
v
EEL 6713 - Analog Integrated Circuit Design 35
IV.5 Cascade amplifiers
Two-stage amplifiers - 11
NOTE: white noise only
K. Laker and W. Sansen: Design of
Analog Integrated Circuits and
Systems, McGraw-Hill, 1994
Open-loop output noise of a Miller OTA
1st stage
2nd stage
A
vII
A
d
EEL 6713 - Analog Integrated Circuit Design 36
IV.5 Cascade amplifiers
Two-stage amplifiers - 12
Two-stage CMOS op amp with a cascode current mirror load in the input stage
P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G.
Meyer, Analysis and Design of Analog
Integrated Circuits, 4th. Ed., Wiley, 2001.
This connection reduces the
feedforward current through C
when comparing to connecting
C to node Y
EEL 6713 - Analog Integrated Circuit Design 37
IV.5 Cascade amplifiers
Two-stage amplifiers - 13
P. Allen and D. Holberg CMOS
Analog Circuit Design, 2nd. Ed.,
Oxford, New York, 2002.
CMOS two-stage op amp using nulling resistor compensation
EEL 6713 - Analog Integrated Circuit Design 38
IV.5 Cascade amplifiers
Two-stage amplifiers - 14
CMOS two-stage op amp using nulling resistor compensation
P. Allen and D. Holberg CMOS
Analog Circuit Design, 2nd. Ed.,
Oxford, New York, 2002.
1
1
mII I II c
p
g R R C

( )
2
mII c
I II
mII
I I I C I I
g C
p
C C C C C
g
C

+ +
( )
6
1
1/
c z m
z
C R g
=

3
1
z I
p
R C
=
Placing z on top of p
2
:
6 6
1 1
c II
z
m c
c L
m c
C
C
C
R
g C
C
g
C

+
=



+


High-frequency pole
Determined by source/drain
and gate voltages, and W/L
EEL 6713 - Analog Integrated Circuit Design 39
IV.5 Cascade amplifiers
Two-stage amplifier: design equations - 1
0 1 2
1
1
2 4
6
2
6 7
d d d
m
d
ds ds
m
d
ds ds
A A A
g
A
g g
g
A
g g
=
=
+
=
+
( )
2
mII c
I II
mII
I I I C I I
g C
p
C C C C C
g
C

+ +
mII
c
g
z
C
=
0 1
2 /
d mI C
GBW A p g C = =
/
T C
SR I C =
C
L
V
SS
M
4
M
3
M
1
M
2
M
8
M
5
M
7
M
6
I
T
v
i
+
-
C
C
v
o
1:1 1:B
1:1
1:2B
inv
noninv
V
DD
EEL 6713 - Analog Integrated Circuit Design 40
IV.5 Cascade amplifiers
Two-stage amplifier: design equations - 2
7 7 SS DSsat o DD DSsat
V V V V V + < <
max
min
ICM
ICM
V
V
=
=
See diff. amp.
CMRR, noise (white & 1/f),
PSRR

, (random) offset voltage,

C
L
V
SS
M
4
M
3
M
1
M
2
M
8
M
5
M
7
M
6
I
T
v
i
+
-
C
C
v
o
1:1 1:B
1:1
1:2B
inv
noninv
V
DD