5

Power Input

SDRAM

ADC
Inputs

Flash
EPROM

ADC
Page 10

4...6 Volt Main Power Supply

Page 2

Power Regulators

ECC optional

+5 Volt
charge
pump

Page 5

Page 6

JTAG
connectors

1,8 Volt

JTAG I/O

3,3 Volt

Page 3

CMC Connector
Page 7

Ethernet and
Power
Connector

Altera
EPXA1F484C3
FPGA

Intel
LXT971ALC
Ethernet Phy

TTCrx and
PLL Clock
Recovery

Page 4

Page 4

FPGA Decoupling on Page 11

Page 9

Optical
Link

IC Bus

CPLD serial shiftregisters

for slow I/Os. Page 8

DCS to ROB Connector

Page 8

see grounding scheme on page 14 see

PLL configuration table on page 13

Title

Overview for the DCS board

Size
A4

Document Number
01

Date:
5

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

2005.12.20
2

10:30

Rev
1.64
Sheet

1
1

of

14

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15

SDQ[15:0]

B20
C20
F18
C21
E20
F19
F20
G18
H19
G20
E22
H18
G21
H20
H17
H22

MT48LC16M16_TSOP54

D13
A15
F13
C13
E13
D14

DQ-ECC0
DQ-ECC1
DQ-ECC2
DQ-ECC3
DQ-ECC4
DQ-ECC5

These pins are reserved

for future functionallity
and should be left
unconnected

DQM0
DQM1
CS-N0
CS-N1
DQS0
DQS1

D22
J17

DDR-VS0
DDR-VS1
DDR-VS2

D21
G22
B15

1
2
3
4

SDR_CLK
SDR_SDR_
SDR_CKE
SDR_RAS
SDR_WE
SDR_DQML
SDR_DQMH
SDR_CS

E21
J20
G15
B16

8
7
6
5

8
7
6
5
4x330R

C14
F14

RN32

R7
10k

3V3

1
14
27
3
9
43
49
6
12
46
52

RN38

4x330R
R8
10k

17
37
15
39
18
16
19

RN21
4x330R

4x330R

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

CLK

2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15

CAS
CKE
DQML
DQMH
RAS
WE
CS
VDD1
VDD2
VDD3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VSSQ1
VSSQ2
VSSQ3
VSSQ4

NC

40

28
41
54

RAS
WEn

DQM-ECC
DQS-ECC

RN20

A17
E15

38

8
7
6
5

B13
G13

CASn
CLKE

C15
J16

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
BA0
BA1

1
2
3
4

SDRAM Interface pins are not

available as user I/Os!

3V3
CLK
CLKn

1
2
3
4

SDRAM Interface

8
7
6
5

23
24
25
26
29
30
31
32
33
34
22
35
36
20
21

1
2
3
4

IC1B
EPXA1F484C3

B17
G16
D16
F16
A19
E16
B18
F17
C17
D17
B19
D18
D19
C19
E18

GND1
GND2
GND3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

IC5

SDA0
SDA1
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10
SDA11
SDA12
SDA13-BA0
SDA14-BA1

3V3

GND

3V3
A

C15

C13

C12

C94

C91

C9

C10

C16

10n

47n

10n

47n

10n

47n

10n

47n

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

Title

DCS SDRAM Interface

Size
A3

Document Number
02

Date:

2003.12.19

14:00

Rev
1.60
Sheet
1

of

14

3
3V3
LED6

IC29 acts as a
level translator
from 1V8 to
3V3.

3V3
3V3

6
5
10
11
14
13

OUTB
OUTB

INA
INB
INC
IND

OUTC
OUTC
OUTD
OUTD

AM26LV31C_SO16

3V3

1
7
9
15

-V
2

16

OUTA
OUTA

G
G

R90
3k3

4
12

P18

Dout1
Dout2
Dout3
Dout4
Dout5

K3
J1
L5
L4
L6
L22
M18

IO_C5
TTC_rdy

H4
H1

BAR43A

page 4 TTCrx

VErrIn

2k2

R81

100R

R83

100R
C95

1n

1n

1n

8
7
6
5
H5

nCE
nCEO
nCS *
CS *
nRS *
nWS *
DATA0

3V3

PTCK
TP21

J5
PTDO

Boot-Flash

nRESET
nPOR

* DEV-OE
* DEV-CLRn

U16
R20

EN_SELECT

H2

Sense1
Sense2
PFI
GND

VCC
WDI
PFO
RST

8
7
6
5

C88
power supply supervisor
and watchdog timer

OUTB

INB
INB

OUTC

INC
INC

OUTD
G
G

C230

INA
INA

IND
IND

14
15
6
7
Header_07x2x2mm

10
9

JTAG Input
CON5

AM26LV32C_SO16

1 2
3 4
5 6
7 8
9 10
1112
1314

differential JTAG
interface receiver

1n

RN42

TP24
PTMS

8
7
6
5

R55

C227

4x10k
10k

TP25

10n
3V3

PTRST
E_Pause

IO_C0 connected to
Ethernet page 9

R67
10k

R77
10k

DEV-OE and DEV-CLRn

where expected not to be
used as dedicated pins

R73
150R
OC4
4

C190
10n

R65
150R

100R

nCfgIn

OC5
3V3

page 6 flash eprom

C26

RSTn

page 5 power
page 8 DCS-ROB con

330R

LTV357T

page 8 DCS-ROB
con

1
10n

2
LTV357T
OC2

page 5 power

C148

nShdwn

R24
4k7

R101

150R

2
LTV357T

OC1

C109

CRSTI
4

1n

VERR
R104

OC3
1

D16

100n

LTV357T

1n

R173
100R

2
1

C86
TPS3306-18DGK

4
12

R56
3k3

1
2
3
4

TP23

11

JTAG_Drvr_Dis

PTDI
TP22

G3
G7
G2
H6
G6

Proc-TCK
Proc-TDI
Proc-TDO
Proc-TMS
Proc-TRST

DATA1 *
DATA2 *
DATA3 *
DATA4 *
DATA5 *
DATA6 *
DATA7 *

RSTn

R15
4k7

1
2
3
4

5
MTDI

Y11
T20
J4
U11
J6

TCK
TDI
TDO
TMS
TRST

Configuration pins and ports

DCLK
CLKUSR *

13

TMS

OUTA

10n

TP2

IC8

R18
100k

JSELECT

TD_EF

WD_In

1V8

1V8

K6

EPXA1F484C3

MRSTn

3V3

100n

INIT-DONE *
CONF-DONE

C89
MRSTn
TP13

DEBUG-EN

IC1D

R21

ShdwnNext

C224

Shaded area shows

devices not used for
KIP/TRD

RDYnBSY *
nSTATUS
nCONFIG
MSEL0
MSEL1

R172
100R

TD_FC
IC6

Boot_Fl

C225

R171
100R

EN_SELECT is reserved for future use. Connect to GND.

GND

R98

0R_Jmpr

CRSTO

page 8 DCS-ROB con

TCK

Pins with an (*) are available as

user I/O, too.

R88

differential JTAG interface driver

R102
10k

R16
L7

R91
47k

3V3

D19
2

1 2
3 4
5 6
7 8
9 10

10k

page 8
DCS-ROB
con

to TTCrx
page 4

MTDO

R87
100k

GND

2
3

RN5 4x22R
1
8
2
7
3
6
4
5
1
8
2
7
3
6
4
5
RN6 4x22R

VCC

IC4

1 2
3 4
5 6
7 8
9 10
1112
1314

P19
H3
N20
P17
P16
M21

ShdwnNext

IO_C2

Out

MTCK

CON9

K7
V12

IO_C4

330R

IC29
LMV7239M5

R161

C
Header_07x2x2mm
JTAG Master Output

R5
T3

10n

K4
AB12
R4

10n

-In

100n

100n

TCK

10k

C136

+In

470n

Init_Done
TP4
R132

C76

10k

C82

R160

4x10k

CON4

TP3 nSTATUS

connected to
TTCrx page 4

3V3

+V

C83

1V8

10n

page 8 DCS-ROB con

Dout0
10k

470n

RN4

R14
10k

10k

page 8 DCS-ROB con

nCfgNext
R159

C80

TMS

TD_CE

100R

R116

NC7SV86P5X

IO_C6
IO_C3

page 4 TTCrx
R97

R117

IO-150
IO-153
IO-151
IO-148

VCC

3
2
1

16

IO-147
IO-149
IO-141 Block 13 I/Os
IO-146

M19
M17
M16
L21 ASclk

5
IO_C1

GND
B
A

VCC

L1intTrig

N22
N16
M22 E_MJTG
M20 MTDI

Out

C77

GND

L17
L18
L19
L20

IO-157
IO-154
IO-155
IO-152

IC27

R170
100R
C78

IO_C7

IO-140
IO-142
IO-144
IO-138

K15
L15
L16
K17

R22
P22
P20

AP1
AP2
ARstn
ACSn

MTMS

IO-159
IO-158
IO-156

3V3

Debug_EN

R22
10k
debug_en must be high
to switch off internal
watchdog timer for
testing and debugging!

connected to
ADC page 10

IC1L

R115
0R_Jmpr

IO-139
IO-137
IO-143
IO-145

R121
150R

K18
K19
K20
K21

ARdyn
ADout
ADin
ADMCLK

MTDIn

Test_Point
TP29
1

MTDIp

Header_05x2x2mm
standart JTAG IF

R76
0R_Jmpr

green_0603

SDA
EPXA1F484C3

SCL

TTCrx page 4

2
3V3

1
2
3
4

4
1

C149
10n

R61

150R
AN_GND ( adjacent
neibourhood board ground )

LTV357T
AN_GND

BAR43A
optional

TDOFn

TDOFp

Company : KIP Uni-Heidelberg / Lindenstruth

Title
Size
A3

Date:

Editor : Dirk Gottschalk

DCS JTAG Interface

Document Number
03
2005.02.18

13:40

Rev
1.62
Sheet

of

14

VEE/GND

Outp

VCC

GND

GND

VCC

BCnt0
BCnt1
BCnt2
BCnt3
BCnt4

AUX connector page 7

B
BCntStrb
BCnt8
EvCntLStr
BrcstStr2
BCnt9
BCnt3
BCnt4
SerBChan
BCnt0
BCnt1
EVCntRes
BCnt10
BCnt5
Brcst5
BCnt6
BCnt7
Brcst4
Brcst7
BCnt11
EvCntHStr

U4
W3
T5
T4
V3
T6
W2
T7
U3
W1
T8
V2
U2
R3
P5
P4
R7
R2
P3
P6

IO-0
IO-1
IO-2
IO-3
IO-4
IO-5
IO-6
IO-7
IO-8
IO-9
IO-10
IO-11
IO-12
IO-13
IO-14
IO-15
IO-16
IO-17
IO-18
IO-19

IC1H
EPXA1F484C3

Block 9 I/Os

IO-20
IO-21
IO-22
IO-23
IO-24
IO-25
IO-26
IO-27
IO-28
IO-29
IO-30
IO-31
IO-32
IO-33
IO-34
IO-35
IO-36
IO-37
IO-38

R1
P7
P2
P1
N5
N4
N6
N3
N2
N7
N1
M5
M4
M3
M6
L1
M7
L2
L3

BCnt6
BCnt7
BCnt8
BCnt9
BCnt10
BCnt11

Brcst6
SinErr
BCnt2
ClkL1Acc
Brcst3
BrcstStr1
Brcst2
SubAd7
SubAd0
DBErr
SubAd1
SubAd2
SubAd4
SubAd6
SubAd3
DoutStr
SubAd5
Dout7
Dout6

EvCntHStr
EvCntLStr
BCntStrb
Brcst2
Brcst3
Brcst4
Brcst5
Brcst6
Brcst7
BrcstStr1
BrcstStr2
EVCntRes

BCnt0
BCnt1
BCnt2
BCnt3
BCnt4
BCnt5
BCnt6
BCnt7
BCnt8
BCnt9
BCnt10
BCnt11

L7
M7
G7
K6
M6
L6
J6
J5
M5
L5
L4
H6

EvCntHStr J7
EvCntLStr K8
BCntStrb
L8
Brcst2
Brcst3
Brcst4
Brcst5
Brcst6
Brcst7

D12
D11
J11
J10
K11
K9

BrcstStr1 D10
BrcstStr2 K12
EVCntRes

L9
M9

Shaded area shows

devices not used for
KIP/DCS

ROB connector page 8

R13

BCnt0
BCnt1
BCnt2
BCnt3
BCnt4
BCnt5
BCnt6
BCnt7
BCnt8
BCnt9
BCnt10
BCnt11

TTC_TCK

I1
GND
I0

S
VCC
Out

6
5
4

NC7SV157P6X 2-in Mux

R114

10k

A
B
GND

VCC
Out

2R2

C96

C97

C98

C100

100n

470n

100n

10n

R64
51R

EPXA1F484C3

330R

Clk40
TP27

5
VCC

Dout0
Dout1
Dout2
Dout3
Dout4
Dout5
Dout6
Dout7
SubAddr0
SubAddr1
SubAddr2
SubAddr3
SubAddr4
SubAddr5
SubAddr6
SubAddr7
DQ0
DQ1
DQ2
DQ3
DoutStr
Serial_B_Channel
ClockL1Accept
SinErrStr
DbErrStr
Reset_b
TTC_Ready
D_VDD_C1
D_VDD_C2
D_VDD_C3

U17
Y22

R35

CLKLK-out2p
CLKLK-FB2p

F12
G12
H11
J8

R16

470R

B6
C6
B5
C5
D5
A4
B4
C4
E8
E7
B9
A9
C9
A8
D8
F6
B7
A7
C7
D7
A6

Dout0
Dout1
Dout2
Dout3
Dout4
Dout5
Dout6
Dout7
SubAd0
SubAd1
SubAd2
SubAd3
SubAd4
SubAd5
SubAd6
SubAd7

K4
F8
E9
C12
C2
D2

SerBChan
ClkL1Acc
SinErr
DbErr

1
2
3
4

SerBChan
ClkL1Acc
SinErr
DbErr
MRSTn

TTC_Rdy

TTC_Rdy
R155
do not populate

8
7
6
5

0R_Jmpr
0R_Jmpr
0R_Jmpr
0R_Jmpr
VregShdn 1
VregShdn 2
VregShdn 3
VregShdn 4

RN48 4x0R_Jmpr

LED2
Lock4

1V8

if_PLL_EN_unused
GND

TPC PLL configuration

table see page 13 !
RN30
1
2
3
4
1
2
3
4

4x47R
8
7
6
5
8
7
6
5

RN31

4x47R

IO_A0
IO_A1
IO_A2
IO_A3
IO_A4
IO_A5
to ROB connector page 8

AUX connector
page 7
JTAG page 3
JTAG page 3

JTAG page 3

RN51
4x10k

RN52
4x10k

3V3

to ROB connector
page 8
RN50
4x10k

3V3

RN49, 50,51 and 52 are TTCrx

start up configuration resistors

R12

C102

C103

C101

470n

100n

10n

2R2

R34
0R_Jmpr

R20
0R_Jmpr

SubAd0
SubAd1
SubAd2
SubAd3
SubAd4
SubAd5
SubAd6
SubAd7

RN49
4x10k

3V3

R33
150R

Dout0
Dout1
Dout2
Dout3
Dout4
Dout5
Dout6
Dout7

TTC_DQ0
TTC_DQ1
TTC_DQ2
TTC_DQ3
ROB connector page 8
DOutStr

DoutStr

G10
G9
H12

R107
R108
R109
R110

R99 0R_Jmpr
R100 0R_Jmpr
R105 0R_Jmpr
L1intTrig

U22
N21

3V3

R68 0R_Jmpr

IC32

LED1
Lock2

1V8

R6

Clocks and PLLs

L1Accept
ROB con. page 8

A
C105
Company : KIP Uni-Heidelberg / Lindenstruth

100n

Title

GND_TPLL

Lock2
Lock4

CLKLK-ENA
C128
optional

U1
R21
V1
P21

IC1E

Size
A3

CLK1p
CLK2p
CLK3p
CLK4p

CLK-REF

PLL_ICLK
R128

Clock40Des2
Clock40Des1
Clock40
L1Accept

BrcstStr1
BrcstStr2

R28
150R
H7

R130
150R

green_0603
2
1

1
2
3

TTC_TDO

TTCrx can shift Clock40Desn phase

in 104ps steps between 0 and 25ns.

EvCntRes
BCntRes

R71
10k
R72
10k

if_PLL_off

1
2
3

TTCrx 3.2

Brcst2
Brcst3
Brcst4
Brcst5
Brcst6
Brcst7

4x47R
8
7
6
5

R69
10k
R70
10k

0R_Jmpr

10n

IC7

EvCntHStr
EvCntLStr
BCntStrb

G3
G4

3V3

100n

NC7SV86P5X

A
B
GND

SCL
SDA
PromD
PromReset
PromClk

BCntRes

IC26

1
H3
J2
C1
D3
E5

10k

51R

3V3

RN19
1
2
3
4

R136
51R

ClkVar1p
ClkVar1n

8
7
6
5

Outn

In
In_b

100n
R112

TRR-1B43

Out

F1
G1

GND1
GND2
GND3
D_GND1
D_GND2
D_GND3
D_GND4
D_GND5
D_GND6
D_GND7
D_GND8
D_GND9
G_GND

C118

D_VDD1
D_VDD2
D_VDD3
D_VDD4
D_VDD5
D_VDD6
D_VDD7
D_VDD8
D_VDD9
D_VDD10
VDD

100n

10n

10n

4x10k

R79
51R

R135

Clock1p
Clock1n
Clock2p
Clock2n

R129
33R

ICS670M-01
IC23

clock line
separation buffer

C66

IC24

TTC_TRST
TP8
1

A5
B8
D1
E12
E3
H9
H1
J12
K7
M4
F5

C117

C119

HFBR-2316T

TP7

16
15
14
13
12
11
10
9

OutAp
OutAn
OutBp
OutBn
OutCp
OutCn
OutDp
OutDn

SN75LVDS391PW
VCC_PLL

Clock40Des1

C120
R30 0R_Jmpr
for TRR-1B43

RN29

R25
100R

AVDD2
AVDD1

0R_Jmpr

4
3
2
1

C85

10n

TTC_TMS

TP6

E2
H2
M8
C8
D6
E1
E4
E10
F7
G5
H10
K5
G2

R27
0R_Jmpr

HFBR-2416
may fit, too,
but pulse width
distortion is
worth than
HFBR-2316T

R26
100R

R29

C62
51R

TTC_TDI

TP5

EN12
InA
InB
VCC
GND
InC
InD
EN34

40MHz1p
40MHz1n

16
15
14
13
12
11
10
9

1
2
3
4

1
2
3
4

for HFBR2316

or HFBR-2316T

Pin

100n

1
2
3
4
5
6
7
8

Trigger1p
Trigger1n
Trigger2p
Trigger2n

OutAp
OutAn
OutBp
OutBn
OutCp
OutCn
OutDp
OutDn

8
7
6
5

5
6
7
8

for HFBR2316
TRR-1B43

10n

1n

EN12
InA
InB
VCC
GND
InC
InD
EN34

1
2
3
4

470n

TP1

100n

8
7
6
5

C92

1n

Keep these signals

as short as possible!

R92

GND Out

470n

1
2
3
4

C90

3V3

NC1
Out
V_O
NC2

EN VCC

leadfree: CFPS-73 40MHz

NC4
P1
P2
NC3

OR1

IQXO-71 40MHz

C93

100n

1
2
3

10uF

1n

470n

A1
A2
A3
A10
A11
A12
B1
B2
B3
B10
B11
B12
C3
C10
C11
D4
D9
E6
F2
F3
F4
F9

C127

470n

100n

C69

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22

C123

100n

470n

3V3

H4
J3
J1
K1
M2

C122

10n

C44

C75

GND_PLL
OSC1

R63
2k2

C50

C261

NC7SV32P5X OR-Gate

R62
2k2

C56

C110

8
7
6
5
4
3
2
1

10n

8
7
6
5

C121

0R_Jmpr

2R2

C112

IC25

GND_PLL

10n
R124

C186

100n

3V3

connect capacitors C44,

C50 and C56 as close as
possible to PLL IC23!

3V3

populate R122 if
Vreg not used

5V

Voltage regulator IC28

only used if low supply
noise for PLL required.

4uF7

10n NPO

R122

*!

1R for CFPS
oscillator !!

3V3

5V

100n

C38

C114

SN75LVDS391PW

2
2R2

C188

R32
2R2

100n

2uF2

JTAG TDI
JTAG TMS
JTAG TDO
JTAG TCK
JTAG_TRST_b

10n

C116

SDA

SDA

C130

C20

NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
D_GND_C1
D_GND_C2
D_GND_C3

C129
R31
2R2

R11

SCL

SCL

Out

to JTAG page 3
for HFBR2316

C124

C126

3V3

BP

F10
F11
G6
H5
H7
H8
J4
J9
K2
K3
K10
L1
L2
L3
L10
L11
L12
M1
M3
M10
M11
M12
E11
G8
G11

0R_Jmpr for TRR-1B43

R168

0R_Jmpr
R169

Please see grounding scheme

for PLL layout on page 12.
R167 0R_Jmpr
for TRR-1B43

for HFBR2316

nShdwn

EN

1
2
3
4
5
6
7
8

3V3

Clock40Des2

100n

SubAd[7..0]

R9
10k

Vout

ICLK
FBIN
S3
OE1
S2
FBCLK
S1
OE2
S0
CLK2
GND3 VDD3
GND2 VDD2
GND1 VDD1

C125

Vin

IC10

8
7
6
5

3V3

PLL frequency is defined by resistors

R68, R99, R100, R105 and R107 to
R110. If the voltage regulator shutdown
feature is not needed the CPLD can
configure the PLL via RN48 which
otherwise is not populated.

green_0603

IC28

2R2

LP3988IMF-3.3 may be
used too but C20 should
be left unpopulated then.

9
10
11
12
13
14
15
16

R123
VCC_In

*! keep this GND connection

near/between TTCrx and IC28 !

Keep <10mm LP3985IM5-3.3

1
2
3
4

GND

Date:

Editor : Dirk Gottschalk

Clock Regeneration and Distribution with TTCrx

Document Number
04
2006.05.03

Rev
1.64
Sheet

of

14

TO220-5

10k

10n

6
ERR

TAB

SD

GND

100n

R37
10k

C79

!*

C134

C133

100n

10n

47uF/10V_Tant

0.2R/1W

GND_PW
GND_PW

20k Connector for current

and input voltage
measurement
0.1R/1W
nShdwn
R150

D18
3

C14

330uF/10V

TO220-5

2
BAR43A

LP3963ET-3.3

BAT54C

Welwyn LR or equ.

D15

VERR
R154

Header_03x2

10k

CON10

1
3
5

C8
<10mm !!

R39
10k

VCC_In

10n

C32

C106

C137

330uF/10V

22uF

100n

IC12

Vin

SD

3V3/3A

R151

Vout

ERR

10k

2
4
6

R152
1k

R38+
10k

TO263-5

C180

C81

C140

C139

100n

10n

!*

R126
10k

GND_PW

1 2
3 4
5 6
7 8
9 10

MVCC

3V3
R106

2R2
C220

Header_05x2

2uF2

5V

IC15

max. 5,5Volt Input

1
2
3
4

nc
Vout
EN
Cpp
Vin
Cpn
GND PGND

8
7
6
5

C219
220n

REG711EA-5

VregTemp
C221

C222

C142

100n

470n

10uF

NTC1
10k

R125
330R

GND_TPLL

Main Power Input 3.8 ... 4.3 Volt

Do not connect Power GND nets
directly to the plane but route via
the voltage regulators and main
supply decoupling capacitors
(10uF and 22uF) !! Use plane keep
out or whatever ....

Q1
BC859C

GND_PW

green_0603

GND_PW

Charge pump for the HFBR2316 optical link receiver

CON8

LED10

100n

PGND*

3V3

47uF/10V_Tant

R153
1k

22uF

C226

1V8

C131

R141

R60

C84

Vout

R147 20k

C11

Vin

TAB

1
2

Header_02x1
CON3

R36

IC11

GND

interrupt GND plane

here. Route to top
layer. Connect all
VReg capacitors to
this vias. Do not
connect caps
directly to plane.

Welwyn LR or equ.

VIAs

<10mm !!

1V8/1,5A

For the National semiconductor

voltage regulators the output
capacitor ESR must be between
0.2R and 5R !! See datasheet !

!*

LP3962ET-1.8

330uF/10V

GND layer
trace to board
ground plane

1
2

GND layer trace

to power input
connectors

All capacitors are 10 Volt minimum.

Kelvin connections to caps preferred!

top layer to
Vreg GND
connection

VReg

Shaded area shows

devices not used for
KIP/DCS

CON10 is for voltage measurement by

the adjacent DCS board. Connect only
differentially to the ADC . Do not
connect the GND pins of one DCS
board here to GND of the other board.
The GND pins must be connected to
one of the differential ADC inputs.

Company : KIP Uni-Heidelberg / Lindenstruth

Title

Editor : Dirk Gottschalk

DCS Board Voltage Regulators

Size
A

Document Number
05

Date:

2005.02.14
2

13:20

Rev
1.63
Sheet

of
1

14

DQ[15:0]

IC1C
EPXA1F484C3

3V3
R82
IC2

EBI-A0
EBI-A1
EBI-A2
EBI-A3
EBI-A4
EBI-A5
EBI-A6
EBI-A7
EBI-A8
EBI-A9
EBI-A10
EBI-A11
EBI-A12
EBI-A13
EBI-A14
EBI-A15
EBI-A16
EBI-A17
EBI-A18
EBI-A19
EBI-A20
EBI-A21
EBI-A22
EBI-A23
EBI-A24

C5
A4
D7
A5
E7
B6
C7
A6
F8
B7
D8
C8
E8
A7
G9
B8
F9
A8
E9
C9
D9
B9
H10
A9
G10

EBI-WEn
EBI-OEn
EBI-BE0
EBI-BE1

G8
D2
D1
H9

EBI-CS0
EBI-CS1
EBI-CS2
EBI-CS3

C2
B3
D3
C4

EBI-ACK
EBI-CLK

B4
C3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
R1

ACK is claimed to be
unreliable in Errata Sheet ver.
1.2 Febr. 2003 page2 !! So
ACK should not be used !
B

AT49BV322AT

R1

Am29LV320D

BYTE
OE
RST
WE
CE

37

VCC

RN1 4x10k
5
4
6
3
7
2
8
1

R111 0R_Jmpr

14

WP/ACC

3V3

R3

R5
10k

GND2
IRQn
D15
D14
D13
D12
D11
D10
D9
D8
res2
VCCQ
GND3
D7
D6
D5
D4
D3
D2
D1
D0
busyn
ID1
GND4

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

BUSYFL

MD2811-Dxx-V3

27
46

GND1
GND2

3V3

0R_Jmpr

R95
0R_Jmpr

RSTn

R2
0R_Jmpr

3V3

IRQFL
D

RSTn
CEn
WEn
OEn
A12
A11
A10
A9
A8
A7
A6
VCC
GND
A5
A4
A3
A2
A1
A0
BHEn
res1
IF_cfg
Lockn
ID0

R75
10k

prog_Flash

R95

LockFL

C6

C7

IFcfgFL

10n

100n

connected to FPGA on
DCS-ROB connector page 8

3V3

X
X

1
2
3
4
A12 5
A11 6
A10 7
A9
8
A8
9
A7 10
A6 11
12
13
A5 14
A4 15
A3 16
A2 17
A1 18
A0 19
20
21
22
23
24

15 RDY_BSY

RY/BY

C2

C4

10n

100n

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

R96
10k

29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1

R113 0R_Jmpr

GND

M29W320DT90N1

MBM29DL164TD

MBM29DL32xTE

47
28
12
11
26

X
X

TE28F320C3TC90
A

R3

AT49BV320AT
Am29DL640D

R2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21

TP16
EBI_Clk

Settings

25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
10
13

10k

IC3

0R_Jmpr

Expansion Bus Interface (EBI) Block 6

EBI pins are not available as user I/Os

AM29LV640D-TSSOP48

DiskOnChip Millenium Plus 16/32MB

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
F10
C10
E10
A10
G11
B10
F11
D11
E11
C11
B11
F12
A12
E12
B12
EBI-DQ0
EBI-DQ1
EBI-DQ2
EBI-DQ3
EBI-DQ4
EBI-DQ5
EBI-DQ6
EBI-DQ7
EBI-DQ8
EBI-DQ9
EBI-DQ10
EBI-DQ11
EBI-DQ12
EBI-DQ13
EBI-DQ14
EBI-DQ15

A[19:0]

EBIA0 :
see
Altera
AN143

Shaded area shows

devices not used for
KIP/DCS

Title

There are two types of Flash Eproms.

Pins 9, 13, 14 and 15 are connected
disparately. Especialy adress pins 19
and 21 are exchanged.

Expansion Bus Interface (EBI)

Size
A4

Document Number
06

Date:

2004.11.23

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

16:30

Rev
1.60
Sheet

6
1

of

14

3V3
3V3
C182
100n
CON6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

SerBChan
EVCntRes
BrcstStr2
BrcstStr1
SubAd0
SubAd1
SubAd2
SubAd3

SubAd4
SubAd5
SubAd6
SubAd7
to TTCrx page 4

DbErr
ClkL1Acc
BCnt11
BCnt10
BCnt9
BCnt8
BCnt7
BCnt6
IO_B7
IO_B6
IO_B5
IO_B4

Brcst7
Brcst6
Brcst2
Brcst5

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

Brcst4
Brcst3
Brcst2
SinErr

EVCntLStr
EVCntHStr
BCntStrb
DOutStr

to TTCrx page 4

BCnt0
BCnt1
BCnt2
BCnt3
BCnt4
Dout7
Dout6
IO_B0
IO_B1
IO_B2
IO_B3

Header_30x2

GND_TPLL
to DCS to ROB connector page 8
8
7
6
5

8
7
6
5
1
2
3
4

1
2
3
4
VregShdn 21
VregShdn 22
VregShdn 23
VregShdn 24

4x47R

VregShdn 17
VregShdn 18
VregShdn 19
VregShdn 20

4x47R

RN17

1
2
3
4

Shaded area shows

devices not used for
KIP/TRD

4x47R

RN15

VregShdn 13
VregShdn 14
VregShdn 15
VregShdn 16

1
2
3
4

4x47R

VregShdn 5
VregShdn 6
VregShdn 11
VregShdn 12

4x47R
1
2
3
4

RN13

VregShdn 1
VregShdn 2
VregShdn 3
VregShdn 4

RN12

RN16

8
7
6
5

8
7
6
5

8
7
6
5

ExtInt

IC1M

TP14

INT_EXT_PIN

B5

1
INT

EPXA1F484C3

to DCS to ROB connector page 8

Devices on this
page are not used
for KIP/DCS

Company : KIP Uni-Heidelberg / Lindenstruth

Title
Size
A3

Date:

Editor : Dirk Gottschalk

DCS AUX Connector

Document Number
07
2004.11.23

16:55

Rev
1.60
Sheet

of

14

3V3
connected to
Flash page 6

LED7
2

green_0603

R85

IO_B6

IO_B7
IO_B5
IFcfgFL

IO_B7
IO_B5

AB9

LockFL

AA9

150R prog_Flash

3V3 1V8

IO_D7

IO_B3

IO_B3

IO_B4

IO_B4
IO_D5

0R_Jmpr

IC1I
EPXA1F484C3

Block 10 I/Os

V8
AA6
AA5
V7
Y7
W7
Y6
V5
V4
V6
W5
Y5
U6
Y4
U7
AA4
AB4
U8
AA3
T9
Y3
Y2

3V3

IO_B1

IO_B1

IO_B0
IO_D3
IO_D4
IO_D2

aux5
AUX4

IO_B0

SRStr
connected to
JTAG page 3

TTC_DQ3
BCntRes
TTC_DQ2
L1Accept

IO_D1

CRSTO
CRSTI
AUX3

connected
to TTCrx on
page 4

TTC_DQ1

IO_D0

SRShClk
aux2

TTC_DQ0
AB4

IO_B2

R131
10k

3V3

BUSYFL
C152

C153

10n

100n

3V3

1
2
3
4
5
6
7
8

4x0R_Jmpr

8
7
6
5

C178

C184

10n

100n
LVDSdown5p
LVDSdown5n
LVDSdown7p
LVDSdown7n
LVDSdown6p
LVDSdown6n
LVDSdown8p
LVDSdown8n

LVDSup8n

LVDSup6n

LVDSup7n

LVDSup5n

RN44

AUX4

IO_C6
IO_C4
IO_C2
IO_C0

Shaded area shows

devices not used for
TRD/DCS
GND_PW

1
2
3
4

SCL

AAin8
AAin2

RN2
4x47R

8
7
6
5

51R
R66

1
2
3
4
1
2
3
4

TxD

ClkVar1p
40MHz1p

IC20

to JTAG page 3

LVDSup5p
LVDSdown5p
LVDSup6p
LVDSdown6p
VregShdn 14
VregShdn 16
VregShdn 18

UART

In1p
In1n
In2p
In2n
In3p
In3n
In4p
In4n

5
6
7
8

9
10
11
12
13
14
15
16

4x0R_Jmpr

1
2
3
4

4x0R_Jmpr

RN25

GND

SRDin
SRShClk
SROEn
SRIO

8
7
6
5

EN12
Out1
Out2
VCC
GND
Out3
Out4
EN34

RN43

8
7
6
5

100n

1
2
3
4

C155

10n

16
15
14
13
12
11
10
9

AB17

C154

4
3
2
1

SN75LVDS391PW

4x0R_Jmpr
OutDn
EN34
OutDp
InD
OutCn
InC
OutCp
GND
OutBn
VCC
OutBp
InB
OutAn
InA
OutAp
EN12

8
7
6
5
4
3
2
1

IC17

SN75LVDT390PW

AB15
4
3
2
1
5
6
7
8

4x0R_Jmpr

4
3
2
1
5
6
7
8

SN75LVDT390PW

16
15
14
13
12
11
10
9

EN12
Out1
Out2
VCC
GND
Out3
Out4
EN34
LVDSdown1p
LVDSdown1n
LVDSdown2p
LVDSdown2n

4x47R 4x47R
RN7
RN47

VregShdn 8
VregShdn 10
VregShdn 12

Header_03x2

RN45
1
2
3
4

4x0R_Jmpr
8
7
6
5

to Clock page 4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
SerBChan

RN28 RN46
4x47R 4x47R

C5
10n

R74
51R

VregShdn 2
VregShdn 4

RN3
4x47R

AUX3

C157

C156

100n

100n

1
2
3
4

MVCC

SDA

R166 0R_Jmpr

AAin7
AAin1

0R_Jmpr

IO_C7
IO_C5
IO_C3
IO_C1

LVDSup5n
LVDSdown5n
LVDSup6n
LVDSdown6n
VregShdn 13
VregShdn 15
VregShdn 17

VregShdn 11
R4

8
7
6
5

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69

LVDSup2n
LVDSdown2n
LVDSup1n
LVDSdown1n

LVDSup4n
LVDSdown4n
LVDSup3n
LVDSdown3n
VregShdn 1
VregShdn 3
VregShdn 5

8
7
6
5
8
7
6
5
to Clock IO_A4
IO_A2
page 4
IO_A0
IO_B7
1
IO_B5
2
IO_B3
3
IO_B1
4
IO_D7
1
IO_D5
2
IO_D3
3
IO_D1
4

ClkVar1n
40MHz1n
ExtInt

Clock1n
Clock2n

EPXA1F484C3

Trigger1n
Trigger2n

RxD

10k
R165

W12

GND_PW* -> Do not connect these GND

nets directly to the plane but route via
the voltage regulators and main supply
decoupling capacitors !

CON14

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69

CON13
10k
R164

V11

10k

K5

SRIO

4x0R_Jmpr

1
2
3
4

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69

J2

R163

FAST4

R84
150R

SRMRn

0R_Jmpr

10k

FAST3

RN18 may connect

VRegShdn pins 7 to 10
directly to FPGA if the CPLD
is not populated.

LVDSdown4n

2
4
6

VregShdn 7
VregShdn 9

1
3
5

LVDSdown3n

F1
G4
F2
F6
F3
G5
E2
E6

SRMRn

R162

FAST2

RN27

RN18

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70

Dedicated Fast Inputs

FAST1

R139
10k

AB14

RN24

CON1

to Clock page 4

MRSTn

IC1F

LED8
green_0603

aux1

R138
10k

AA16
AA17

AA10

AA9
AB10
5
6
7
8

4x0R_Jmpr

4
3
2
1
4
3
2
1
5
6
7
8

OutDn
OutDp
OutCn
OutCp
OutBn
OutBp
OutAn
OutAp
9
10
11
12
13
14
15
16

IC18

RN26
1 In1p
2 In1n
3
In2p
4 In2n
5 In3p
6 In3n
7 In4p
8 In4n

Y2
Y3
AA3
AA4

8
7
6
5
4
3
2
1
EN34
InD
InC
GND
VCC
InB
InA
EN12

4
3
2
1

3V3

Clock1p
Clock2p

0R_Jmpr

5
6
7
8

URI
TP26

all VregShdn pins connected on AUX connector

page 7. May be configured as PCI pins.

R57

SROEn

AA14

IC19

SN75LVDS391PW

LVDSup2p
LVDSdown2p
LVDSup1p
LVDSdown1p

VregShdn 19

RN23

LVDSup4p
LVDSdown4p
LVDSup3p
LVDSdown3p
VregShdn 2
VregShdn 4
VregShdn 6

1
UART-CTSn
UART-DSRn
UART-RxD
UART-DCDn
UART-RIn
UART-TxD
UART-RTSn
UART-DTRn

VregShdn 15
VregShdn 16
VregShdn 17
VregShdn 18

100n

IO_A5 to Clock
IO_A3 page 4
IO_A1
8 IO_B6
7 IO_B4
6 IO_B2
5 IO_B0
8 IO_D6
7 IO_D4
6 IO_D2
5 IO_D0

UDCD
TP12

EPXA1F484C3
IC1G

R6

SRDin

3V3

SRStr

VregShdn 11
VregShdn 12
VregShdn 13
VregShdn 14

10n

LVDSup4n

TMS

C151

4x0R_Jmpr

LVDSup3n

VregShdn 22
VregShdn 23
VregShdn 24

AB8
AB6
AA8
AA7

4x0R_Jmpr

VregShdn 20
VregShdn 21

LVDSup1n
LVDSup1p
LVDSup2n
LVDSup2p

100n

aux4
to AUX connector page 7

SRIO

Trigger1p
Trigger2p

C87

36
35
34
33
32
31
30
29
28
27
26
25

RN22

A6
A4
A2
A1
A0_GOE0
CLK0_in
CLK3_in
D0_GOE1
D2
D4
D6
GND3

VCC2
TDO
D8
D10
D12
D15
VCCO_B1
GND_B1
C11
C10
C8
TMS

C150

150R

to AUX connector page 7

1V8
1V8

connected to
JTAG page 3

R137

VregShdn 8
VregShdn 9
VregShdn 10
aux5
TCK

Y14
R13
W14
T13
AB15
AA14
U13
Y13
V13
W13
T12
AB14
AA12
U12
Y12

10k

AB9

2
aux3

VregShdn 7

TDI
A8
A10
A11
GND_B0
IC14
VCCO_B0
B15
B12
LC4064ZC-75T48
B10
B8
TCK
VCC1

GND1
B6
B4
B2
B0
CLK1_in
CLK2_in
C0
C1
C2
C4
C6

VregShdn 6

TCK

3V3

SRDin
SRShClk
SROEn

TD_CE
1
2
3
4
5
6
7
8
9
10
11
12

IO-99
IO-100
IO-101
IO-102
IO-103
IC1J
IO-104
EPXA1F484C3 IO-105
IO-106
IO-107
IO-108
Block 11 I/Os
IO-109
IO-110
IO-111
IO-112
IO-113

3V3

red_0603

100n

48
47
46
45
44
43
42
41
40
39
38
37

VregShdn 1
VregShdn 2
VregShdn 3
VregShdn 4

VregShdn 5

IO-84
IO-85
IO-86
IO-87
IO-88
IO-89
IO-90
IO-91
IO-92
IO-93
IO-94
IO-95
IO-96
IO-97
IO-98

R134

IO_B2

AA15

C223

13
14
15
16
17
18
19
20
21
22
23
24

to AUX connector page 7

Y16
W16
AA17
T15
AB17
U15
V15
AA16
W15
Y15
T14
AB16
U14
AA15
V14

LED9

100n

C185

aux2
aux1

TD_FC

IO_D6

IO-62
IO-63
IO-64
IO-65
IO-66
IO-67
IO-68
IO-69
IO-70
IO-71
IO-72
IO-73
IO-74
IO-75
IO-76
IO-77
IO-78
IO-79
IO-80
IO-81
IO-82
IO-83

LVDSup7n
LVDSdown7n
LVDSup8n
LVDSdown8n
VregShdn 19
VregShdn 21
VregShdn 23

R78

AA10

IO-39
IO-40
IO-41
IO-42
IO-43
IO-44
IO-45
IO-46
IO-47
IO-48
IO-49
IO-50
IO-51
IO-52
IO-53
IO-54
IO-55
IO-56
IO-57
IO-58
IO-59
IO-60
IO-61

LVDSup7p
LVDSdown7p
LVDSup8p
LVDSdown8p
VregShdn 20
VregShdn 22
VregShdn 24

IO_B6

W11
T11
AB10
V10
AA10
W10
Y10
U10
AB9
T10
AA9
R10
Y9
W9
AB8
V9
AA8
AB6
U9
Y8
AA7
W8
AB5

AB10

IRQFL

to JTAG page 3

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

Title

DCS DIMM and LVDS port

Size
A3

Document Number
8

Date:

2005.02.14

12:00

Rev
1.60
Sheet

of

14

2
R144

51R

C237

3V3

47n

LED5

R80
51R

3V3

R86
51R

1
2
3
4
V19
V20
W17
W18

100n

AB19
AA20
AA19
Y21
Y20
Y19
Y18
Y17
W22
W21
W20

1
2
3
4

8
7
6
5
RN11
4x22R

IC9

LXT971ALC

ERst
R103
3k3

3V3
3V3

C166

C164

100n

10n

R47

keep signals short!

R46
0R_Jmpr

EClkExt

R58
0R_Jmpr

51R

C236

R143

100n

590R

C245

C246

33p

33p

R148 R149
51R 51R

R140
100R

C171

R43
51R

10n

270p
C169
270p
R40
R41

R51

0R_Jmpr

R50

0R_Jmpr

8R06
8R06

16
15
14

1
2
3

13
12

4
5

11
10
9

6
7
8
R52

3V3

C158

C160

10n

100n

R44
0R_Jmpr

0R_Jmpr

10n

C177
not used
R59
0R_Jmpr
C181

3V3

R54
100R
Rx+
Tx-

Tx+

0R_Jmpr
R53

C172

Rx-

TR1
Halo TG110-S050N2

C170

TPFIN
TPFIP

Jumper R45...48
will set slew rate.

place jumper
close to crystal.

AD8351ARM

47n

R42
51R

R48
0R_Jmpr

0R_Jmpr

GND

22k1_1%

R89
10k

0R_Jmpr

R49
R45

R145

32
31
30 E_TCK
29 E_TMS
28 E_TDO
27 E_TDI
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

MDintn

Sleep
TRST
TCK
TMS
TDO
TDI
SD/TP
GND4
TPFIN
TPFIP
VCCA2
VCCA1
TPFON
TPFOP
GND3
RBIAS

ETDI
TP20

TxTx+
Rx+
Rx-

10
9
8
7
6

33p

ETDO
TP19

Rx_DV
GND8
VCCD
Rx_Clk
Rx_ER
Tx_ER
Tx_Clk
Tx_EN
TxD0
TxD1
TxD2
TxD3
GND9
COL
CRS
MDint

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

RxD0
RxD1
RxD2
RxD3
NC3
MDC
MDIO
GND7
VCCIO2
PwrDwn
LED_Cfg1
LED_Cfg2
LED_Cfg3
GND6
GND5
Pause

4x22R
8
7
6
5

ETCK
TP17

R146
100R

C233

TPFOP

keep signal short!

U21
V16
V17
V18

IO-118 IC1K IO-128

IO-124
IO-130
IO-119
IO-133
IO-117
IO-123
IO-116
IO-127
IO-115
IO-134
IO-121
IO-136
IO-126
IO-129
IO-132
IO-114
IO-122
IO-120
IO-131
IO-125
IO-135 Block 12 I/Os

10n

ETMS
TP18

RefClk_XI
XO
MDDIS
RST
TxSlew0
TxSlew1
GND1
VCCIO1
NC1
NC2
GND2
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4

T18
U18
U19
U20

EPXA1F484C3

C168

PwUp VOCM
RGP1 VPOS
InHi
OutHi
InLo
OutLo
RGP2
GND

C249

D7

D9

E_Pause

C167

4x22R

RN10
1
2
3
4

1
2
3
4
5

C232

TPFON

1 2
3 4
5 6
7 8
9 10
Header_05x2

33p

8
7
6
5

RN9

100n

TPFON
TPFOP
TPFIN
TPFIP

374R

D8

RN8

place resistors RN9..11 near output pins

C248

22uF

IC22

4x330R

1
2
3
4

C247

8
7
6
5

2k2

LED4

R142

3V3

R118

LED3

PwrDown
TP15

3V3

red_0603

red_0603

red_0603

CON2

C173

C174

1n/2kV

1n/2kV

Ethernet Connector

CON7

D10

1
3
5

2
4
6

Header_03x2

MMSZ5228BT1G
MMSZ5228BT1G
MMSZ5228BT1G
MMSZ5228BT1G

100n

XTAL1
1

2
25MHz

C175

C176

18p

18p

C161

C162

10n

100n

Shaded area shows

devices not used for
KIP/TRD

GND_ETH

Slewrate Table
3,0ns

R45

R46

X
X

3,4ns
3,9ns
4,4ns

R47

R48

X
X

Title

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

Block 09 I/Os Ethernet

Size
A3

Document Number
9

Date:

2005.12.21

12:35

Rev
1.64
Sheet

09

of

14

Place jumper R10 near to

crystal. Keep trace short.

shield signals AAin1 .. 4 with GND traces

AAin7
AAin8
D

To ROB connector page 8

R127

10k
VregTemp

AAin1
AAin2

Populate R122 if
AIN8 should measure
voltage regulator
temperature.

keep all analog signals as short as possible

8
7
6
5
RN40
4x10k
1
2
3
4

RN39
8
7
6
5
4x10k

CON11

Header_08x2x2mm

RN41
1
2
3
4

4x10k
RN35
5
6
7
8
RN36
5
6
7
8

1 2
3 4
5 6
7 8
9 10
1112
1314
1516

RN37
5
6
7
8

8
7
6
5

33p

100n

10n

C196
10n

C208

10n

C209

0R_Jmpr
IC13

10n

1
2
3
4
5
6
7
8
9
10
11
12
13
14

4x10k
4
3
2
1

4x10k
4
3
2
1

C210

C211

C212

C213

10n

10n

10n

10n

C216

C217

C218

10n

10n

10n

C214

C215

100n

2uF2

AIN7
AIN8
AVDD
AGND1
RefIn1n
RefIn1p
AIN1
AIN2
AIN3
AIN4
AIN5
AINCOM
RefIn2p
RefIn2n

XTALin
XTALout
DVDD
DGND
DIN
DOUT
RDY
CS
SCLK
RST
P1
AGND2
P2
AIN6

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CON12
2 2
1 1
Temp2

100n

470n

10uF

GND_ADC

4x47R
4
3
2
1

ADin
ADout
ARdyn
ACSn

4
3
2
1

RN34

Vout
Vin
GND

ASclk
ARstn
AP1
AP2

4x47R

3V3

10R

3V3
3

C197

C199

C200

C204

10n

100n

470n

10uF

R93

C201

C202

100n

470n
GND_ADC

C241
GND_ADC

10R

10n

C135

Please connect these analog ground to one point

near voltage reference ! Do only connect to GND
plane here with multiple vias!

R157
1k

Shaded area shows

devices not used for
KIP/DCS

100n

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

Title

DCS ADC

Size
A4

Document Number
10

Date:
5

10n

2
A

Q2
BC859C

Current source for additional

temperature sensor.

C195

5
6
7
8

AD7708BRU

C132
100n

C193

RN33
5
6
7
8

R94

AD1582ART

green_0603

C192

LED11

C189

Keep this
line short!

R156
10k

3V3

33p

Keep this
signals short!

IC21

R158
0R_Jmpr

32kHz

R10

4
3
2
1

4x10k

Populate R158 if AIN7

should measure
system temperature.

C207

ADMCLK
C194

1
2
3
4

XTAL2

C206

C68

2004.11.16
2

12:30

Rev
1.63
Sheet

10
1

of

14

Shaded area shows

devices not used for
KIP/DCS

J3
A1
A11
A16
A2
A21
A22
AA1
AA11
AA13
AA18
AA2
AA21
AA22
AB1
AB2
AB21
AB22
B1
B14
B2
B21
B22
C12
C16
C6
D20
D4
E1
E17
E3
F21
G14
H11
H16

1V8

CF2

CF3

C64

C17

C3

C1

1n

1n

1n

10uF

100n

10n

1n

C99

C19

C18

100n

10n

1n

CF4

CF5

CF6

C23

C22

C21

1n

1n

1n

100n

10n

1n

C104

C25

C24

100n

10n

1n

3V3
C29

C28

C27

100n

10n

1n

3V3

C63

C107

C31

C30

10uF

100n

10n

1n

VCC_CLKF

C60

1V8

2uF2

R119

C61

10R

100n

C34

C33

10n

1n

FPGA Clock Supply

Keep this traces as short as

possible short!

AB20
T16
V22

VCCint01
VCCint02
VCCint03
VCCint04
VCCint05
VCCint06
VCCint07
VCCint08
VCCint09
VCCint10
VCCint11
VCCint12
VCCint13
VCCint14
VCCint15
VCCint16
VCCint17
VCCint18
VCCint19
VCCint20
VCCint21
VCCint22
VCCint23
VCCint24

3V3

VCCIO2-01
VCCIO2-02
VCCIO2-03
VCCIO2-04
VCCIO2-05
VCCIO2-06
VCCIO2-07
VCCIO2-08
VCCIO2-09
VCCIO2-10
VCCIO2-11
VCCIO2-12
VCCIO2-13
VCCIO2-14
VCCIO2-15
VCCIO2-16
VCCIO2-17
VCCIO2-18
VCCIO2-19
VCCIO2-20

VCCIO12-01
VCCIO12-02
VCCIO12-03

K22
M15
T22

VCCIO13-01
VCCIO13-02
VCCIO13-03

R18
N17
E5
E4

VCC-CLK2
VCC-CLK4
VCC-CLK5
VCC-CLK6

T19

VCC-CKout2

T17

GND-CKout2

R17
R19
N19
N18
D6
D5
F5
F4

GND-CLK21
GND-CLK22
GND-CLK41
GND-CLK42
GND-CLK51
GND-CLK52
GND-CLK61
GND-CLK62

IC1A

VCCIO3-01
VCCIO3-02

EPXA1F484C3

VCCIO6-01
VCCIO6-02
VCCIO6-03
VCCIO6-04

A14
A18
A20
C18
C22
D12
D15
E14
E19
F15
F22
G12
G17
G19
H13
H14
H21
J15
J18
J22
K1
L8
A13
A3
C1
F7

VCCIO7-01
VCCIO7-02

G1
J7

VCCIO9-01
VCCIO9-02
VCCIO9-03

M1
M8
T1

VCCIO10-01
VCCIO10-02
VCCIO10-03
VCCIO10-04
VCCIO10-05
VCCIO10-06
VCCIO11-01
VCCIO11-02
VCCIO11-03

AB11
AB3
AB7
R11
U5
Y1
AB13
AB18
R12

C36

C37

C108

C65

1n

10n

100n

10uF

C39

C40

C41

1n

10n

100n

C42

C43

C111

1n

10n

100n

C45

C46

C47

1n

10n

100n

C48

C49

C113

1n

10n

100n

C51

C52

C53

1n

10n

100n

C54

C55

C115

1n

10n

100n

C57

C58

C59

C67

1n

10n

100n

10uF

J10
J12
J14
J19
J21
J8
K11
K13
K16
K2
K8
K9
L10
L12
L14
M11
M13
M2
M9
N10
N12
N14
N15
N8
P11
P13
P15
P9
R14
R8
T2
T21
V21
W19
W4
W6

100n

C35

H12
H15
H8
J11
J13
J9
K10
K12
K14
L11
L13
L9
M10
M12
M14
N11
N13
N9
P10
P12
P14
P8
R15
R9

GND-36
GND-37
GND-38
GND-39
GND-40
GND-41
GND-42
GND-43
GND-44
GND-45
GND-46
GND-47
GND-48
GND-49
GND-50
GND-51
GND-52
GND-53
GND-54
GND-55
GND-56
GND-57
GND-58
GND-59
GND-60
GND-61
GND-62
GND-63
GND-64
GND-65
GND-66
GND-67
GND-68
GND-69
GND-70
GND-71

CF1

GND-01
GND-02
GND-03
GND-04
GND-05
GND-06
GND-07
GND-08
GND-09
GND-10
GND-11
GND-12
GND-13
GND-14
GND-15
GND-16
GND-17
GND-18
GND-19
GND-20
GND-21
GND-22
GND-23
GND-24
GND-25
GND-26
GND-27
GND-28
GND-29
GND-30
GND-31
GND-32
GND-33
GND-34
GND-35

1V8

3V3
R120

10R

GND

PLL Supply
VCC_PLLF

C74

C73

C72

C71

C70

470n

2uF2

100n

10n

1n

GND_PLLF

GND_PLLF

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

Title

FPGA Power Connections

Size
A3

Document Number
11

Date:

2003.12.19 14:30

Rev
1.60
Sheet

11

of

14

Routing Hints for the DCS Board

Place 10nF and 100nF capacitors as close as possible

to the devices. Place power vias as close as possible to
the related decoupling capacitors not to the related
device. This may not allways work with BGAs but should
work with all non BGA packages. See picture.

via*

via*

device
wrong

via*

via*

okay

*via to supply or GND planes

Grounding scheme for PLL, TTCrx and 120MHz LVDS driver

PLL 3V3
Vreg

QOsc
40MHz
MUX1

PLL

LVDS
driver

PLL_GND

PLL_GND
R124
B

Board_GND
Optical Link
Receiver

TTCrx

Wednesday 2003.12.17
Title

Editor : Dirk Gottschalk

DCS Board Routing Hints

Size
A4

Document Number
12

Date:

2003.12.17

10:10

13:30

Rev
1.60
Sheet

12

of

14

PLL Configuration Table for TPC and TRD

TRD

TPC

default
frequency

120 MHz

40 MHz

R68

no device

10k

R99

0R_Jmpr

no device

R100

no device

no device

R105

no device

no device
no device

R107

0R_Jmpr

R108

no device

10k

R109

0R_Jmpr

10k

R110

0R_Jmpr

10k

RN48

no device

4x0R_Jmpr

Editor : Dirk Gottschalk

Company : KIP Uni-Heidelberg / Lindenstruth

Title

PLL Clock Configuration

Size
A4

Document Number
13

Date:

2005.05.02

10:00

Rev
1.61
Sheet

13

of

14

J3
D

GND_PW

J8

GND_ADC

GND_TPLL

GND_ADC

B2S

GND_PLL

B2S

J2

GND_PLLF

GND_ETH

GND_PLLF

B2S
J4

GND_ETH

B2S
C

J5

GND_TPLL

GND

GND

GND

GND

GND_TPLL

B2S
J6

GND

B2S
J7

GND

B2S
J1

GND

B2S
J9

GND

B2S
Company : KIP Uni-Heidelberg / Lindenstruth

Title
Size
A
Date:
5

Editor : Dirk Gottschalk

DCS Ground Scheme

Document Number
14
2005.05.02
2

Rev
1.60
Sheet

14

of
1

14