NR

Code No. A0611

JAWAHARLAL NEHRU TECHNOLOGY UNIVERSITY, HYDERABAD
M.Tech. I Semester Regular Examinations, March – 2009
LOW POWER VLSI DESIGN
(Common to Digital Systems & Computer Electronics and Wireless and Mobile
Communications)
Time: 3 hours Max. Marks.60
Answer any Five questions
All questions carry equal marks
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1.a) What are the implications of Device Technology on IC design? Explain.
b) Discuss about the various problems associated with low voltage VLSI circuit
design? Explain.

2.a) Draw the structure of optimized twin-well BiCMOS structure with self aligned
buried layers and explain the same.
b) How graded drain structure can be produced? What are the advantages of the
same?

3.a) Draw the structure of Bipolar with double poly silicon emitter and explain the
significance of the same.
b) Explain about LOCOS Isolation method bringing out its significance.

4. Draw the structure of poly silicon Emitter high performance BICMOS structure
and explain the same. Give the process flow for the same.

5.a) Explain about the features of high performance LVLP; CMOST device.
b) Give the process sequence of SOI lateral BJT and give the typical values of
Device parameters.

6.a) Explain about SPICE level 3 model of MOSFET, with necessary equations.
b) Explain about EKV model and capacitance models of MOSFETS.

7.a) Derive the Rigorous expression for turn-off or Rise time; considering body effect
for a CMOS Inverter Logic Gate.
b) Draw the circuits and explain about the Two-types of Feed back type BICMOS
Digital circuits.

8. Write notes on any two:

a) ESD free BICMOS circuit
b) Low power Flip-Flops
c) Negative edge Triggered C2 MOS FF.

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