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  • Quantization Noise Suppression in Fractional-N Plls Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider

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    Vij Ay
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    This document proposes a novel glitch-free phase switching multi-modulus frequency divider (PS-MMFD) to reduce quantization noise in fractional-N phase-locked loops. The PS-MMFD utilizes a divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5, suppressing quantization noise by an additional 6 dB compared to existing approaches. The proposed PS-MMFD is more robust, can operate at higher frequencies, and consumes less power than other dividers used for quantization noise suppression. Experimental results from a fractional-N PLL using the proposed technique demonstrate its effectiveness.

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    VTVL25VTVL25

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    VTVL25

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    This document proposes a novel glitch-free phase switching multi-modulus frequency divider (PS-MMFD) to reduce quantization noise in fractional-N phase-locked loops. The PS-MMFD utilizes a divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5, suppressing quantization noise by an additional 6 dB compared to existing approaches. The proposed PS-MMFD is more robust, can operate at higher frequencies, and consumes less power than other dividers used for quantization noise suppression. Experimental results from a fractional-N PLL using the proposed technique demonstrate its effectiveness.

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    15 views3 pages

    Quantization Noise Suppression in Fractional-N Plls Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider

    Uploaded by

    Vij Ay
    This document proposes a novel glitch-free phase switching multi-modulus frequency divider (PS-MMFD) to reduce quantization noise in fractional-N phase-locked loops. The PS-MMFD utilizes a divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5, suppressing quantization noise by an additional 6 dB compared to existing approaches. The proposed PS-MMFD is more robust, can operate at higher frequencies, and consumes less power than other dividers used for quantization noise suppression. Experimental results from a fractional-N PLL using the proposed technique demonstrate its effectiveness.

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    © All Rights Reserved
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    of 3

    QUANTIZATION NOISE SUPPRESSION IN FRACTIONAL-N

    PLLs UTILIZING GLITCH-FREE PHASE SWITCHING


    MULTI-MODULUS FREQUENCY DIVIDER
    ABSTRACT:
    A novel programmable frequency divider for quantization noise (QN) suppression in
    fractional-N phase-locked loops (PLLs) is presented in this paper. The proposed phase switching
    multi-modulus frequency divider (PS-MMFD) utilizes a novel glitch-free phase switching (PS)
    divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and its QN induced by
    modulation is thus suppressed by additional 6 dB. Compared with other frequency dividers used
    for QN suppression, the proposed glitch-free PS-MMFD is more robust, can operate at higher
    input frequency and consumes less power. Detailed analysis and implementation of the proposed
    glitch-free PS-MMFD is demonstrated, followed by experimental results from a fully integrated
    fractional-N PLL utilizing the proposed QN suppression technique.

    EXISTING SYSTEM:
    In existing model allows straightforward noise and dynamic analyses of - fractional-N
    frequency synthesizers and other PLL applications in which the divide value is varied in time.
    Based on the derived model, a general parameterization is presented that further simplifies noise
    calculations.

    EXISTING SYSTEM ALGORITHM:


    Pseudo continuous Approximation

    EXISTING SYSTEM DRAWBACKS:

    Area will be high


    Consume more power

    PROPOSED SYSTEM BLOCK DIAGRAM:


    The overall architecture of the proposed Phase Switching multi-modulus frequency
    divide (PS-MMFD) is shown in Fig. 1.

    Fig. 1. Proposed glitch-free PS-MMFD architecture.

    PROPOSED SYSTEM TECHNIQUE (ALGORITHM):


    the division range extension logic, the division ratio of the proposed PS-MMFD scan is
    expressed as follows:
    9

    N = 25.

    pi
    i=6

    +28.p9+27.p8++21.p2-20.p1-2-1.p0

    PROPOSED SYSTEM ADVANTAGES:

    More robust
    Can operate at higher input frequency
    Consumes less power

    SOFTWARE REQUIREMENTS:

    ModelSim 6.4c
    Xilinx 13.2
    Matlab 7.14(R2012a)

    HARDWARE REQUIREMENT:

    FPGA Spartan 3(xc3s400 pq 208)

    REAL TIME EXAMPLE

    radio receivers,
    mobile telephones,
    satellite receivers,
    GPS systems

    FUTURE ENHANCEMENT
    In our future enhancement we are using Matlab coding for finding Phase noise profile
    with and without QN suppression.

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