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SEQUENCE DETECTOR

Advanced Digital System Design ASSIGNMENT (CAT 2)

Given Question

Design a pattern detector to detect 1001 and 010 in Overlapping manner.

Irfanuddin

130051601031 | ECE A | VI Semester

Program:

`timescale 1ns / 1ps


module seqdec(datain, reset, clk, y);
output reg y;
input datain, clk, reset;
reg [1:0] cur_state, next_state;
parameter S0 = 3'b000,
S1 = 3'b001,
S2 = 3'b010,
S3 = 3'b011,
S4 = 3'b100,
S5 = 3'b101;
always @(cur_state or datain)
begin
case (cur_state)
S0: if (datain == 1'b1)
begin
next_state = S2;
y=1'b0;
end
else
begin
next_state = S1;
y=1'b0;
end
S1: if (datain == 1'b0)
begin
next_state = cur_state;
y=1'b0;
end
else
begin
next_state = S3;
y=1'b0;
end
S2: if (datain == 1'b1)
begin
next_state = cur_state;
y=1'b0;
end
else
begin
next_state = S4;
y=1'b0;
end
S3: if (datain == 1'b0)
begin
next_state = S1;
y=1'b1;
end
else
begin
next_state = S2;
y=1'b1;

end
S4: if (datain == 1'b0)
begin
next_state = S5;
y=1'b0;
end
else
begin
next_state = S3;
y=1'b0;
end
S5: if (datain == 1'b0)
begin
next_state = S1;
y=1'b0;
end
else
begin
next_state = S2;
y=1'b1;
end
default: next_state = S0;
endcase
end
always@(posedge clk)
begin
if (reset)
cur_state <= S0;
else
cur_state <= next_state;
end
endmodule

Test bench
Program:
module tb;
reg datain;
reg reset;
reg clk;
// Outputs
wire y;
seqdec uut (.datain(datain),
.reset(reset),
.clk(clk),
.y(y));
initial begin
// Initialize Inputs
datain = 0;
reset = 0;
clk = 0;

always

end

#10
#10
#10
#10
#10
#10
#10
#10
#10
#10
#10

datain=1;
datain=0;
datain=1;
datain=0;
datain=0;
datain=1;
datain=0;
datain=0;
datain=1;
datain=0;
datain=1;

#5 clk=~clk;
initial
#150 $finish;
endmodule

Simulation
Waveform

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