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Irfanuddin
Program:
end
S4: if (datain == 1'b0)
begin
next_state = S5;
y=1'b0;
end
else
begin
next_state = S3;
y=1'b0;
end
S5: if (datain == 1'b0)
begin
next_state = S1;
y=1'b0;
end
else
begin
next_state = S2;
y=1'b1;
end
default: next_state = S0;
endcase
end
always@(posedge clk)
begin
if (reset)
cur_state <= S0;
else
cur_state <= next_state;
end
endmodule
Test bench
Program:
module tb;
reg datain;
reg reset;
reg clk;
// Outputs
wire y;
seqdec uut (.datain(datain),
.reset(reset),
.clk(clk),
.y(y));
initial begin
// Initialize Inputs
datain = 0;
reset = 0;
clk = 0;
always
end
#10
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#10
datain=1;
datain=0;
datain=1;
datain=0;
datain=0;
datain=1;
datain=0;
datain=0;
datain=1;
datain=0;
datain=1;
#5 clk=~clk;
initial
#150 $finish;
endmodule
Simulation
Waveform