Seminar Report 09 System-on-Chip

1. INTRODUCTION
Today's mobile phones have more processing power than typical desktop computers of
the last millennium. Even the Portable Media Players (PMPs) have more sophisticated
processors than the revolutionary Pentium processor launched 15 years back. On top of that,
mobile phones, PMPs and other handheld devices are getting smaller and thinner with
increasing battery life.

So, what makes these new generation handheld devices tick? Ticking at 200MHz or
more, these devices are powered by a small silicon chip -the size of about 10mm x 10mm,
which contains almost all components of a powerful computer including processor core,
memory controller, interrupt controller, timer, multimedia co-processors or digital signal
processor (DSP) etc. This silicon chip, along with the software running on it, is called a
System-on-Chip or SoC.

We use a cutting-edge technology for development of electronics and devices based on

Systems-on-Chip (SoC) from the leading semiconductor manufacturers such as Intel, Texas
Instruments, Atmel, Sharp, and NetSilicon. This breakthrough technology allows creating
competitive products with rich functionality while saving your time-to-market and expenses.
Electronic device development with a new functional level based on MCU or DSP require
significant amount of resources and a highly qualified team of hardware engineers, often
resulting in failing to fit into project time frame.

The SoC has been talked about, marketed, and accepted in the new millennium,
especially for embedded applications. More recently, with announcements of high-performance
SoC designs such as the Cell chip, and use of these chips in consumer products including the
Sony PlayStation 3 (PS3) and Microsoft XBox, it has become clear that SoC designs will
have broad impact. What is really exciting about SoC architecture is that supercomputing and
embedded computing may become the cutting edge of computer architecture. For
supercomputing this is nothing new, but embedded systems have often followed rather than led
architecture.

Dept. of Computer Science & Engg. 1 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

What is a SoC?
System-on-chip is an integration of almost all components of a computer into a single
integrated circuit (chip). The SoC consists of both the hardware (HW) components of the
computer as well as the software (SW) that controls the microprocessor and peripherals.

SoCs include not only the brains (e.g. microprocessor) but also all required ancillary
electronics, such as switches, comparators, resistors, capacitors, timing elements, and digital
logic. While having the required interfaces (for example Ethernet, USB, LCD) onboard and
almost the same functionality as a single board industrial computer (SBC), the embedded
System-on-Chip (SoC) module provides additional advantages such as minimized footprint,
operation in extended temperature range, minimized power consumption suitable for use in
mobile environments.

Figure 1: AMD Geode is a x86 compatible system-on-a-chip

Structure of SoC

A typical SoC consists of:

One microcontroller, one microprocessor or DSP core(s). Some SOCs called
multiprocessor System-on-Chip (MPSoC) include more than one processor core.
Memory blocks including a selection of ROM, RAM, EEPROM and Flash.
Timing sources including oscillators and phase-locked loops.
Peripherals including counter-timers, real-time timers and power-on reset generators.

Dept. of Computer Science & Engg. 2 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

External interfaces including industry standards such as USB, FireWire, Ethernet,

USART, SPI.
Analog interfaces including ADCs and DACs.
Voltage regulators and power management circuits.

HARDWARE SOFTWARE
Processor such as ARM core. The operating system - ranges from a
System bus-connecting the processor to simple RTOS like eCOS or uITRON to
other components- e.g. AMBA Bus. high level OS such as Windows CE or
Memory-some types of ROM, Embedded Linux.
EEPROM or Flash. The operating system layer, generally
Timers-oscillators, PLLs, real time termed as the Board Support Package
clocks etc. (BSP) abstracts the actual SoC HW.

LCD controllers or VGA Controller, Device drivers - which control the

with optional Touch Screen interface. peripherals.

External Interfaces for USB, Firewire, Middleware components - such as

etc. & for flash memory- Compact multimedia engines, protocol stacks
Flash, SD Card, Memory Stick etc. etc.

Power management circuits, Interrupt Application software - the UI, the

Controller and Memory Interface. media players, phone applications,
browsers etc.

Table 1: Components of SoC

These blocks are connected by either a proprietary or industry-standard bus such as the
AMBA bus from ARM. DMA controllers route data directly between external interfaces and
memory, by-passing the processor core and thereby increasing the data throughput of the SoC.

Dept. of Computer Science & Engg. 3 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

2. SoC ARCHITECTURE

The generic SoC architecture consists of the processor, system bus, timers, memory,
interrupt controller and power management circuits. The other peripherals such as LCD
controllers, USB interface; Flash memory interfaces etc. are optional and depend on the target
application of the SoC.

Figure 2: Typical SoC Architecture

SoCs for multimedia platforms such as mobile phones or PMPs, require a large amount of
audio and video processing. There are two schools of thoughts in the industry to achieve better
multimedia experience for the user: Dedicated DSP and Dedicated multimedia blocks.

Some SoC designers use a dedicated DSP along with the main processor. The Audio and
Video processing is shared between the main processor and the DSP. E.g. the main processor
may be decoding audio, while the video is decoded on the DSP. This approach allows for more
generic application of the SoC and also allows scalability in the future as new codecs are

Dept. of Computer Science & Engg. 4 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

released in the market. But this approach may increase the size of the chip and also increase the
power utilization.

Figure 3: Generic Software Stack for SoC

Other designers prefer using dedicated blocks for processing popular Audio and Video
encoding formats. E.g. there can be dedicated hardware blocks for MP3 decoding, H.264
decoding, MPEG4 encoding etc. This approach may be more optimized in terms of size and
power, but application and scalability may be limited.

The approach used in a particular SoC will usually depend on the application, market
requirements and other constraints like cost and power.

Example SoC: Intel EP80579

The Intel EP80579 Integrated Processor with Intel QuickAssist Technology development
kit enables customers to create a new generation of embedded, storage, security and

Dept. of Computer Science & Engg. 5 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

communications solutions. It utilizes a breakthrough system-on-a-chip (SOC) processor product

line to deliver excellent performance-per-watt for small form factor designs. The fully pin-
compatible SOC product line includes the Intel EP80579 Integrated Processor and the Intel
EP80579 Integrated Processor with Intel QuickAssist Technology.

Figure 4: Intel EP80579

This development kit is a highly configurable platform that enables evaluation of Intel
QuickAssist Technology. It can also be used to evaluate general embedded applications that don't
require the effective performance boost of integrated acceleration.

This SOC product line delivers a significant leap in architectural design, providing an
outstanding combination of performance power efficiency, footprint savings and cost effectiveness
compared to discrete, multi-chip solutions. The single-chip design includes an Intel architecture
complex based on the Intel Pentium M processor, integrated memory controller hub, integrated
I/O controller hub, and a wide range of I/O for flexible design options. It features PCI Express*,
Gigabit Ethernet, High Speed Serial (HSS) ports for TDM or analog voice connectivity, security
accelerators for bulk encryption, hashing and public/private key generation, and data path
acceleration. Utilizing the Intel software supporting Intel QuickAssist Technology, users can
effectively boost performance by offloading key security or communications functionality and
conserving valuable CPU cycles.

Dept. of Computer Science & Engg. 6 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

3. SYSTEM ON CHIP CORES

One solution to the design productivity gap is to make ASIC designs more standardized
by reusing segments of previously manufactured chips. These segments are known as blocks,
macros, cores or cells.

The blocks can either be developed in-house or licensed from an IP company. These
Cores are the basic building blocks for System on Chip.

There are three different form of blocks or macros of System on Chip cores which are
described below:

Soft Macro
Reusable synthesizable RTL or netlist of generic library elements.
User of the core is responsible for the implementation and layout.

Firm Macro
Structurally and topologically optimized for performance and area through floor
planning and placement
Exist as synthesized code or as a netlist of generic library elements

Hard Macro
Reusable blocks optimized for performance, power, size and mapped to a
specific process technology
Exist as fully placed and routed netlist and as a fixed layout such as in GDSII
format.

Dept. of Computer Science & Engg. 7 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Figure 5: Graph showing variations in different cores

Locating the required cores and associated contract discussions can be a lengthy process
Identification of IP vendors and Evaluation criteria
Comparative evaluation exercise
Choice of core
Contract negotiations
Reuse restrictions
Costs: license, royalty, tool costs
Core integration, simulation and verification

Solution is Design Re-use

To overcome complexity and verification issues by designing Intellectual Property (IP)
to be re-usable .This is done on such a scale that a new industry has been developed. The
Design activity is split into two groups:
IP Authors producers.
IP Integrators consumers.
IP Authors produce fully verified IP libraries and thus making overall verification task
more manageable.
IP Integrators select, evaluate, and integrate IP from multiple vendors. IP integrated onto
Integration Platform designed with specific application in mind.

Dept. of Computer Science & Engg. 8 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

4. SYSTEM ON CHIP INTERCONNECTION

In SoC interconnection design reuse is facilitated if standard internal connection buses

are used. All cores connect to the bus via a standard interface and any-to-any connections easy
but it is seen that not all connections are necessary. There must be a global clocking scheme
and consideration for Power consumption must be kept in mind while considering the design of
a SoC.

Standardization is being addressed by the Virtual Socket Interface Alliance (VSIA) for
the best production of these chips interconnection. SOC [Systems-On-Chip] buses are not real
physical buses. SOC buses reside within an FPGA and are used to interconnect an IP core to
the surrounding interface logic. A SOC bus provides a way to define an IP core with I/O and
allow an interconnection method to the core. With out a predefined bus, the interface would
need to be redesigned for each IP core used. SOC may also be seen as SOPCs: systems on re-
programmable chips, or CSoC: configurable SoC, or NoC; Network-on-Chip.

IP: "Intellectual Property". IP cores are pre-designed modules used in FPGAs, PLDs, or
ASICs. The IP buses are used to interconnect the modules [or Blocks] within the core and or
user defined logic within the gate-array. These designs are also called Systems-On-Chip [SOC].

I/O interconnections

Since SoCs include processing, memory, and I/O on-chip by definition, and most often
include multiple processors, the I/O interconnection on-chip is fundamental to the design.
Figure 6 provides an overview (taxonomy) of the many different schemes for interconnecting
processing elements, memory, and I/O devices for any system, including SoCs. Each
interconnection architecture has advantages and disadvantages based upon cost, complexity of
implementation, complexity of usage by firmware and software, and performance. Since an
SoC typically includes all resources needed on a single chip and often includes multiple
processor cores (the IBM Cell architecture works this way, for instance), the interconnection
scheme is critical to SoC design.

Dept. of Computer Science & Engg. 9 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Figure 6: Interconnection network taxonomy

Static interconnection topologies
Point-to-point: One-to-one connection of nodes, N nodes, N-1 connections, N-1 hops to
any node
Ring: One-to-one connection and first to last, N nodes, N-1 connections, N/2 hops to any
node worst case
Hub: One central node connected to N-1 nodes, N nodes, N-1 connections, two hops
from any node to another
Tree: One root node connected to M sub-nodes for N nodes, N-1 connections, log(N) or
fewer hops to any node
Square mesh: Each node connected to four nearest neighbors, N nodes, 2*N - 2*square-
root(N) connections, square-root (N) hops worst case
Fully connected: Each node connected to all others, N nodes, N(N-1) connections, one
hop all cases

Dept. of Computer Science & Engg. 10 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Dynamic interconnection networks

Bus: Arbitrated transactions for read and write (split transaction read, posted write
optimizations)
Blocking switch: Some active circuits prevent others from becoming active
Non-blocking switch: All circuits may be active simultaneously

For SoC interconnection we make use of the following buses for the interconnection
network:

AMBA (Advanced Microcontroller Bus Architecture) : A collection of buses from

ARM for satisfying a range of different criteria.

APB (Advanced Peripheral Bus): Simple strobed-access bus with minimal interface
complexity. Suitable for hosting peripherals.

ASB (Advanced System Bus): A multimaster synchronous system bus. This bus has
high performance with pipelined operation and multiple bus masters.

AHB (Advanced High Performance Bus): a high- throughput synchronous system

backbone. Burst transfers and split transactions.

The objective of the AMBA specification is to be technology independent, enhance

design reusability using IP cores, encourage modular system design to improve processor
independence and minimize silicon infrastructure. The timing aspects and the voltage
levels on the bus are not dictated by the specifications.

Dept. of Computer Science & Engg. 11 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

5. SoC DESIGN FLOW

A SoC consists of both the hardware described above, and the software that controls the
microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for
an SoC aims to develop this hardware and software in parallel.

Most SoCs are developed from pre-qualified hardware blocks for the hardware elements
described above, together with the software drivers that control their operation. Of particular
importance are the protocol stacks that drive industry-standard interfaces like USB. The
hardware blocks are put together using CAD tools; the software modules are integrated using a
software development environment.

A key step in the design flow is emulation: the hardware is mapped onto an emulation
platform based on a field programmable gate array (FPGA) that mimics the behavior of the
SoC, and the software modules are loaded into the memory of the emulation platform. Once
programmed, the emulation platform enables the hardware and software of the SoC to be tested
and debugged at close to its full operational speed. After emulation the hardware of the SoC
follows the place and route phase of the design of an integrated circuit before it is fabricated.

Chips are verified for logical correctness before being sent to foundry. This process is called
functional verification, and it accounts for a significant portion of the time and energy
expended in the chip design life cycle (although the often quoted figure of 70% is probably an
exaggeration).

Verilog and VHDL are typical hardware description languages used for verification. With
the growing complexity of chips, hardware verification languages like SystemVerilog,
SystemC, e, and OpenVera are also being used. Bugs found in the verification stage are
reported to the designer.

Dept. of Computer Science & Engg. 12 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Figure 5. System-on-a-Chip Design Flow

Complete description for design of SoC

The design of any SoC starts with the requirement specification and architecture
exploration. The design team identifies all the processing blocks along with their
interconnections. A lot of time is devoted to the hardware and software partitioning. This is
essential for optimization of the performance of the SoC as well as the costs involved. E.g. if
the SoC requires processing of 3D Graphics - the options for implementing the required
processing logic or algorithm are as follows:

Dept. of Computer Science & Engg. 13 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Use a collection of interconnected logic gates (AND/NAND/NOR etc.) as a HW block

Implementation as a software library running on the main processor

Once the partitioning is finalized, the HW team starts working on the implementation of
the architecture platform. It consists of the main processor core and the system buses. The main
processor core is usually available as a component from core vendors such as ARM or Ten
silica. The system bus can be either an industry standard architecture such as AMBA, or can be
designed specifically be the HW team. Next is design and implementation of HW blocks called
HW IPs (intellectual property) using a hardware description language such as VHDL or
Verilog. Examples of HW blocks can be USB controller, memory controller, LCD controller
etc. depending on the SoC requirements. Not all HW blocks are designed and implemented by
the HW team; some HW blocks are purchased or licensed from 3rd parties who sell these as
components. These may be commonly used blocks such as serial bus controllers, memory
controller, interrupt controllers or can be very specialized blocks such as multimedia codecs,
3D accelerators etc.

Next comes the integration of the HW blocks with the architecture platform. This
involves creating interconnection or bridges for the processor to communicate and control each
HW block. The whole system is then tested using various verification techniques such as
functional simulation.

The HW system is essentially a collection of logic gates and their interconnections. To

further verify the functionality of the HW system, the HW team uses a field-programmable gate
array (FPGA). An FPGA is a silicon chip which consists of programmable logic (gates) and
programmable interconnects. The entire HW system can be realized using one or more FPGAs.
The FPGAs are set on a PCB which has similar external interfaces as the final SoC.
Since the FPGAs are reprogrammable, the HW team can test and modify their implementation
to eliminate bugs. The FPGA board with the HW system is also used by the software team to
co-simulate the entire system (SW+HW) and eliminate bugs in both HW blocks and software
programs.

Dept. of Computer Science & Engg. 14 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

The HW system implementation is done using Software tools on development

workstations running Windows or Linux. These software tools are called the Electronic Design
Automation (EDA) tools available from companies such as Cadence, Synopsis and Mentor
Graphics.

While the HW team is busy creating the HW System, the software team can start
developing the SW system. They create an environment on a development PC (running
Windows or Linux) simulating the SoC. There are many tools available to create such
environments. Mostly the tools are specific to the Operating System chosen to run on the final
SoC. E.g. the Windows CE tools from Microsoft provide emulated execution environments on
the PC itself for developing software. Next comes the design and implementation of
components such as multimedia codecs, application software etc. these components are tested
on the simulation environment on the PC.

Once the FPGA board is ready with the HW system, the SW team can start porting the
operating system on to the FPGA board. The device driver development is also done at this
stage.

Once the HW and SW system on the FPGA board is stabilized and bug fixing is complete,
the HW team proceeds with the physical design of the SoC. This involves developing the
layout of the gates for the final realization on Silicon.

This is a complex process usually termed as 'backend process'. The HW design is then sent
to the Semiconductor Fabrication Plant (FAB) for making of the final chip (ICs) on silicon.
This process is called 'tape-out'. The first sets of ICs are called the engineering sample and are
made available to the HW and SW team for verification.

The verification process involves finding bugs in the IC and finding workarounds to fix
them since the HW cannot be modified easily, most of the bugs are fixed using software
patches. If there are too many bugs, or some bugs affect the functionality of the SoC, then the
HW design is fixed and a second tape-out may be required. This is termed as a re-spin and can

Dept. of Computer Science & Engg. 15 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

be expensive. When the engineering samples are found to be good enough to hit the market, a
mass production is ordered to the FAB and the ICs are shipped to the customer with all
associated software. The customers are often the original equipment manufacturers (OEM) who
make the final product using the SoC and other components.

Intel, Samsung, ST Microelectronics, Texas Instruments and Qualcomm are some

Semiconductor companies, which make the SoCs and ship them to OEMs such as Nokia,
Apple, HP, HTC and Motorola. E.g. the new HTC Touch Diamond Smartphone is powered by
a Qualcomm SoC (MSM7201A) which has an ARM 1136 CPU Core running at 528MHz.

Figure 6: SoC design time

With increasing Complexity of ICs and decreasing geometry, IC Vendor steps of

Placement, Layout and Fabrication are unlikely to be greatly reduced. In fact there is a greater
risk that Timing Convergence steps will involve more iteration and there is a need to reduce
time before Vendor Steps and to consider Layout issues up-front.

Dept. of Computer Science & Engg. 16 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Fabrication

SoCs can be fabricated by several technologies, including:

Full custom
Standard cell
FPGA

SoC designs usually consume less power and have a lower cost and higher reliability than the
multi-chip systems that they replace. And with fewer packages in the system, assembly costs
are reduced as well.

However, like most VLSI designs, the total cost is higher for one large chip than for the same
functionality distributed over several smaller chips, because of lower yields and higher NRE
costs.

Dept. of Computer Science & Engg. 17 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

6. SoC DESIGN CONSIDERATIONS

The focus of all SoCs designers is to deliver maximum performance at the lowest cost and
lowest power consumption. Many factors contribute to SoCs characteristics:

Process Technology:
The SoCs are manufactured using a Silicon fabrication technology called
Complementary metal oxide semiconductor (CMOS). Logic gates are created on a Silicon
wafer using the CMOS process technology. The gates are then interconnected to realize the
HW system of the SoC. The CMOS process technology has been evolving over the years
with the size of the gate reducing considerably. Smaller size of each gate means a closer
packing of the gates on the silicon chip. The packing of gates which is roughly the distance
between them is measured in nanometers (nm). A smaller size indicates a more advance
process. The commonly used process these days ranges from 180 nm to 90 nm. Some FABs
also have capability of 65 nm and 45 nm.
The advancement in the process technology has been a key contributor of the
evolution of the SoC. More and more gates, which in turn mean more and more
functionality, can be put in a single SoC thus reducing the number of ICs inside a product.
This has led to thinner, smaller and more power efficient handheld products.
The CMOS process technology is also optimized for either higher speed or lower
power consumption. The SoC designers can select the process based on the requirements of
the target SoC and its applications.

Die Size:
This is the physical surface area of the silicon used to make a single IC. Die size is
measured in mm2. The importance of die size is that it translated directly to cost. Smaller die
size of a chip means that more of them can be made from a single wafer, thus reducing cost.
Die size depends on the number of gates required to realize a particular HW System for a
SoC.
SoC designers try to optimize the die size to reduce cost. They try to optimize the
algorithms used to realize a particular functionality and also optimize the gates required to

Dept. of Computer Science & Engg. 18 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

implement the algorithm. Another target is to reuse a particular HW block for multiple
functionalities to reduce die size. SoC designs frequently require performance vs. die size
decisions.

Power:
Most handheld devices run on battery power and power consumption of a SoC
becomes a prime consideration for OEMs as this is an important buying consideration for
users.

Power management:
The process of reducing power consumption involves controlling standby power,
reducing leakage currents, switching off HW blocks which are not in use at the moment,
slowing down the main processor during low usage periods etc.
Example in a mobile phone, the USB controller can be switched off when the
phone is not connected to a PC, the LCD can be switched off after some time of inactivity.
Also, the main processor clock can be slowed down to bare minimum when the phone is not
in use.
Power management in SoCs for handheld devices is one of the most complex tasks
faced by the SoC designers.

Hardware Software Partitioning:

One of the initial discussions during the design of a SoC is on the question of what
goes into HW and what is implemented in SW. The factors involved are

1. HW is faster than SW
2. A large amount of parallel processing can be done in HW
3. There is limited flexibility in HW, functionality cannot be modified
4. Any bug found in HW may require an expensive re-spin

Dept. of Computer Science & Engg. 19 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Since point 1, 2, contradict with 3, 4, the decisions of partitioning are complex and
require a lot of deliberation.

Operating System:
The design of the SoC also depends on the type of operating system that will be
running on the processor. This is usually dictated by the application of the SoC and the
choice of the target customers.
If the SoC is targeted to run real time operating systems such as VxWorks,
uITRON etc. then some blocks such as Memory Management Unit (MMU) may not be
required. On the other hand, if the target OS is Windows CE or Embedded Linux, then
MMU becomes essential along with certain amount of Cache memory.

The above factors are a subset of all the factors that affect the design of a SoC.

Dept. of Computer Science & Engg. 20 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

7. ADVANTAGES AND DISADVANTAGES

The Benefits

There are several benefits in integrating a large digital system into a single integrated circuit.
These include
Lower cost per gate.
Lower power consumption.
Faster circuit operation.
More reliable implementation.
Smaller physical size.
Greater design security.
Easy-to-incorporate modern protocols and interfaces such as USB, Wi-
Fi/IEEE802.11, and Bluetooth into embedded systems.
Porting PC software on embedded systems.
Overall we can say that System on Chip provides us the many great advantages of Fast
turn around time, flexibility and customization, cost/power/size optimization and at last high
performance.

The Drawbacks

The principle drawbacks of SoC design are associated with the design pressures imposed
on todays engineers, such as:
Time-to-market demands.
Exponential fabrication cost.
Increased system complexity.
Increased verification requirements

Dept. of Computer Science & Engg. 21 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

8. SOC APPLICATIONS AND FUTURE TRENDS

System on Chip applications can be broadly divided into four main types of
applications as featured below:

Speech Signal Processing: This refers to the acquisition, manipulation, storage, transfer
and output of vocal utterances by a computer. The main applications are the recognition,
synthesis and compression of human speech:
Speech recognition (also called voice recognition) focuses on capturing the
human voice as a digital sound wave and converting it into a computer-
readable format.
Speech synthesis is the reverse process of speech recognition. Advances in this
area improve the computer's usability for the visually impaired.
Speech compression is important in the telecommunications area for increasing
the amount of information which can be transferred, stored, or heard, for a
given set of time and space constraints.

Image and Video Signal Processing: Image processing is any form of signal processing
for which the input is an image, such as photographs or frames of video; the output of
image processing can be either an image or a set of characteristics or parameters related
to the image. Most image-processing techniques involve treating the image as a two-
dimensional signal and applying standard signal-processing techniques to it. Image
processing usually refers to digital image processing, but optical and analog image
processing are also possible.

Information Technologies: SoC is applied to different areas in Information technology

that includes the following given below:
PC interface (USB, PCI, PCI-Express, IDE, etc) Computer peripheries (printer
control, LCD monitor controller, DVD controller, etc).

Dept. of Computer Science & Engg. 22 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

Data Communication: This is concerned with communication between computer

systems or devices. SoC applications allow two types of data communication as
mentioned below:
Wire line Communication: 10/100 Based-T, xDSL, Gigabit Ethernet.
Wireless communication: BlueTooth, WLAN, 2G/3G/4G, WiMax, UWB

The ever increasing requirement on the functionality of handheld devices is pushing the
SoC designers to make more powerful, power efficient and cost effective SoCs with more and
more functionality going into a single chip which is getting smaller and thinner.

Latest SoCs feature CPU cores running at 500 MHz or more, peripherals include LCD and
Touch panel interface, camera interface, USB host/device, WLAN, Bluetooth, TV Out, Flash
memory controllers for Compact Flash, Memory Stick, SD Card etc., complex HW blocks such
as multi-format codecs, 3D accelerators, GPS Baseband, 3G Modems, and DSP cores.

Dept. of Computer Science & Engg. 23 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

9. CONCLUSION

System-on-chip has been a nebulous term that mystically holds out a lot of excitement,
and has been gaining momentum in the electronics industry. While the potential is huge, the
complexities are several, and countering these to offer successful designs is a true engineering
challenge. Technological advances mean that complete systems can now be implemented on a
single chip. The benefits that this brings are significant in terms of speed, area and power. The
reasons are not far to look: SoCs make available, on a single piece of silicon, the embedded IP
and high system-level integration required for performance demanding applications today. This
enables semiconductor manufacturers to cost-effectively meet specific system requirements
while delivering competitive time-to-market advantage.

A system-on-a-chip (SoC) can provide a single-chip solution, lower power usage, better
performance, more frugal use of board real estate, simpler integration, and lower part counts.
Compared to multichip solutions, the SoC has huge advantages, but mistakes in sizing on-chip
resources require spinning the ASIC and result in high cost. The SoC design concept has appeal
in a broad range of computing applications, from supercomputing to embedded systems.

Paradoxically, if the opportunities look promising, the challenges are no less daunting.
While opportunities come in the form of drastic reduction in the overall cycle time of the
system with superior performance levels, challenges are in the form of deep sub-micron
complexities, faster timing closure requirements, verification challenges and the need for an
extensive portfolio for pre-verified IP components. SoC designs typically exhort several man-
hours of skilled engineering resources. The drawbacks are that these systems are extremely
complex requiring amounts of verification. In catering to a competitive market with shortened
product cycle times, it is important to offer tangible reductions in design cycle time. The
solution is to design and verify re-useable IP.

Dept. of Computer Science & Engg. 24 College of Engg. Trikaripur, Cheemeni

Seminar Report 09 System-on-Chip

BIBLIOGRAPHY
1. International Symposium on System-on-Chip.
2. Wikipedia: http://en.wikipedia.org /wiki/System-on-a-chip
3. PCQuest Magazine
4. SoC drawer: The resource view: http://tinyurl.com/3lnt8t
5. Intel website: www.intel.com/pressroom/kits/soc
6. Wipro System-on-Chip Designs, white paper, June 2009

Dept. of Computer Science & Engg. 25 College of Engg. Trikaripur, Cheemeni