AEC Lab Manual

ANALOG ELECTRONICS CIRCUITS LAB MANUAL
III Semester B.E (E & E)
VISVESVARAYA TECHNOLOGICAL UNIVERSITY
DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING

P E S Institute of Technology & Management
NH-206, Sagar Road, Shivamogga – 577204
CONTENTS
EXPERIMENT NO 1: SERIES AND PARALLEL RESONANT CIRCUITS 1
EXPERIMENT NO 2: VERIFICATION OF THEVENIN’S THEOREM

AND MAXIMUM POWER TRANSFER THEOREM 5
EXPERIMENT NO 3: CLIPPING CIRCUITS 10
EXPERIMENT NO 4: CLAMPING CIRCUITS 19
EXPERIMENT NO 5: RECTIFIERS 25
EXPERIMENT NO 6: RC COUPLED AMPLIFIER 34
EXPERIMENT NO 7: DARLINGTON EMMITER FOLLOWER 40
EXPERIMENT NO 8: VOLTAGE SERIES FEEDBACK AMPLIFIER 44
EXPERIMENT NO 9: RC PHASE SHIFT OSCILLATOR 48
EXPERIMENT NO 10: HARTLEY AND COLPITTS OSCILLATOR 52
EXPERIMENT NO 11: CRYSTAL OSCILLATOR 55
EXPERIMENT NO 12: CLASS – B PUSH PULL POWER AMPLIFIER 57

Dept of Electrical and Electronics, PESITM, Shivamogga Analog Electronics Lab Manual
EXPERIMENT NO 1: SERIES AND PARALLEL RESONANT CIRCUITS
AIM
To obtain the frequency response of series and parallel circuit & hence to determine
i) Response frequency
ii) Bandwidth
iii) Q factor
APPARATUS / COMPONENTS REQUIRED
Sl No Apparatus Range Quantity

1 AFO 1
2 Ammeter 0-100 mA 1
3 Resistor 100Ω 1
4 Decade Inductance Box 500mH 1
5 Capacitor 1μF 1
6 Connecting Wires
7 Bread Board 1
THEORY
Resonance is the phenomenon and study of AC circuits, when an inductance coil and
capacitance are connected either in series or parallel across an alternating supply of varying
frequency. Resonance condition can be achieved either by keeping network elements same and
varying frequency or by keeping frequency constant and varying the frequency dependent
circuit element.
Resonance circuit are classified in 2 categories
Series Resonance
Parallel resonance
Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 1

A) SERIES RESONANCE
CIRCUIT DIAGRAM
Fig (a) Circuit diagram for Series Resonance
PROCEDURE
1. Rig up the circuit as shown in figure.
2. Switch on the supply and adjust the signal generator to say 10V peak to peak.
3. Vary frequency gradually from zero and note down the reading of Ac current Io in
ammeter for different values of frequency.
4. Take down the readings for smaller steps of frequency near the maximum current value
to get accurate resonance frequency.
5. From the tabulated readings plot a graph of current versus frequency. This graph is
called as frequency response.
6. From graph note down the resonant frequency (f0) at which current is largest (I0).
7. Note down the frequency f1 & f2 corresponding to a current of (I0/√2).
8. Find Bandwidth and Q factor using the formula given below.
i. f1 = Lower half power frequency (Theoretical Equation f1 = f0-(R/ 4πL)
ii. f2 = upper half power frequency (Theoretical Equation f2 = f0+(R/ 4πL)
iii. Band Width = (f2-f1) (Theoretical Equation BW = R/ 2πL or BW = f0/Q)
iv. Q Factor = f0 / (f2-f1) (Theoretical Equation f1 Q0 = (1/R)*√ (L/C)
DESIGN PROCEDURE
Assume R=100Ω, C=1µF and resonating frequency, f0 =225Hz and calculate L.
Series Resonance: f0 = 1/2π√(LC)
Parallel Resonance: f0 = 1/2π√[(1/LC) – (R/2L)2]

TABULAR COLUMN
Sl. No F in Hz I in mA
GRAPH
Current in mA
I0
I0/√2
F1 F0 F2 Frequency in
Hz
B) PARALLEL RESONANCE
CIRCUIT DIAGRAM
Fig (b) Circuit diagram for Parallel Resonance

TABULAR COLUMN
Sl. No F in Hz I in mA
GRAPH
Current in mA
I0√2
I0
F1 F0 F2 Frequency in Hz
RESULT
Circuit Series Parallel

Parameter Resonance Resonance
Theoretical Resonating Frequency
Practical Resonating Frequency
Theoretical bandwidth
Practical bandwidth
Theoretical Q Factor
Practical Q Factor

EXPERIMENT NO 2: VERIFICATION OF THEVENIN’S THEOREM AND MAXIMUM

POWER TRANSFER THEOREM
a) THEVENIN’S THEOREM
AIM
To state and verify the Thevenin’s theorem for the given circuit diagram.
COMPONENTS / APPARATUS REQUIRED

Sl. No Apparatus Range Quantity
1 VRPS 0 – 30V 1
2 DC Ammeter 0 – 10mA 1
3 DC Voltmeter 0 – 10V 1
4 Resistors 1KΩ 4
5 Bread Board 1
6 Connecting Wires
STATEMENT
“Any linear, bilateral network containing energy sources and impedances can be replaced
with its equivalent Thevenin circuit consisting of a “voltage source” (VTh) in series with an
“impedance” (ZTh). The value of voltage source is open circuit voltages between the
terminals of a network and the value of impedance is the impedance measured between the
two terminals of the network with all energy sources reduced to zero.
CIRCUIT DIAGRAM
Fig (a)

Fig (b)
Fig (c)
Fig (d)
PROCEDURE
1) Given circuit is as shown in Fig1 (a).
2) Connections are made as shown in Fig 1(b).
3) Supply voltage is adjusted to 5V and the ammeter reading IL is noted down.

4) Open circuit the terminal A and B, voltmeter reading VTh = V0 is measured which
is the Thevenin’s voltage therefore V0 = VTh = ------------ V.
5) To find Thevenin’s impedance, connections are made as shown in Fig 1 (c).
6) The readings of voltmeter V and ammeter I, are noted down. The Thevenin’s
impedance is obtained by ZTh = V/I = ------------ Ω.
7) Thevenin’s equivalent circuit connections are made as shown in Fig 1 (d).
8) The supply voltage is set to VTh as measured above.
9) The ammeter reading ITh is noted. If ITh = IL then the Thevenin’s theorem is
verified.
RESULT
The Thevenin’s theorem for the given circuit is verified.
IL = _________________A
VTh =_______________ V
ZTh =________________Ω
ITh =_______________ A
b) MAXIMUM POWER TRANSFER THEOREM
AIM
i) To state and verify Maximum power transfer theorem.
ii) To determine maximum power and the value of RL for Maximum power transfer
theorem.

1 VRPS 0 – 30V 1
2 DC Ammeter 0 – 10mA 1
3 DC Voltmeter 0 – 10V 1
4 Resistors 1KΩ 1

5 Potentiometer 10kΩ 1
6 Bread Board 1
7 Connecting Wires
STATEMENT
“For a pure variable resistor load, Maximum power transfer takes place from source to load,
when the value of load resistance equals source resistance”
OR
“The Maximum power will be transferred to the load when the load impedance is complex
conjugate of circuit impedance”
CIRCUIT DIAGRAM
Fig (a)
Fig (b)
PROCEDURE
1. Connections are as shown in Fig 2 (a).
2. Supply voltage v is set to 10V.
3. The potentiometer (POT) RL is kept at maximum.

4. The readings of voltmeter V and ammeter I, are noted down in tabular column.
5. A graph of versus power is plotted.
6. The maximum power P max and the value of RL for maximum power transfer are noted
from graph. P max in watts and RL in Ω
7. To measure source resistance the connections are made as shown in Fig 2 (b)
8. Supply is set to 10V, the ammeter reading I and voltmeter reading v are noted down
9. The source resistance RS = V/I Ω
10. If RS = RL Maximum power transfer theorem is verified.
TABULAR COLUMN
Sl No V in volts I in mA P=VI in mW RL=V/I in kΩ
GRAPH
RESULT
The Maximum power transfer theorem is verified.
RS = -------------- Ω
RL= ----------------Ω

EXPERIMENT NO 3: CLIPPING CIRCUITS
AIM
To design and test the diode clipping (single or double ended) circuits for the peak clipping
and peak detection.

1 AFO 1
2 VRPS Dual Supply 0 – 30V 1
3 CRO 1
4 Resistors 10KΩ 1
5 Diode IN4007 2
6 Bread Board 1
7 Connecting Wires
THEORY
Clippers are networks that employ diodes to clip away portions of an input signal
without distorting the remaining part5 of the applied waveform. These clipper circuits
transfer a selected portion of the input waveform to the output diode clipping circuits are
used to prevent a waveform from exceeding some particular limit either negative or positive
or both. This is achieved by connecting the diode in serial or in parallel circuit. Variable DC
voltage is connected in the circuit to achieve required level of clipping. By using different
level DC voltages, it is possible to get different level of clipping in positive and negative side.
These clippers are also called as limiters.
PROCEDURE
1. Place the components on bread board and connect them as per the circuit diagram 1(a).
Use the wires for connection as required.

2. Switch on the signal generator and set voltage to 10V P-P and frequency to 100Hz,
3. Using CRO measure the output wave form and sees that it matches with required wave
form. Vary the DC voltage and tabulate the level of clipping.
4. Connect the input and output wave form to the two channels of the CRO and using XY
mode observe and note down the transfer characteristic.
5. Note down input & output wave form and draw it on graph.
6. Repeat this for other clipping circuits.
CIRCUIT DIAGRAM AND DESIGN PROCEDURE

1) Diode shunt clipping above VR or Positive peak clipping
Refer to the circuit diagram 1(a), Let the output voltage be clipped to say +2v
V0 (max) = +2V
V0 (max) =Vr+VR; Where Vr = 0.6 for silicon diode, is cut in voltage
VR = V0 (max) – Vr
VR = 2v-0.6v = 1.4v
The value of resistor is chosen to be R = √ (Rf Rr)
Where Rf = diode forward resistance = 10 Ω
Rr = diode reverse resistance = 10M Ω
R = √ (Rf Rr) = √ (10*10M) = 10K Ω
Fig 1(a) Circuit Diagram

Fig 1(b) Input & output waveforms
Fig 1(c) Transfer Characteristics

2) Diode shunt clipping above VR or Positive peak clipping
Refer to the circuit diagram 2(a)
Let the negative voltage be clipped to say -2v
V0 (min) = -2v
V0 (min) =Vr-VR => VR = -1.4v and R =10K Ω

Fig 2 (c) Transfer characteristic
3) Diode series clipping above VR or Positive peak clipping

Let the output voltage be clipped to say +2v
V0 (max) = VR = +2V and R =10K Ω

Fig 3(c) Transfer Characteristics
4) Diode series clipping below VR or Negative peak clipping

Let the output voltage be clipped to say -2v
V0 (max) = VR = -2v and R =10K Ω
Fig 4 (a) Circuit Diagram
Fig 4 (b) Input & output waveforms

Fig 4 (c) Transfer characteristic

5) Clipping at two independent levels or slicer circuits
To obtain a slice of input voltage between 2v and 4v levels at its output
Let VR1 > VR2, V0 (max) = 4v = VR1 + VR
VR1 = 4v - 0.6v = 3.4v
Also V0 (min) =2v = VR2 – VR
VR2 = -2v + 0.6v =-1.4v and R =10K Ω

Fig 5 (c) Transfer characteristics

6) Double ended clipper to generate a symmetrical square wave or squarer.
To generate a symmetrical square wave of ± VR volts when Vi = Vm sin ωt
VR1 = 2v – 0.6v = 1.4v and
V0 (min) = VR2 – VR
VR2 = V0 (min) + VR = -2v + 0.6v = -1.4v and R = 10K Ω

6(c) Transfer characteristics

7) Clipping circuits to clip the centre portion and transmit the extremities of
sinusoidal signal.
To clip a sinusoidal wave between +2v and -3v level
V0 = VR1 + 0.6v
VR1 = 2v – 0.6v = 1.4v
Similarly V0 = -3v = VR2 – 0.6v
VR2 = - 3v + 0.6v = -2.4v and R = 10K Ω
7 (b) Input & output waveforms

7 (c) Transfer characteristics

RESULT
All types of clipper circuits are tested and output waveform matches with the expected
waveform.

EXPERIMENT NO 4: CLAMPING CIRCUITS
AIM
To design and test the clamping circuits for Positive and Negative clamping.

1 AFO 1
2 VRPS Dual Supply 0 – 30V 1
3 CRO 1
4 Resistors 100KΩ 1
5 Diode IN4007 1
6 Capacitor 0.1µF 1
7 Bread Board 1
8 Connecting Wires
THEORY
Clamper is a circuit that clamps a signal to a different dc level without changing the
appearance of the applied signal. The magnitude of R and C must be chosen such that the
time constant RC is large enough to ensure voltage across capacitor does not discharge
significantly during the interval the diode is non-conducting. By connecting suitable Dc
voltage in series with the diode, the level of swing can be varied.
PROCEDURE
1. The Circuits are wired up as shown in the circuit diagrams for each case.
2. A sinusoidal signal of 1KHz and amplitude of 10VP-P is applied as input Vi from
AFO
3. Observe the output waveform on the CRO and verify it with the given waveforms.

DESIGN PROCEDURE
Given f = 1K Hz => T = 1msec choose RC >> T
Let RC = 10 T = 10m sec
Let R =√ (Rf*Rr) = 100K Ω
RC = 10ms => 100K Ω*C = 10ms
Therefore C = (10ms / 100 K) = 0.1 μF
1. (a) Positive voltage clamping without reference.

V0 = Vi + Vm -------------- (1)
When Vi = 0 in equation (1), V0 = Vm
When Vi = Vm in equation (1), V0 = 2Vm
When Vi = -Vm in equation (1), V0 = 0 [which can be observed from the I/O waveforms]
Fig 1.a. (i) Circuit Diagram
Fig 1.a. (ii) Input & Output Waveforms

1. (b) Positive voltage clamping with Positive reference.

Let V0 (min) = 2V; V0 (min) = VR – Vr => VR = 2 + 0.6 = 2.6
Fig 1.b. (i) Circuit Diagram
Fig 1.b. (ii) Input & Output Waveforms
1. (c) Positive voltage clamping with Negative reference.
Let V0 (min) = -2V; V0 (min) = VR – Vr => VR = -2 + 0.6 = -1.4
Fig 1.c. (i) Circuit Diagram

Fig 1.c. (ii) Input & Output Waveform
2. (a) Negative voltage clamping without reference.
V0 = Vi – Vm ----------------- (2)
When Vi = 0 in equation (2), V0 = - Vm
When Vi = Vm in equation (2), V0 = 0
When Vi = -Vm in equation (2), V0 = -2 Vm
Fig 2.a. (i) Circuit Diagram
Fig 2.a. (ii) Input & Output Waveforms

2. (b) Negative voltage clamping with Positive reference
Let V0 (max) = 2V; V0 (max) = VR +Vr => VR = 2V – 0.6 V = 1.4V
Fig 2.b. (i) Circuit Diagram
Fig 2.b. (ii) Input & Output Waveforms
2 (c) Negative voltage clamping with Negative reference.
Let V0 (max) =- 2V; V0 (max) = VR +Vr => VR = -2V – 0.6 V = -2.6V

Fig 2.c. (i) Circuit Diagram
Fig 2.c. (ii) Input & Output Waveforms
RESULT
All types of clamper circuits are tested and output wave form matches with the
expected waveform.

EXPERIMENT NO 5: RECTIFIERS
1) HALF WAVE RECTIFIERS

AIM
To find the efficiency of half wave rectifier and the ripple factor with and without capacitor filter.
COMPONENTS/ APPARATUS REQUIRED
CIRCUIT DIAGRAM
Fig 1 (a) circuit diagram for half wave rectifier without capacitor

Fig 1 (b) Input & Output waveforms for Fig 1 (a)
Fig 1 (c) Circuit diagram for Half wave rectifier with capacitor
Fig 1 (d) Output waveform for circuit in Fig 1 (c)

PROCEDURE
1. The connections are made as shown in the circuit diagram.
2. An input is applied to the diode through the secondary of the transformer.
3. The output waveform is observed on the CRO.
4. The amplitude on the CRO, of the output is measured from which ŋ and �is calculated.
5. Capacitor filter is connected and the amplitude of the output, the ripple voltage is noted down.
6. The ŋ and ripple factor are calculated from above readings.

TABULAR COLUMN
a) Without capacitor filter

2)FULL WAVE RECTIFIERS
AIM
To find the efficiency of full wave rectifier and the ripple factor with and without capacitor filter.
SL.NO Apparatus / Range Quantity

components
required
01 Transformer 1
02 Diode IN4007 2
03 Resistor 1K Ω 1
04 Capacitor 470μF 1
05 CRO 1
CIRCUIT DIAGRAM
Fig 2 (a) Circuit diagram for full wave rectifier without capacitor

Fig 2(b) Input & Output waveforms for Fig 2 (a)
Fig 2 (C) Circuit diagram for full wave rectifier with capacitor
Fig 2 (d) Output waveform for the circuit in fig 2(c)
PROCEDURE
4. The amplitude on the CRO, of the output is measured from which ŋ and �is calculated.

TABULAR COLUMN

3) BRIDGE RECTIFIERS
AIM
To find the efficiency of Bridge rectifier and the ripple factor with and without capacitor filter.
SL.NO Apparatus / Range Quantity

components
required
01 Transformer 1
02 Diode IN4007 4
03 Resistor 1K Ω 1
04 Capacitor 470μF 1
05 CRO 1
CIRCUIT DIAGRAM
Fig 3 (a) Circuit diagram for Bridge rectifier without capacitor

Fig 3(b) Input & Output waveforms for Fig 3 (a)
Fig 3 (c) Circuit diagram for Bridge rectifier with capacitor
Fig 3(d) Output waveform for the circuit in Fig 3 (c)
PROCEDURE
4. The amplitude on the CRO, of the output is measured from which ŋ is calculated.


EXPERIMENT NO 6: RC COUPLED AMPLIFIER
AIM
Design RC Coupled single stage BJT/FET amplifier and determine the gain, Frequency response,
input
and output impedance.
CIRCUIT DIAGRAM
Fig (a) Circuit diagram for RC coupled amplifier

DESIGN PROCEDURE
Select transistor BC107b having the following specifications,
Ie=Ic= 2mA; ß=215; Vce=5v; Vcc=2Vce =>10v
To find Re
Choose Ve =Vcc/10=10/10 =1 v
Ve = Ie*Re =>Re=Ve / Ie
Re = 1 / Ie =1 / 2mA = 0.5K Ω
Select Re = 560 Ω
To find Rc
Choose Vce = Vcc / 2 =10/2=5 v
Apply KVL in CE loop:
Vcc- (IcRc) - Vce - Vre=0
10v-(2mA* Rc) – 5v –1v=0
Rc = (10v-5v-1v) / 2mA
Rc = 2K Ω
Select Rc= 2.2K Ω
To find R1 & R2
Vb = Vbe + Ve => 0.7v + 1v = 1.7v
Vb =(Vcc*R2) / ( R1 + R2 )
1.7v = (10v*R2) / ( R1 + R2 ) => R2/(R1+ R2)=1.7v/10v
10 R2 = 1.7 R1 +1.7 R2
R1= 4.8* R2
Select R2 =4.7K Ω
R1 = 4.8 * 4.7K Ω => R1 = 22.56K Ω

Select R1 = 27K Ω

To find Bypass capacitor Ce:

Let Xce = Re / 10, at f = 100 Hz; 1/(2π*f*Ce) = Re / 10
Therefore Ce=10 / (2π*100 Hz *560 Ω) =31.8 micro farad
Choose Ce=50 micro F (electrolytic)
To find Cc1 and CC2

Assume CC1 & CC2 = 0.47 micro F (ceramic)
To design
Xcc1 = (Hie||Rb)/10, Xcc1 =1/ (2π*f*Cc1), Cc1=?
Xcc2 = (Rc||Rl)/10, Xcc2 =1/ (2π*f*Cc2), Cc2=?
PROCEDURE
1. Connect the circuit as shown above.
2. Feed a sine wave signal of amplitude 20 mV from signal generator.
3. Keep the frequency of the signal generator in mid band range i.e., around 2 KHz. Increase
amplitude of the input signal till the output signal is undistorted.(CRO at output).
4. Measure Vi amplitude =__________V for corresponding maximum undistorted output.
5. Measure Vo amplitude =__________V
6. The ratio of (Vo/Vi) max gives the maximum undistorted gain of the amplifier.
7. Now vary the input sine wave frequency from 10 Hz to 1 MHz in suitable steps. Measure
output voltage amplitude at each step using CRO.(See that amplitude of Vi remains constant
throughout the frequency range.)
8. Tabulate the results in the tabular column shown below.
9. Plot the frequency i.e., frequency versus Gain in dB, determine Bandwidth and G.B.W
product.

TABULAR COLUMN
Take the readings for 100 Hz to 1Khz in 100Hz steps, 1Khz to 10Khz in 1Kz steps, 10khz
to 100khz in 10khz steps, 100khz to 1mHz in 100kHz steps (total 37 readings) Note down
Vi (P-P)…….
FREQUENCY RESPONSE
f1 is Lower Cut-Off Frequency.

f2 is Higher Cut-Off Frequency.
Av is the Voltage Gain = 20log10 (Vo/Vi).
Av mid is the Voltage Gain at mid-band.
F2-F1 is the Band width of the amplifier.
3dB = 20log10 (0.707).

TO MEASURE Zin
PROCEDURE TO FIND Zin

1. Connect the circuit as shown in above figure
2. Set the following
DRB to 0Ω
Input sine wave amplitude to say 40 mV
Input sine wave frequencies to any mid frequency say 10 KHz.
3. Measure amplitude of Vop-p. Let Vo=Va say
4. Increase DRB (keeping Vi constant) till Vo=Va/2.The corresponding DRB gives the input
impedance Zin in RC coupled amplifier
TO MEASURE Zo :
PROCEDURE TO FIND Zo
1. Connect the circuit as shown in the above figure
DRB to its maximum resistance value.
Input sine wave amplitude to about 40 mV
Input sine wave frequency to 10 KHz.
3. Measure Vop-p. Let Vo=Vb

4. Decrease DRB from its maximum value till Vo=Vb/2.The corresponding DRB gives the
output impedance Zo.
RESULT
Thus the RC Coupled Amplifier was designed and studied.
Gain = …………………….
Bandwidth =………………
Gain-Bandwidth product =…………………………
Input Resistance =………………………..
Output Resistance =…………………………

EXPERIMENT N0 7: DARLINGTON EMMITER FOLLOWER
AIM
Design of a BJT Darlington emitter follower and determine the gain, input and output
impedances.
CIRCUIT DIAGRAM

Note: - R1 & R2 junction is not directly connected to CC1 and Q1 base.
DESIGN OF BIAS CIRCUIT

Let Vce = 6V, Ieq=10mA (Q point of transistor Q2)
Then Vcc = 2Vce=2 x 6 =12 V
Ie = Ic = 10 mA
VR3 = Vcc - Vce= 12 – 6 = 6V
Re= VR3 / Ie = 6V / (10 mA) = 0.6K =560Ω (Choose)
VR2 -Vbe1 - Vbe2 – VR3 = 0 and VR2 = Vbe1 + Vbe2 + VR3
= 0.6 + 0.6 + (Ie.Re) = 1.2 + (10x0.6) = 7.2V
Vcc = Vr1 + Vr2
VR1= Vcc – VR2 = 12 – 7.2 = 4.8 V

Ie1= Ib2 = Ic / hfe = 10 mA / 100 = 0.1mA
Ib1=Ie1 / hfe = 0.1mA / 100 = 1 μA
R1 = VR1/ (10 (Ib1)) = 4.8 / (10 x 1 μA) = 480 KΩ
R2= VR2 / (9 Ib) = 7.2 / (9 x 1 μA = 800kΩ

To find Cc
PROCEDURE
1. To find Q-point: Connect the ckt without Ac supply .Set Vcc=12V.Measure the DC voltage
(using CRO/multimeter) at the (VB2), Collector (VC2) emitter (VE2) w.r.t ground. Then
determine VCE2=VC2 – VE2, IC2=IE2=VE2 / RE
2. Q point = (Vce2, Ic2)
3. Connect the signal generator and apply a sine wave of peak-to-peak amplitude 1V , 1kHz
from the signal generator and note down the output wave form.
4. Gradually increases the input signal until the output signal get distorted. When this
happens slightly reduce the input signal amplitude such that output is maximum undistorted
signal. Then measure the magnitude of the input and output waveform. Calculate the Voltage
gain.
5. Find the input and output impedance as explained below
6. Connect the bootstrap circuit Rb and Cb between the emitter and base as shown in the
circuit. Repeat the steps 3 to 5
Avm = Vi/Vo
TO MEASURE Zin AND Zo
1. To measure Zin (Input Impedance)

Procedure to find Zin

1. Connect the circuit as shown in figure.
2. Set the DRB to minimum resistance (0Ω), I/P sine wave amplitude to 1V p-p, I/P sine
wave Frequency to 10 KHz.
3. Measure Vo (p-p). Let Vo=Va
4. Increase DRB till Vo=Va/2.the corresponding DRB value gives Zin.
2. To measure Zo (Output Impedance)
PROCEDURE
1. Connect the circuit as shown in figure. Set the DRB to its maximum resistance value, I/P
sine wave Frequency to 10 KHz.
2. Measure Vo p-p, let Vo = Vb
3. Decrease DRB till Vo =Vb/2.
4.The corresponding DRB value gives Zo.
To find the current gain

Ai=Io/Ii= (Vo/Zo)/(Vi/Zin) = (Vo/Vi) * (Zin/Zo)
Current gain Ai ≈ Zin / Zo, since (Vo/Vi) = 1
RESULT
Thus the Darlington’s Emitter follower was designed and studied

EXPERIMENT NO 8: VOLTAGE SERIES FEEDBACK AMPLIFIER
AIM
To design and test a voltage series feedback amplifier to meet the following specification
i) Input impedance = 2MΩ
ii) Voltage gain AV = 2
COMPONENTS /APPARATUS REQUIRED

SL.NO Apparatus / RANGE Quantity
components required
01 FET BFW10 1
02 Resistors
03 Capacitors
04 VRPS 0-30Vdc 3A 1
05 AFO 10Hz to 1Mhz 1

06 Probes & wires
07 CRO 1
08 Bread board 1
09 DRB 0 to1Mohm 1
CIRCUIT DIAGRAM

PROCEDURE
1. Before wiring the circuit, check the given component using multimeter.
2. Make the circuit connections as shown in Fig (a).
3. Set the signal generator amplitude to say 1V (p-p) (sine wave).
4. By varying the frequency of the input from Hz range to higher 1MHz range.
5. Note the frequency of the signal & corresponding voltage across the load resistor with
respect to ground.
6. The output voltage Vo remains constant in mid frequency range.
7. Tabulate the readings in tabular column.
8. Plot the graph with frequency along X- axis and gain dB along Y- axis.
9. From the graph determine the bandwidth.
10. With the one end of the POT removed the voltage series amplifier circuit without
feedback circuit is obtained
PROCEDURE TO FIND Zin

1. Connect the circuit as shown in above figure
DRB to 0Ω
Input sine wave amplitude to say 40 mV
Input sine wave frequencies to any mid frequency say 10 KHz.
3. Measure amplitude of Vop-p. Let Vo=Va say
4. Increase DRB (keeping Vi constant) till Vo=Va/2.The corresponding DRB gives the input
impedance Zin of voltage series amplifier

TABULAR COLUMN
TO MEASURE Zin

TO MEASURE Zo
PROCEDURE TO FIND Zo
1. Connect the circuit as shown in the above figure
DRB to its maximum resistance value.
Input sine wave amplitude to about 40 mV
Input sine wave frequency to 10 KHz.
3. Measure Vop-p. Let Vo=Vb
4. Decrease DRB from its maximum value till Vo = Vb/2.The corresponding DRB gives the
output impedance Zo.
RESULT
Thus the voltage series feedback Amplifier was designed and studied.
Circuit VOLTAGE SERIES AMPLIFIER VOLTAGE SERIES AMPLIFIER
Parameter WITH FEEDBACK WITHOUT FEEDBACK
Gain
Bandwidth
Input Resistance
Output Resistance

EXPERIMENT NO 9: RC PHASE SHIFT OSCILLATOR
AIM
Wiring and testing for the performance of BJT- RC phase shift oscillator for fo ≤ 10KHZ
COMPONENTS/APPARATUS REQUIRED
THEORY
RC phase shift Oscillator basically consists of an amplifier and feed back network consisting
of resistors and capacitors in ladder fashion. The basic RC circuit is as shown below
The current I is in phase with Vo, whereas the capacitor voltage Vc lags the current I by φ
(90®→Ideal value).OR the output voltage Vo leads the I/P voltage Vi by angle φ is adjusted in
practice, equal to 60®.RC network is used in feedback path. In Oscillator, feedback network must

introduce a phase shift of 180® to obtain total phase shift around a loop as 360®.Thus three Rc
network each provide 60® phase shift is cascaded, so that it produces total 180® phase shift.
The Oscillator circuit consisting amplifier and Rc feedback network is as shown below
CIRCUIT DIAGRAM
Fig (a) Circuit diagram for RC Phase shift Oscillator
DESIGN PROCEDURE
Select transistor BC107b having the following specifications,
Ie=Ic= 2mA; ß=215; Vce=5v; Vcc=2Vce =>10v
To find Re:
Choose Ve =Vcc/10=10/10 =1 v
Ve = Ie*Re =>Re=Ve / Ie
Re = 1 / Ie =1 / 2mA = 0.5K Ω
Select Re = 560 Ω
To find Rc:
Choose Vce = Vcc / 2 =10/2=5 v
Apply KVL in CE loop:
Vcc- (IcRc) - Vce - Vre=0
10v-(2mA* Rc) – 5v –1v=0
Rc = (10v-5v-1v) / 2mA
Rc = 2K Ω
Select Rc= 2.2K Ω
To find R1 & R2
Vb = Vbe + Ve => 0.7v + 1v = 1.7v
Vb =(Vcc*R2) / ( R1 + R2 )
1.7v = (10v*R2) / ( R1 + R2 ) => R2/(R1+ R2)=1.7v/10v
10 R2 = 1.7 R1 +1.7 R2
R1= 4.8* R2
Select R2 =4.7K Ω
R1 = 4.8 * 4.7K Ω => R1 = 22.56K Ω
Select R1 = 27K Ω
To find Bypass capacitor Ce:

Let Xce = Re / 10, at f = 100 Hz; 1/(2π*f*Ce) = Re / 10
Therefore Ce=10 / (2π*100 Hz *560 Ω) =31.8 micro farad
Choose Ce=50 micro F (electrolytic)
To find Cc1 and CC2:

Assume CC1 & CC2 = 0.47 micro F (ceramic)
To design:
Xcc1 = (Hie||Rb)/10, Xcc1 =1/ (2π*f*Cc1), Cc1=?
Xcc2 = (Rc||Rl)/10, Xcc2 =1/ (2π*f*Cc2), Cc2=?

Design of phase shifting network

The frequency of oscillator is determined by phase shifting network. The oscillating
frequency for the above circuit is given by
f = 1/ (2ΠRC√ (6+4K))
Where K = Rc/R which is usually less than 1.
Let f = 10K HZ and R = 10KΩ => k = (2.2K Ω/10K Ω) = 0.22
f = 1/ (2ΠRC√ (6+4K))
10K = 1/ (2Π*10K*C√ (6+4(0.22)))
=> C = 0.006 μ F [choose C = 0.0047 μ F]
NOTE
The last resistor in the phase shifting network is chosen to be a 10K POT. This is done to get
an overall phase shift of 180º at frequency of oscillations. The minimum hfe required for the
transistor to oscillate is hfe min = 23 + 29(R/Rc) + 4(Rc/R)
Where Rc = 1K Ω and R = 2.2K Ω (Phase shifting network)
Therefore hfe (min) = 23 + 29(2.2K/1K) +4 = (1K/2.2K) = 89.The transistor should be
chosen to have a value hfe of greater than 89
PROCEDURE
1. Make the circuit connection as shown in fig. a

2. The output Vo is obtained on CRO.
3. The 10K POT is adjusted to get a stable out on the screen of CRO.
4. The frequency of oscillations is measured using CRO is then compared with theoretical
values.
5. We can see the phase shift at each point being 60º, 120º & 180º
RESULT
Theoretical frequency = ………………………
Practical frequency = ………………………

EXPERIMENT NO 10: HARTLEY AND COLPITTS OSCILLATOR
AIM
To test the performance of BJT Hartley and colpitts oscillator for RE range fo ≥ 100K Hz
CIRCUIT DIAGRAM
Fig (a) Circuit diagram for Hartley oscillator

Fig (b) Circuit diagram for Crystal oscillator
DESIGN PROCEDURE
Select BF194 BJT having the following specifications
Vce = 10V, Ic = 1mA, hfe = 115, hie = 1.85K
Ce = 36.17μF hence choose Ce = 47μF
Selecting coupling capacitance Cc1 and Cc2
Choose Cc1 = Cc2 = 0.047 μF
{Other designs are as specified as in amplifier experiment}
Design of tank circuit

fo = where Leq=L1 + L2
fo = 100K Hz choose C = 0.001 μF
(fo) 2 = =>

PROCEDURE
1. Rig up the circuit as shown in Fig (a) for Hartley oscillator and (b) for colpitts oscillator.
2. Adjust 10K POT to obtain proper sinusoidal output waveform.
3. Measure the frequency of oscillations and compare with designed value.
RESULT

EXPERIMENT NO 11: CRYSTAL OSCILLATOR
AIM
Testing for the performance of BJT-Crystal oscillator for fo > 100K Hz.
SL.NO Apparatus/Components Range Quantity

Required
01 BJT BF-194 1
02 Resistor 1each
03 Crystal 1
04 Inductance box 1
05 Potentiometer
06 Capacitor
07 CRO 1
08 Probes & wires
09 VRPS 1
CIRCUIT DIAGRAM
Fig (a) Circuit diagram for Crystal oscillator

PROCEDURE
1. Rig up the circuit as shown in the circuit diagram (a).

2. Adjust 10K POT to obtain proper sinusoidal output waveform.
3. Measure frequency of oscillations and compare with designed value.
RESULT
Theoretical frequency =
Practical frequency =

EXPERIMENT NO 12: CLASS – B PUSH PULL POWER AMPLIFIER
AIM
To test class-B transformer less push pull amplifier for crossover distortion and find its
conversion efficiency.
Sl. No Apparatus and Range Quantity
components
01 Bread board 1
02 NPN & PNP transistors SL100 1 each
03 Resistors
04 Capacitors
05 VRPS 0-30Vdc 3A 2
06 Signal generator 10Hz to 1Mhz 1
07 CRO
08 Probes, wires
09 Multimeter 1
CIRCUIT DIAGRAM

PROCEDURE
1. Rig up the circuit as shown in figure.
2. Keep increasing the input signal, from 0, until crossover distortion is observed. Note
down the waveform and peak values of input and output voltage.
3. Calculate the conversion efficiency using the formula
OUTPUT WAVEFORM
RESULT
Conversion Efficiency =………………………………………..

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ANALOG ELECTRONICS CIRCUITS LAB MANUAL

III Semester B.E (E & E)

VISVESVARAYA TECHNOLOGICAL UNIVERSITY

DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING

EXPERIMENT NO 1: SERIES AND PARALLEL RESONANT CIRCUITS 1

EXPERIMENT NO 2: VERIFICATION OF THEVENIN’S THEOREM

EXPERIMENT NO 3: CLIPPING CIRCUITS 10

EXPERIMENT NO 4: CLAMPING CIRCUITS 19

EXPERIMENT NO 6: RC COUPLED AMPLIFIER 34

EXPERIMENT NO 7: DARLINGTON EMMITER FOLLOWER 40

EXPERIMENT NO 8: VOLTAGE SERIES FEEDBACK AMPLIFIER 44

EXPERIMENT NO 9: RC PHASE SHIFT OSCILLATOR 48

EXPERIMENT NO 10: HARTLEY AND COLPITTS OSCILLATOR 52

EXPERIMENT NO 11: CRYSTAL OSCILLATOR 55

EXPERIMENT NO 12: CLASS – B PUSH PULL POWER AMPLIFIER 57

EXPERIMENT NO 1: SERIES AND PARALLEL RESONANT CIRCUITS

APPARATUS / COMPONENTS REQUIRED

Sl No Apparatus Range Quantity

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 1

Fig (a) Circuit diagram for Series Resonance

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 2

Fig (b) Circuit diagram for Parallel Resonance

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 3

Circuit Series Parallel

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 4

EXPERIMENT NO 2: VERIFICATION OF THEVENIN’S THEOREM AND MAXIMUM

COMPONENTS / APPARATUS REQUIRED

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 5

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 6

b) MAXIMUM POWER TRANSFER THEOREM

COMPONENTS / APPARATUS REQUIRED

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 7

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 8

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 9

EXPERIMENT NO 3: CLIPPING CIRCUITS

COMPONENTS / APPARATUS REQUIRED

Sl. No Apparatus Range Quantity

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 10

CIRCUIT DIAGRAM AND DESIGN PROCEDURE

Fig 1(a) Circuit Diagram

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 11

Fig 1(b) Input & output waveforms

Fig 1(c) Transfer Characteristics

Fig 2(a) Circuit Diagram

Fig 2(b) Input & output waveforms

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 12

Fig 2 (c) Transfer characteristic

3) Diode series clipping above VR or Positive peak clipping

Fig 3(a) Circuit Diagram

Fig 3(b) Input & output waveforms

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 13

Fig 3(c) Transfer Characteristics

4) Diode series clipping below VR or Negative peak clipping

Fig 4 (a) Circuit Diagram

Fig 4 (b) Input & output waveforms

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 14

Fig 4 (c) Transfer characteristic

Fig 5 (a) Circuit Diagram

Fig 5 (b) Input & output waveforms

Prepared by: Ms.Aparna Rao S.L. and Shamanth.G.S. 15

Fig 5 (c) Transfer characteristics

Fig 6 (a) Circuit Diagram

Fig 6 (b) Input & output waveforms