ADSP 2100

BUSES & MEMORY INTERFACE

Jithin Krishnan
MTV\05\10
BUSES

• Five on chip buses

 Data memory address (DMA) bus

 Data memory data (DMD) bus

 Program memory address (PMA)

bus
 Program memory data (PMD) bus

 Result (R) bus

BUSES

• Multiplexed into a single external

address bus and a single external data
bus
• BMS’, DMS’ and PMS’ signals select
the different address spaces.
• PMD-DMD bus exchange unit
• Contains hardware to overcome the 8-
bit width discrepancy between the two
buses
BUSES
DMA 14 bits
bus Allow direct access up to 16k words of data

DMD 16 bits
bus Register to register or any data memory
location in a single cycle
PMA 14 bits
bus Direct access of up to 16k words of mixed
instruction code and data
PMD 24 bits
bus Transfer data to and from computational
units

R bus Transfer intermediate results b/w

computational units
DATA MEMORY MAP
DATA MEMORY MAP

• Can address a total of 16K words of 16-bit

data memory
• On-chip data memory starts at address
0x3800
• The processors’ control and status registers
are mapped into the top 1K of data memory,
addresses 0x3C00-0x3FFF.
• The rest of the top 1K is reserved.
• External data memory is available for
additional data storage.
External Data Memory
Read/Write

1. The processor places the address on the DMA

bus, which is multiplexed off-chip, and DMS is
asserted.
2. RD or WR is asserted.
3. Within a specified time, data is placed on the data
bus, multiplexed to the internal DMD bus.
4. The data is read or written and RD (or WR ) is
deasserted.
5. DMS is deasserted.
PROGRAM MEMORY MAP
Program Memory Maps

Two configurations depending on the state of the

MMAP pin

When MMAP=0, internal RAM occupies 2K words beginning

at address0x0000. In this configuration, the boot loading
sequence is automaticallyinitiated when RESET is released
(as described in “Boot Memory Interface”).
When MMAP=1, words of external program memory begin at
address 0x0000 and internal RAM is located in the upper 2K
words, beginning at address 0x3800. In this configuration,
program memory is not loaded although it can be written to
and read from under program control.
External Program Memory Read / Write

1. The processor places the address on the PMA bus,

which is multiplexed off-chip, and PMS is
asserted.
2. RD or WR is asserted.
3. Within a specified time, data is placed on the data
bus, multiplexed to the internal PMD bus.
4. The data is read or written and RD (or WR ) is
deasserted.
5. PMS is deasserted