BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG

BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY

ADuC832
INSTRUCTION SET PIN FUNCTIONS

FP
SP
Q
M

C
s
1 56 P1.0 / ADC0 / T2

d
Legend

s
Arithmetic Operations

rio
pe C
te

52
51
50
49
48
47
46
45
44
43
42
41
40
S
by

O
ADD A,source 1,2 12 Rn register addressing using R0-R7 2 1 P1.1 / ADC1 / T2EX

56
55
54
53
52
51
50
49
48
47
46
45
44
43
add source to A 3 2 P1.2 / ADC2
ADD A,#data 2 12 direct 8bit internal address (00h-FFh)

G03203-2.5-9/02 (0)
1 pin 1 identifier 42
2 41 1 pin 1 identifier 39
ADDC A,source 1,2 12 @Ri indirect addressing using R0 or R1 4 3 P1.3 / ADC3 3 40
2 38
4 39
add with carry source any of [Rn, direct, @Ri] 5 4,5 AVDD
5 ADuC832 38 3 37
ADDC A,#data 2 12 ADuC832
6 37 4 36

MicroConverter®
7 56pin CSP 36
dest any of [Rn, direct, @Ri] 6 6,7,8 AGND 8
TOP VIEW 35 5 35
SUBB A,source subtract from A 1,2
with borrow
12
#data 8bit constant included in instruction
9
10
(not to scale)
34
33
6
7
52pin MQFP 34
33
7 9 CREF 11 32
TOP VIEW
Quick Reference Guide
SUBB A,#data 2 12 #data16 16bit constant included in instruction
12
13
31
30
8 32
9 31
INC A 1 12 bit 8bit direct address of bit
8 10 VREF 14 29
10 (not to scale) 30
11 29

15
16
17
18
19
20
21
22
23
24
25
26
27
28
INC source increment 1,2 12 rel signed 8bit offset 9 11 DAC0 12 28
13 27
INC DPTR * 1 24 addr11 11bit address in current 2K page 10 12 DAC1

DEC A 1 12 addr16 16bit address 11 13 P1.4 / ADC4

decrement 12 14 P1.5 / ADC5 / SS

14
15
16
17
18
19
20
21
22
23
24
25
26
DEC source 1,2 12 * INC DPTR increments the 24bit value DPP/DPH/DPL
13 15 P1.6 / ADC6
MUL AB multiply A by B 1 48 a “Data Acquisition System on a Chip”

FP

FP
s

SP

SP
d

Q
s
Logical Operations

rio
pe C
te

M
C

C
S
by
DIV AB divide A by B 1 48

O
ANL A,source 1,2 12 14 16 P1.7 / ADC7 27 29 SDATA / MOSI 40 43 EA
DA A decimal adjust 1 12 15 17 RESET 28 30 P2.0 / A8 / A16 41 44 PSEN
ANL A,#data 2 12
logical AND
ADC:
s

16 18 P3.0 / RxD 29 31 P2.1 / A9 / A17 42 45 ALE the ADuC832 is:

d

12bit, 5µs, 8channel, self calibrating

s

Data Transfer Operations ANL direct,A 2 12

rio
pe C
te

S
by

MOV A,source 1,2 12 ANL direct,#data 3 24 17 19 P3.1 / TxD 30 32 P2.2 / A10 / A18 43 46 P0.0 / AD0 0.5LSB INL & 70dB SNR
MOV A,#data 2 12 ORL A,source 1,2 12 18 20 P3.2 / INT0 31 33 P2.3 / A11 / A19 44 47 P0.1 / AD1

MOV dest,A move source 1,2 12 ORL A,#data 2 12 19 21 P3.3/INT1/MISO/PWM1 32 34 XTAL1 (in) 45 48 P0.2 / AD2 DAC: dual, 12bit, 15µs, voltage output
to destination logical OR 20 22 DVDD 33 35 XTAL2 (out) 46 49 P0.3 / AD3
1LSB DNL
MOV dest,source 1,2,3 24 ORL direct,A 2 12
21 23 DGND 34 36 DVDD 47 50 DGND
MOV dest,#data 2,3 12,24 ORL direct,#data 3 24
P3.4 / T0 / PWMC /
Flash/EEPROM: 62K bytes Flash/EE program memory
MOV DPTR,#data16 3 24 XRL A,source 1,2 12 22 24 PWM0 / EXTCLK 35 37,38 DGND 48 51 DVDD 4K bytes Flash/EE data memory
MOVC A,@A+DPTR move from 1 24 XRL A,#data 2 12 23 25 P3.5 / T1 / CONVST 36 39 P2.4 / A12 / A20 49 52 P0.4 / AD4

MOVC A,@A+PC
code memory
1 24 XRL direct,A
logical XOR
2 12 24 26 P3.6 / WR 37 40 P2.5 / A13 / A21 50 53 P0.5 / AD5 microcontroller: industry standard 8052
25 27 P3.7 / RD 38 41 P2.6/A14/A22/PWM0 51 54 P0.6 / AD6 32 I/O lines, programmable PLL clock
MOVX A,@Ri 1 24 XRL direct,#data 3 24
(131KHz to 16.8MHz from 32KHz crystal)
MOVX A,@DPTR move to/from 1 24 CLR A clear A to zero 1 12 26 28 SCLOCK 39 42 P2.7/A15/A23/PWM1 52 55 P0.7 / AD7
data memory
MOVX @Ri,A 1 24 CPL A complement A 1 12 other on-chip features: temperature sensor, power supply monitor,
MOVX @DPTR,A 1 24 RL A rotate A left 1 12
watchdog timer, flexible serial interface ports,
CODE MEMORY SPACE voltage reference, time interval counter,
PUSH direct push onto stack 2 24 RLC A ...through C 1 12 dual 8/16bit PWM, power-on-reset
POP direct pop from stack 2 24 RR A rotate A right 1 12
FFFFh FFFFh
XCH A,source exchange bytes 1,2 12 RRC A ...through C 1 12 (NOP instructions)
F800h
XCHD A,@Ri exchg low digits 1 12 SWAP A swap nibbles 1 12 F7FFh FUNCTIONAL BLOCK DIAGRAM
* pin numbers below refer to MQFP package

P3.4 (T0/PWMC/PWM0/EXTCLK)
s

P3.3 (INT1 / MISO / PWM1)

d

d
s

Program Branching Boolean Variable Manipulation

rio

rio
pe C

pe C
te

te
S

P2.6 (A14 / A22 / PWM0)

P2.7 (A15 / A23 / PWM1)
by

by
O

ACALL addr11 2 24 CLR C 1 12

P3.5 (T1 / CONVST)

P1.1 (ADC1 / T2EX)
call subroutine clear bit to zero

P1.5 (ADC5 / SS)

P1.0 (ADC0 / T2)

P2.2 (A10 / A18)

P2.3 (A11 / A19)
P2.4 (A12 / A20)
P2.5 (A13 / A21)
LCALL addr16 3 24 CLR bit 2 12

P2.0 (A8 / A16)

P2.1 (A9 / A17)
P1.2 (ADC2)
P1.3 (ADC3)
P1.4 (ADC4)

P1.6 (ADC6)
P1.7 (ADC7)
RET return from sub. 1 24 SETB C 1 12

P3.2 (INT0)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)

P3.0 (RxD)
P3.1 (TxD)
EA=1 EA=0

P3.6 (WR)
P3.7 (RD)
set bit to one
RETI return from int. 1 24 SETB bit 2 12
AJMP addr11 2 24 CPL C 1 12
internal external
complement bit code space code space

43
44
45
46
49
50
51
52

11
12
13
14

28
29
30
31
36
37
38
39

16
17
18
19
22
23
24
25
1
2
3
4
LJMP addr16 3 24 CPL bit 2 12
jump 62K bytes (64K
SJMP rel 2 24 ANL C,bit AND bit with C 2 24 hardware
Flash/EE addressable)
JMP @A+DPTR 1 24 ANL C,/bit ...NOTbit with C 2 24
CONVST 23
ADuC832
JZ rel jump if A = 0 2 24 ORL C,bit OR bit with C 2 24 ADC0 1
ADC1 2 DAC0 BUF 9 DAC0
JNZ rel jump if A not 0 2 24 ORL C,/bit ...NOTbit with C 2 24 ADC2 3 ADC
control DAC
0000h 0000h
ADC3 4 T/H 12bit ADC & control
CJNE A,direct,rel 3 24 MOV C,bit 2 12 ADC4 11 AIN calibration
move bit to bit ADC5 12 MUX
CJNE A,#data,rel compare and 3 24 MOV bit,C 2 24 ADC6 13
DAC1 BUF 10 DAC1
jump if not ADC7 14
CJNE Rn,#data,rel equal 3 24 JC rel jump if C set 2 24
INTERRUPT VECTOR ADDRESSES PWM
38 PWM0
CJNE @Ri,#data,rel 2 24 JNC rel jmp if C not set 2 24 39 PWM1
4K x 8 2K x 8
TEMP (-3 mV/oC) data
DJNZ Rn,rel decrement and 2 24 JB bit,rel jump if bit set 3 24 sensor user “XRAM”
Flash/EE 22 T0
Vector Priority
jump if not zero
DJNZ direct, rel 3 24 JNB bit,rel jmp if bit not set 3 24 Interrupt Interrupt Name within 2.5V 62K x 8
256 x 8
user RAM 16bit 23 T1
Bit Address Level bandgap program 8052 counter
1 T2
NOP no operation 1 12 JBC bit, rel jmp&clear if set 3 24 reference Flash/EE timers
MCU watchdog
core 2 T2EX
PSMCON.5 Power Supply Monitor Interrupt 43h 1 baudrate timer
timer

WDS WatchDog Timer Interrupt 5Bh 2 power supply

time
PRINTED IN U.S.A.
VREF 8 BUF downloader monitor
ASSEMBLER DIRECTIVES IE0 External Interrupt 0 03h 3
debugger interval
counter
18 INT0
19 INT1
CREF 7
ADCI End of ADC Conversion Interrupt 33h 4

single-pin
asynchronous synchronous

emulator
serial port serial interface OSC &
EQU define symbol DW store word values in program memory
TF0 Timer0 Overflow Interrupt 0Bh 5 POR (UART) (SPI or I2C) PLL
DATA define internal memory symbol ORG set segment location counter
IDATA define indirect addressing symbol END end of assembly source file IE1 External Interrupt 1 13h 6

16
17

32
33
TF1 Timer1 Overflow Interrupt 1Bh 7

20
34
48
21
35
47

15

42
41
40

26
27
19
12
XDATA define external memory symbol CSEG select program memory space

6
BIT define internal bit memory symbol XSEG select external data memory space

RxD
TxD

XTAL1
XTAL2
ISPI/I2CI SPI/I2C Interrupt 3Bh 8

RESET

ALE
PSEN
EA

SDATA / MOSI
AVDD

AGND

SCLOCK

MISO
SS
DVDD

DGND
CODE define program memory symbol DSEG select internal data memory space
DS reserve bytes of data memory ISEG select indirectly addressed internal RI/TI UART Interrupt 23h 9
DBIT reserve bits of bit memory data memory space TF2/EXF2 Timer2 Interrupt 2Bh 10
DB store byte values in program memory BSEG select bit addressable memory space TIMECON.2 Time Interval Counter Interrupt 53h 11 www.analog.com/microconverter REV. 0

BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY
BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY BIG MEMORY
SFR DESCRIPTIONS
ADCCON1 ADC Control register #1 CFG832 ADuC832 Configuration Register
DATA MEMORY: RAM, SFRs, user Flash/EE (all read/write) ADCCON1.7
ADCCON1.6
ADC mode (0=off, 1=on)
external Vref select bit (0=on-chip Vref)
CFG832.7
CFG832.6
extended stack-pointer enable (0=disable)
PWM pins select (0=P2.6/P2.7,1=P3.4/P3.3)
ADCCON1.5 conversion time = 16 / ADCclk CFG832.5 DAC output buffer bypass (0=buffer enabled)
SFR MAP & RESET VALUES ADCCON1.4
ADCCON1.3
ADCclk = 16,777,216Hz / [8,4,16,32]
acquisition time select bits
CFG832.4
CFG832.3
external clock select (0=internal clock)
(this bit must contain 0)
ADCCON1.2 acq time = [1,2,3,4] / ADCclk CFG832.2 (this bit must contain 0)
ADCCON1.1 Timer2 convert enable CFG832.1 (this bit must contain 0)
ADCCON1.0 external CONVST enable CFG832.0 internal XRAM select (0=external XRAM)

ADCCON1
00h

00h

DEh

53h

00h

00h

00h

00h

00h

00h
PSMCON

PLLCON

EDATA4
(reserved)

(reserved)

(reserved)

(reserved)
CFG832

(not used)

(not used)
ADCCON2 WDCON

DPCON
SPIDAT

EADRH
ADC Control register #2 Watchdog Timer control register

PCON
SPH
LOWER RAM
ADCI ADC interrupt flag PRE3 watchdog timeout selection bits
address

address

DMA DMA mode enable PRE2 0-7=[15.6,31.2,62.5,125,250,500,1000,2000]ms

decimal

CCONV continuous conversion enable bit PRE1 8=0ms (immediate reset)

DFh
EFh

D7h

00h C7h

00h BFh

00h AFh
B7h

00h A7h
F7h

87h
SCONV single conversion start bit PRE0 >8=reserved
HEX

CS3 input channel select bits: WDIR watchdog interrupt response bit
CS2 0 - 7 = ADC0 - ADC7 WDS watchdog status flag (1 indicates watchdog timeout)
CS1 8 = temperature sensor WDE watchdog enable control (0=disabled)

00h
PWMCON
127 7Fh CS0 9=DAC0, A=DAC1, B=AGND WDWR watchdog write enable bit (set to enable write)

EDATA3
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
(not used)

(not used)
INTVAL
EADRL

T3CON
General Purpose ADCCON3 ADC Control register #3 PSMCON Power Supply Monitor control register

address

address
... ... Area ADCCON3.7 busy indicator flag (0=ADC not active) PSMCON.6 PSM status bit (1=normal / 0=fault)

MSB

LSB
ADCCON3.6 gain calibration disable (0=gain cal enabled) PSMCON.5 PSM interrupt bit
48 30h (bit addresses) ADCCON3.5 number of averages selection bits: PSMCON.4 trip point select bits

00h BEh

AEh
C6h

00h A6h

00h 9Eh
ADCCON3.4 [15,1,31,63] PSMCON.3 [4.37V, 3.08V, 2.93V, 2.63V]
ADCCON3.3 cal clock divide select (0=ADCclk, 1=ADCclk/2) PSMCON.2 (this bit must contain zero)
47 2Fh 7Fh 7Eh 7Dh 7Ch 7Bh 7Ah 79h 78h ADCCON3.2 cal mode select (0=device, 1=system) PSMCON.1 (reserved)

ADCOFSL ADCOFSH ADCGAINL ADCGAINH ADCCON3

04h

00h

00h

00h
ADCCON3.1 cal type select (0=offset, 1=gain) PSMCON.0 PSM powerdown control (1=on / 0=off)

DACCON

EDATA2
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)
(not used)

(not used)
46 2Eh 77h 76h 75h 74h 73h 72h 71h 70h ADCCON3.0 start calibration bit, cleared by hardware
SP Stack Pointer

HOUR

T3FD
ADCDATAH

TH2

TH1
45 2Dh 6Fh 6Eh 6Dh 6Ch 6Bh 6Ah 69h 68h ADC Data registers SPH Stack Pointer High byte
ADCDATAL

00h CDh

00h BDh
00h FDh

9Dh

00h 8Dh
00h A5h
*00h F5h
44 2Ch 67h 66h 65h 64h 63h 62h 61h 60h IE Interrupt Enable register #1
DMAP,DMAH,DMAL DMA address pointer
EA enable inturrupts (0=all inturrupts disabled)
43 2Bh 5Fh 5Eh 5Dh 5Ch 5Bh 5Ah 59h 58h ADCGAINH ADC Gain
EADC enable ADCI (ADC interrupt)

00h

00h

00h
ET2 enable TF2/EXF2 (Timer2 overflow interrupt)

EDATA1
(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(not used)

(not used)
PWM1H
ADCGAINL calibration coefficients

DAC1H
ES enable RI/TI (serial port interrupt)

DMAP
42 2Ah 57h 56h 55h 54h 53h 52h 51h 50h

DPP
ET1 enable TF1 (Timer1 overflow interrupt)

TH0
MIN
TL2
EX1 enable IE1 (external interrupt 1)
ADCOFSH ADC Offset
41 29h Bit Addressable 4Fh 4Eh 4Dh 4Ch 4Bh 4Ah 49h 48h calibration coefficients
ET0 enable TF0 (Timer0 overflow interrupt)
ADCOFSL EX0 enable IE0 (external interrupt 0)

00h CCh

BCh
00h FCh
Area

00h D4h

00h 8Ch
00h B4h

00h A4h
*00h F4h

00h 84h
40 28h 47h 46h 45h 44h 43h 42h 41h 40h IEIP2 Interrupt Enable/Priority register #2
DACCON DAC Control register IEIP2.6 priority of TII interrupt (time interval)
39 27h 3Fh 3Eh 3Dh 3Ch 3Bh 3Ah 39h 38h DACCON.7 ModeSelect (0=12bit, 1=8bit) IEIP2.5 priority of PSMI interrupt (power supply monitor)

55h
RCAP2H
DACCON.6 DAC1 RangeSelect (0=VREF, 1=VDD) IEIP2.4 priority of ISPI interrupt (serial interface)

(reserved)

(reserved)

ADCCON2 ADCDATAL ADCDATAH (reserved)

(reserved)

(reserved)

(reserved)

(not used)
I2CADD
PWM1L
DAC1L

DMAH
DACCON.5 DAC0 RangeSelect (0=VREF, 1=VDD) IEIP2.3 (this bit must contain zero)
38 26h 37h 36h 35h 34h 33h 32h 31h 30h

DPH
SEC

TL1
DACCON.4 Clear DAC1 (0=0V, 1=normal operation) IEIP2.2 enable TII interrupt (time interval)
DACCON.3 Clear DAC0 (0=0V, 1=normal operation) IEIP2.1 enable PSMI (power supply monitor interrupt)
37 25h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h DACCON.2 SynchronousUpdate (1=asynchronous) IEIP2.0 enable ISPI interrupt (serial interface)

00h CBh
00h FBh

00h D3h

00h B3h

00h A3h

00h 9Bh

00h 8Bh
*20h F3h

00h 83h
DACCON.1 PowerDown DAC1 (0=off, 1=on)
DACCON.0 PowerDown DAC0 (0=off, 1=on) IP Interrupt Priority register
36 24h 27h 26h 25h 24h 23h 22g 21h 20h PSI priority of ISPI/I2CI (serial interface interrupt)
DAC1H,DAC1L DAC1 data registers PADC priority of ADCI (ADC interrupt)

2Xh
00h
35 23h 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h PT2 priority of TF2/EXF2 (Timer2 overflow interrupt)

HTHSEC
RCAP2L
(reserved)

(reserved)

(reserved)

(reserved)
DAC0H,DAC0L

(not used)
PWM0H

I2CDAT
DAC0 data registers

DAC0H

CHIPID
PS priority of RI/TI (serial port interrupt)

DMAL

DPL
PT1 priority of TF1 (Timer1 overflow interrupt)

TL0
34 22h 17h 16h 15h 14h 13h 12h 11g 10h PLLCON PLL Control register PX1 priority of IE1 (external interrupt 1)
PT0 priority of TF0 (Timer0 overflow interrupt)
PLLCON.7 oscillator powerdown control bit (0=XTAL on)

C2h
33 21h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h

00h DAh

CAh
PX0 priority of IE0 (external interrupt 0)

D2h
00h FAh

00h B2h

00h A2h

00h 9Ah

00h 8Ah
*00h F2h

07h 82h
PLLCON.6 PLL lock indicator flag (0=out of lock)
PLLCON.5 (this bit must contain zero) TMOD Timer Mode register
32 20h 07h 06h 05h 04h 03h 02h 01h 00h PLLCON.4
PLLCON.3
(this bit must contain zero)
“fast interrupt” control bit (0=normal)
TMOD.3/.7 gate control bit (0=ignore INTx)

00h

A0h
TMOD.2/.6 counter/timer select bit (0=timer)

TIMECON
PLLCON.2 3-bit clock divider value, “CD” (default=3):

(reserved)

(reserved)

(reserved)

(reserved)

(reserved)

(not used)
31 1Fh R7

PWM0L
TMOD.1/.5 timer mode selecton bits

DAC0L

TMOD
PLLCON.1

ECON
CD

SBUF
fCORE = 16,777,216Hz / 2

IEIP2
TMOD.0/.4 [13bitT, 16bitT/C, 8bitT/Creload, 2x8bitT]
PLLCON.0

SP
(upper nibble = Timer1, lower nibble = Timer0)
30 1Eh R6 TIMECON Time Interval Counter Control Register
TCON Timer Control register
Register Bank 3

00h D9h
TIMECON.6 (this bit must contain 1)

00h B9h

FFh B1h

00h A9h

FFh A1h
04h F9h

00h F1h

00h 99h

00h 89h

FFh 81h
29 1Dh R5 TIMECON.5 INTVAL timebase select bits TF1 Timer1 overflow flag (auto cleared on vector to ISR)
TIMECON.4 [128th sec, seconds, minutes, hours] TR1 Timer1 run control (0=off, 1=run)
28 1Ch R4 DATA MEMORY SPACE TIMECON.3 single time interval control bit (0=reload&restart) TF0 Timer0 overflow flag (auto cleared on vector to ISR)

00h

00h

00h

00h

10h

FFh
TIMECON.2 time interval interrupt bit, “TII” TR0 Timer0 run control (0=off, 1=run)

(read/write area)
SPICON

I2CCON
IE1 external INT1 flag (auto cleared on vector to ISR)

WDCON
T2CON
TIMECON.1 time interval enable bit (0=disable&clear)

SCON
27 1Bh R3

TCON
IT1 IE1 type (0=level trig, 1=edge trig)

PSW
ACC
TIMECON.0 time clock enable bit (0=disable)
IE0 external INT0 flag (auto cleared on vector to ISR)

P3

P2

P1

P0
IP

IE
B

26 1Ah R2 INTVAL TIC Interval Register IT0 IE0 type (0=level trig, 1=edge trig)
TH0,TL0 Timer0 registers

D8h

D0h

C8h

C0h
E8h

E0h

B8h

B0h

A8h

A0h
F8h

F0h

98h

90h

88h

80h
HTHSEC TIC Elapsed 128th Second Register
25 19h R1
SEC TIC Elapsed Seconds Register TH1,TL1 Timer1 registers
24 18h R0 3FFh ( page 1023 ) FFFFFFh MIN TIC Elapsed Minutes Register T2CON Timer2 Control register
23 17h R7 HOUR TIC Elapsed Hours Register TF2 overflow flag
EXF2 external flag
ECON Data Flash/EE comand register RCLK receive clock enable (0=Timer1 used for RxD clk)
22 16h R6
0

1
WDWR
TCLK transmit clock enable (0=Timer1 used for TxD clk)

CAP2
SPR0

01h READ page 82h PROGRAM byte

RXD
EXEN2 external enable (0=ignore T2EX, 1=cap/rld on T2EX)
CS0

PX0

EX0
I2CI

IT0
Register Bank 2

4K bytes 02h PROGRAM page 0Fh EXIT ULOAD mode

T2
RI
TR2 run control (0=stop, 1=run)

P
21 15h R5 04h VERIFY page F0h ENTER ULOAD mode
CNT2 timer/counter select (0=timer, 1=counter)
(1K pages)
D8h

D0h

C8h

C0h
E8h

E0h

B8h

B0h

A8h

A0h
05h ERASE page (all others reserved)
F8h

F0h

98h

90h

88h

80h
CAP2 capture/reload select (0=reload, 1=capture)
06h ERASE ALL
20 14h R4 data TH2,TL2 Timer2 register
EADRH,EADRL Data Flash/EE address registers
Flash/EE
0

1
19 13h R3
I2CTX
SPR1

CNT2 RCAP2H,RCAP2L Timer2 Reload/Capture

T2EX
WDE

TXD
CS1

EDATA1,EDATA2,EDATA3,EDATA4

PT0

ET0
(accessible

IE0
F1

TI
18 12h R2 through Data Flash/EE data registers P0 Port0 register (also A0-A7 & D0-D7)
D9h

D1h

C9h

C1h
E9h

E1h

B9h

B1h

A9h

A1h
F9h

F1h

99h

91h

89h

81h
17 11h R1 SFRs) SPICON SPI Control register P1 Port1 register (analog & digital inputs)
ISPI SPI inturrupt (set at end of SPI transfer)
1

1
T2EX timer/counter 2 capture/reload trigger
I2CRS
CPHA

WDS
WCOL write collision error flag

INT0
16 10h R0

RB8
T2 timer/counter 2 external input
CS2

PX1

EX1
TR2
OV

IT1
SPE SPI enable (0=I2C enable, 1=SPI enable)
7FFh SPIM master mode select (0=slave) P2 Port2 register (also A8-A15 & A16-A23)
000h
DAh

CAh

( page 0 )
EAh

BAh

AAh
15 0Fh R7
D2h

C2h
FAh

E2h

B2h

A2h

9Ah

8Ah
F2h

92h

82h
CPOL clock polarity select (0=SCLK idles low)
CPHA clock phase select (0=leading edge latch) P3 Port3 register
SPR1 SPI bitrate select bits
14 0Eh R6 RD external data memory read strobe
0

1
SPR0 bitrate = Fcore / [2,4,8,16] (slave: SPR0=SS)
EXEN2
CPOL

WR external data memory write strobe

WDIR
I2CM
Register Bank 1

INT1
CS3

RS0

TB8
SPIDAT
PT1

ET1
SPI Data register T1 timer/counter 1 external input

IE1
13 0Dh R5 T0 timer/counter 0 external input
DBh

CBh

I2CCON I2C Control register

EBh

BBh

ABh
INT1 external interrupt 1
FBh

D3h

C3h
E3h

B3h

A3h

9Bh

8Bh
F3h

93h

83h
12 0Ch R4
FFh CFG832.0=1 CFG832.0=0 MDO master mode SDATA output bit
INT0
TxD
external interrupt 0
serial port transmit data line
11 0Bh R3 128 bytes SFRs
MDE master mode SDATA output enable (0=disable) RxD serial port receive data line
CCONV SCONV
0

1
MCO master mode SCLK output bit
internal external
TCLK

PRE0
SPIM

upper RAM SCON

REN
Serial communications Control register
RS1

TR0
MDI

(direct MDI master mode SDATA input bit

PS

ES
T0

10 0Ah R2 (indirect data data I2CM master mode select bit (0=slave mode) SM0 UART mode control bits baud rate:
addressing
DCh

CCh

I2CRS serial port reset

ECh

BCh

ACh
FCh

D4h

C4h

9Ch

8Ch
E4h

B4h

A4h
SM1 00 - 8bit shift register - FOSC/12
F4h

94h

84h
addressing memory memory I2CTX transmission direction status (0=RX,1=TX) 01 - 8bit UART - variable
9 09h R1 only) I2CI serial interface interrupt 10 - 9bit UART - FOSC/64(x2)
only) I2CADD I2C Address register 11 - 9bit UART - variable
0

1
8 08h R0 2K bytes (16M bytes
RCLK

PRE1

SM2 in modes 2&3, enables multiprocessor communication

MCO

SM2
SPE

PT2

ET2

TF0
REN receive enable control bit
F0

T1

128 bytes addressable) I2CDAT I2C Data register TB8 in modes 2&3, 9th bit transmitted
7 07h R7
DDh

CDh
EDh

BDh

ADh
FDh

D5h

C5h

9Dh

8Dh
E5h

B5h

A5h
F5h

95h

85h
RB8 in modes 2&3, 9th bit received
lower RAM PWMCON PWM Control register TI transmit interrupt flag
6 06h R6 (direct or PWMCON.6 PWM mode bits [0=disabled, 1=single/var.res., RI receive interrupt flag
0

1
PWMCON.5 2=twin/8bit, 3=twin/16bit, 4=dual/16bitNRZ, SBUF
WCOL

Serial port Buffer register

Register Bank 0

indirect
EADC
PADC
PRE2
EXF2
DMA
MDE

5 05h R5
SM1

PWMCON.4 5=dual/8bit, 6=dual/16bitRZ, 7=(reserved)]

TR1
WR
AC

00h addressing) 000h

PWMCON.3 PWM clock divide bits
PWMCON.2 PWM counter = clock / [1,4,16,64] PCON Power Control register
DEh

CEh
EEh

BEh

AEh

4 04h R4
FEh

D6h

C6h
E6h

B6h

A6h

9Eh

8Eh
F6h

96h

86h
PWMCON.1 PWM clock source bits [1=FXTAL/15, 2=FXTAL, PCON.7 double baud rate control
PWMCON.0 3=T0 ext.int.rate, 4=FVCO(16.777MHz)] PCON.4 ALE disable (0=normal, 1=forces ALE high)
3 03h R3 PWM0H,PWM0L PWM0 data registers PCON.3 general purpose flag
0

1
PCON.2 general purpose flag
PRE3
ADCI
MDO

SM0
ISPI

TF2

TF1

PCON.1 power-down control bit (recoverable with hard reset)

PSI

RD
CY

EA

2 02h R2 PWM1H,PWM1L PWM1 data registers PCON.0 idle-mode control (recoverable with enabled interrupt)
DFh

CFh

PSW
EFh

D7h

C7h

BFh

AFh
FFh

E7h

B7h

A7h
F7h

9Fh

8Fh

Program Status Word

97h

87h

1 01h R1 DPCON Data Pointer Control register

CY carry flag
DPCON.6 data pointer auto-toggle enable (0=disable)
AC auxiliary carry flag
0 00h R0 DPCON.5 shadow data pointer mode control bits
F0 general purpose flag 0
DPCON.4 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
these bits are contained in this byte
MAP KEY

RS1 register bank select control bits

DPCON.3 main data pointer mode control bits
RS0 active register bank = [0,1,2,3]
DPCON.2 [1=8052, 2=post-inc, 3=post-dec, 4=LSBtgl]
mnemonic mnemonic DPCON.1 (not implemented to allow INC DPCON toggling)
OV overflow flag
SPR1 SPR0 SPICON DPCON.0 data pointer select [0=main, 1=shadow]
F1
P
general purpose flag 1
parity of ACC
address F9h 0 F8h 0 F8h 04h reset value T3CON Timer 3 Control register DPP Data Pointer Page
lower RAM
details SFR details reset value address
T3CON.7
T3CON.2
Timer 3 baud rate enable (0=disable)
binary divide factor (DIV) DPH,DPL (DPTR) Data Pointer
T3CON.1 DIV = log[FCORE/(32·baudrate)] / log2
T3CON.0 (rounded down)
* calibration coefficients are preconfigured at power-up to factory calibrated values ACC Accumulator
T3FD Timer 3 Fractional Divider register
T3FD = (2·FCORE) / (baudrate·2DIV) - 64
B auxiliary math register

CHIPID Chip ID Register (2X hex = ADuC832)

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