(Please write your Exam Roll No.) Exam Rot Wo OB 2N2NEO 6 END-TERM EXAMINATION ‘Tutno Sentesren [B.Tech] DecentpeR-2007 ~ Subject: Analog Electronics |x (Batch:2004-2008) Maximum Marks? 75 isory and attempt one question from each unit. Define zener break down and avalanche break down and compare them. 6) Explain the formation of potential barrier in a p-n junction diode. Derive an expression for contact potential 6) What is early effect? Explain base width modulation 6) List the four feed back amplifier topologies for each ofthe four topologies identify Aand8. (8) Derive the relation between Vos and V, of @ JFET. ©. yNir-1 A sinusoidal voltage having and amplitude of 3OV.is applied. Calcula(a) peak de and rms Values of oad cufentib) dc and rms output voltage? Ye) ge output powe? Tags input power (e) a2 @ A bridge rectifier uses Ri = 2.4 kM. each diode is idealized to have ore R, rectifications efficiency n and (f) percentage regulation. Derive necessary equation. ” NS Obtain the votage transfor characters for the cioul shown in fy assuming thatthe diodes are identical and have V; =0.6V and Ry = 0. Vit) = V sinat 65) Iska . Ute. Vole? Ane) Sk Fy FS 3 (@) __An-nutype Si bar is 2 cm long and.has a cross-section of 2mm X 2mm. When IV battery is sh go 5 geet Pan bate G4 Oueae teymncing Gesamte are ance Cote acerca ae ances capacitance, (8) 4 24 Ya = 008 vee = 0.7 rd te creut Sown nf 2 fr = 244 Neat reve ‘saturation current. (4) ey Write the Ebers-Moll equation fora transistor. Draw the Ebere-Moll fr transistor and explain. (3) N&, Define tree different stabil factors. Explain how stably Is improved na voltage diver bias cireuit (65) oR (2) Drawtheciruit of Darington pair and derive the equation forinput impedance my (©) Determine AV and 8 ofthe creut shown i Fig 3. erve the necessary equations ws)of @ © i as @ (a) © © laa ©) Draw the frequency response of an Re coupled amplifier and expiain 65) OR \Wrte down the advantages of negative feed back amplifier and justly your answer. “6 9 =60,re= 1.1 KA, Determine AV, Rif and Rof ofthe cut shown in 9.5 ea) Vee Rs L ke Bowe pe Vee + ft Vo Rs | Fig.5 = INITIV. 5 ‘Sketch the small signal model for a common Drain FET and derive the equation for votlage oa. 6 Find the voltage gain ofthe circuit shown in fig. 6 FET parameters ae = 30,rd5K2. (68) oo R sok Slokn + 4 Vo Fig.6 v OR @ ® Draw and explain VI characteristics of SCR. Draw the diagram giving basic stricture of UJT. Explain the working of UT. For a SCR, the gate-cathode characteristics has a straight line slope of 150. For trigger source voltage of 20Vand allowable gate power dissipation of O.SW, compute the gate source (5.5) resistance,