LIST OF EXPERIMENTS AS PER VTU SYLLABUS

1. Wiring of RC coupled Single stage FET & BJT amplifier and determination of the gain, Frequency response, input and out put impedances. 2. Wiring of BJT Darlington Emitter follower with and without bootstrapping and Determination of the gain, input and output impedances (Single circuit) (One Experiment). 3. Wiring of a two stage BJT Voltage series feed back amplifier and determination of the Gain, frequency response, input and output impedances with and without feedback (One Experiment). 4. Wiring and Testing for the performance of BJT-RC Phase shift Oscillator for f0 <= 10 KHz 5. Testing for the performance of BJT-Hartley & Colpitts Oscillators for RF range f0>=100 KHz. 6. Testing for the performance of BJT -Crystal Oscillator for f0 > 100 KHz. 7. Diode clipping (Single/Double ended) circuits for peak clipping, peak detection 8. Testing of Clamping circuits: positive clamping /negative clamping. 9. Testing of a transformer less Class - B push pull power amplifier and determination of its Conversion efficiency. 10. Testing of Half wave, Full wave and Bridge Rectifier circuits with and without Capacitor Filter. Determination of ripple factor, regulation and efficiency. 11. Verification of Thevinins Theorem and Maximum Power Transfer theorem for DC Circuits. 12. Characteristics of Series and Parallel resonant circuits.

CYCLE OF EXPERIMENTS

CYCLE - I 1. Testing of diode clipping circuits for single ended positive & negative clipping (Series /Parallel). a) Peak clipping. b) Peak voltage detection a) Testing of Double ended clipping: i) Symmetric. ii) Clipping at two independent levels. b) Testing of clamping circuits: i) Positive clamping. ii) Negative clamping Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for a Half wave rectifier with and without filter. Verification of Thevinins Theorem and Maximum Power Transfer theorem for DC circuits. CYCLE - II 5. 6. 7. 8 9 Wiring of RC coupled single stage amplifier & determine the gain, frequency response, input & output impedances (With BJT or FET) Testing of Rectifier circuit : determine ripple factor, regulation, efficiency for Full wave center tapped rectifier with and without filter Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for Full wave bridge rectifier with and without filter. Wiring of BJT Darlington Emitter follower & determine the gain, input & output impedances without bootstrapping Wiring of BJT Darlington Emitter follower & determine the gain, input & output impedances With bootstrapping CYCLE - III 10 11. Characteristics of resonant circuits :-> a) Series resonant. b) Parallel resonant Wiring & testing for the performance of BJT-RC phase shift oscillator for range f0 <= 10kHz

2. 3. 4.

12.

Wiring & testing for the performance of Oscillator for RF oscillator for RF range f0 >= 100kHz. a) Hartley oscillator. b) Colpitts oscillator. Testing for the performance of BJT crystal oscillator for f0 > 100kHz.

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CYCLE - IV 14 Wiring of a two stage BJT voltage series feedback amplifier and determine the gain, frequency response, input & output impedances .a) With the Feedback. b) without the feedback. Testing of a transformer less Class B push pull amplifier and determine its conversion efficiency.

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EXPERIMENT: 1 DIODE CLIPPING CIRCUITS AIM: Testing of diode clipping circuits for single ended positive & negative clipping (Series /Parallel (Shunt)). a) Peak clipping. b) Peak voltage detection APPARATUS REQUIRED: Power supply (0- 30V), Signal Generator, CRO, Diode: BY127/IN4007 and resistor (10k). THEORY: Clippers are networks that employ diodes to clip away portions of an input signal without distorting the remaining part of the applied waveform. These clipper circuits transfer a selected portion of the input waveform to the output. Diode clipping circuits are used to prevent a wave form from exceeding some particular limit either negative or positive or both. This is achieved by connecting the diode in serial or in parallel circuit. Variable DC voltage is connected in the circuit to achieve required level of clipping. By using different level DC voltages, it is possible to get different level of clipping in positive and negative side. These clipper circuits are also called as limiters. Following are few types of clipper circuits 1. Single ended (positive or negative ) and double ended clipping 2. Series or parallel based on the construction. a) PEAK CLIPPING CIRCUIT (DIODE SHUNT CLIPPING) Case 1: Positive peak Clipper Circuit diagram Input and output waveform Transfer characteristics

Case 2: Negative peak clipper Circuit diagram

Input and output waveform

Transfer characteristics

DESIGN: For case 1, Let the output voltage be clipped to say +3V, Vo (Max) = +3V. Vo (Max)=Vref +Vf, Where Vf=Knee voltage for silicon diode is 0.6V Therefore Vref= Vo (Max) Vf =2.4v. The value of resistor(R) is chosen for all cases as,R =(Rf x Rr) Where Rf = diode forward resistance, 10 ohms, Rr = 10M, internal resistance of diode : . R = (10x 10 x106 ) =10 k. Note: For Case 2 only the sign of the Vref changes i.e.Vref= - 2.4v. Let the output voltage be clipped to say -3V, Vo (Min) = -3V. Vo (Min) = -Vref -Vf, PROCEDURE: 1. Switch on the signal generator and measure the voltage of 10V p-p sine wave with frequency 1 kHz using CRO. 2. Rig up the circuit as shown in the diagram 3. Connect input from signal generator and output should be connected to CRO (select DC knob) 4. Compare input & output wave form for the designed value of clipping and draw it on the tracing sheet. 5. To get the transfer characteristics: Connect the input wave to X-channel & output wave to the Y-channel ,then select X-Y mode on the CRO,take the same on the tracing sheet.

b) PEAK VOLTAGE DETECTION (DIODE SHUNT DETECTION) Case 1: Positive peak detection Circuit diagram Input and output waveform Transfer characteristics

Case 2: Negative peak detection Circuit diagram Input and output waveform Transfer characteristics

Note: Design and Procedure is same as previous

RESULT: The clipper circuits are tested for out put wave form and transfer characteristics are matching with the expected ones with respect to the designed value of clipping for different cases.

(Signature of the Staff with Date)

EXPERIMENT: 2 DIODE CLIPPING & CLAMPING CIRCUITS AIM: a) Testing of Double ended clipping: i) Symmetric. ii) Clipping at two independent levels. b) Testing of clamping circuits:-Positive clamping & Negative clamping. APPARATUS REQUIRED: Power supply (0- 30V), Signal Generator, CRO, diode: BY127/IN4007, resistor of 10k and capacitor of 1F. THEORY (for clamping) :- Clamper is a circuit that "shifts" a signal to a different dc level without changing the appearance of the applied signal The different types of clampers are positive negative and biased clampers A clamping network must have a capacitor, a diode and a resistive element. The magnitude R and C must be chosen such that the time constant RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval the diode is non- conducting. By connecting suitable DC voltage in series with the diode, the level of swing can be varied. CIRCUIT DIAGRAM: a) DOUBLE ENDED CLIPPING Case i) Symmetric Circuit diagram Input and output waveform Transfer characteristics

DESIGN: Let the output voltage be clipped to say +/-3V,i.e.Vo (Max) = +3V & Vo (Min) = -3V.. Vo (Max)=Vref1 +Vf, Where Vf=Knee voltage for silicon diode is 0.6V Therefore Vref1= Vo (Max) Vf = +2.4v. Vo (Min) = -Vref2-Vf,, Vref2= - 2.4v The value of resistor(R) is chosen for all cases as,R =(Rf x Rr) Where Rf = diode forward resistance, 10 ohms, Rr = 10M, internal resistance of diode : . R = (10x 10 x106 ) =10 k.

Case ii) Clipping at two independent levels Circuit diagram Input and output waveform Transfer characteristics

DESIGN: Let the output voltage be clipped to say +4v and +2v, i.e.Vo (Max) = +4V , Vo (Min) = +2V Vo (Max)=Vref1 +Vf, Where Vf=Knee voltage for silicon diode is 0.6V Therefore Vref1= Vo (Max) Vf = 3.4v To find Vref2: Vo (Min) = Vref2 -Vf :. Vref2=2.6 v Note: Procedure for both cases is similar as experiment 1. FOR EXERCISE: Circuit diagram Input and output waveform Transfer characteristics

b) CLAMPING CIRCUITS Case i) Positive clamping Circuit diagram Input and output waveform

DESIGN: Suppose if the output has to clamp for Vo=+3V Then Vo =Vref Vf, where Vf is knee voltage = 0.6 for silicon diode Vref=3.6v Case ii) Negative clamping Circuit diagram Input and output waveform

DESIGN: Suppose if the output has to clamp for Vo= -3V From the circuit, Vo = Vref + Vf, where Vf is knee voltage = 0.6 for silicon diode Then, Vref= -3.6v PROCEDURE :( same for both cases) 1. Switch on the signal generator and measure the voltage of 10V p-p sine wave with frequency 1 kHz using CRO. 2. Rig up the circuit as shown in the diagram 3. Connect input from signal generator and output should be connected to CRO (select DC knob) 4. Compare input & output wave form for the designed value of clamping and draw it on the tracing sheet. RESULT: The theoretical design values are matching to practical waveforms

(Signature of the Staff with Date) 9

EXPERIMENT: 3 HALFWAVE RECTIFIER CIRCUIT AIM: Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for a Half wave rectifier with and without filter.
APPARATUS REQUIRED: Transformer (TR: 12-0-12), Voltmeter (0 to 25V), Ammeter (0 to 100mA), Resistors, CRO, Diode (BY 127) and capacitor. THEORY: Rectifier is a device which converts Ac signal to DC signal. There are three types:

Half wave rectifier, Fullwave rectifier with centre tap transformer and Fall wave bridge rectifier. In half- wave rectification, the rectifier or diode conducts current only during the positive/negative half cycles of the ac input supply, thus the diode acts as a switch and the source voltage appears across the load resistor. Therefore current always flows in one direction in a half wave rectifier. The half wave rectifier with filter can be used for Peak detection. CIRCUIT DIAGRAM :

Input and output waveform

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DESIGN: Vin(ac) = rms value of input(secondary of the transformer), Vo(dc) = Average value of dc output Vo(ac) = rms value of ac component of the output voltage Ripple factor, r = rms value of ac component / Value of dc component = Vo(ac)/Vo(dc) % Efficiency = output power /Input power =Idc2 * 100 /( Iac2+ Idc2)) % Regulation = [(Vnl Vfl)/Vfl]*100 Find Vin (ac) (Transformer secondary voltage) Let Vo(dc) = 5V dc Vm = Vo(dc) x = 15.7V Vin(ac rms) = Vm/2 = 15.7/2 =11.1V Use 12v-0-12v transformer( Connect two end terminals of transformer secondary) Let Idc =100mA So RL =5V/100mA =50 /5 Watts With Filter: Vdc = Vm - Vr(p-p)/2 Let Ripple factor, r = 0.2456 r = 1 / (2 x3 f x RL x C) C = 1/ (2 x3 f x RL x r) =1/ (2 x3 x 50 x 50x 0.2456) = 470 F TABULAR COLUMN: With out C-filter Vnl = V (With load RL removed), Vfl = V (With load RL at maximum) (If requires, reduce RL to limit Idc to 100mA)

% Regulation = Ripple = Vo(ac)/Vo(dc) Efficiency =

Idc2 / ( Iac2 + Idc2)

(RL+DRB) 50 +20 50 +40

Iac(mA)

Idc(mA)

Vo(dc)

Vo(ac )

11

With C-filter (RL+DRB) (50 + 0 ) Ripple = Vo(ac)/Vo(dc) Efficiency =

Idc2 / ( Iac2 + Idc2)

Iac(mA)

Idc(mA) Vo(dc)

Vo(ac )

PROCEDURE: 1. Rig up the circuit as shown in the diagram 2. Switch on the input ac signal and connect the output to CRO, take the same on the tracing sheet 3. Note down readings as in the tabular column for different values of output resistor (RL) and find out ripple factor and efficiency. 4. To calculate load regulation, put the designed value of RL=50 ,note down the output DC voltage i.e.Vfl.Then open the load resistance (RL & DRB) ,note down the output DC voltage i.e.Vnl,now we can calculate regulation using the formula % Regulation = [(Vnl Vfl)/Vfl]*100 5. Repeat the steps 1,2 & 3 by connecting the suitable capacitor across the load and a separate tabular column should be maintained.

RESULT: Parameter Ripple Factor Regulation Efficiency Theoretical value With C Without C 0.2456 1.21 40.6 Practical value With C Without C

(Signature of the Staff with Date)

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EXPERIMENT: 4 THEVININS THEOREM & MAXIMUM POWER TRANSFER THEOREM AIM: Verification of Thevinins Theorem and Maximum Power Transfer theorem for DC circuits. APPARATUS REQUIRED: DC Power Supply (0to 30V), resistors, ammeter and voltmeter. THEORY: Any combination of batteries and resistances with two terminals can be replaced by a single voltage source V and a single series resistor R. The value of V is the open circuit voltage at the terminals, and the value of R is V divided by the current with the terminals short circuited. The Thevenins voltage is the open circuit voltage at output terminal with load disconnected. The Thevenins resistance is the resistance seen at output terminal when all the voltage sources are replaced by short and current sources are replaced by open circuit. Maximum power transfer theorem is used to find the value of the load resistance for which there would be maximum amount of power transfer from source to load. A resistance load, being connected to a DC network, receives maximum power when the load resistance is equal to the internal resistance (Thevenins equivalent resistance) of the source network as seen from the load terminals. a) THEVININS THEOREM CIRCUIT DIAGRAM: Figure 1: T-network

Figure 2:

Figure 3:

Vth = volts and Rth = Parameter Initial value Final value Vdc Idc

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PROCEDURE: 1. Connect circuit as shown in the figure 1, set the DC voltage to10v by measuring through multimeter. 2. Note the initial values of Vdc & Idc from figure 1. 3. Note down the value of Vdc by removing RL from figure 1,that is the value of Vth. 4. Connect the circuit as in figure 2, note down the value of Vdc and Idc.calculate the value of Rth=Vdc/Idc. 5. Connect the circuit as in figure 3, note down the value of Vdc and Idc.these values should match the initial values of Vdc & Idc. EXERCISE: Conduct same experiment for and lattice networks. (Above procedure holds good for any type of networks) b) MAXIMUM POWER TRANSFER THEOREM CIRCUIT DIAGRAM IDEAL GRAPH:

TABULAR COLUMN: RL() 500 800 1000 1300 1500 1800 2000 2500 Ic(mA) P= RL x Idc2(mW)

PROCEDURE: 1. Connect components as shown in the diagram and set the input voltage to 5v. 2. Vary the RL (DRB) from 500 to 2000 in steps of 100 and note down the values of Idc. 3. Plot the graph of Power v/s RL and indicate the point at which the maximum power transferred at RL=R (source resistance) on the graph. RESULT: Hence the Thevinins and maximum power transfer theorem is proved.

(Signature of the Staff with Date)

14

EXPERIMENT: 5 RC COUPLED AMPLIFIER AIM: Wiring of RC coupled single stage amplifier & determine the gain, frequency response, - input & output impedances (With BJT or FET). COMPONENTS REQUIRED: NPN transistor (SL100), Resistors, Capacitors, Signal generator,
DC power supply (0-30v) and CRO.

THEORY: In RC coupled amplifier the input capacitor is used to couple the input signal to the base of first transistor. Since the coupling from one stage to next stage can be achieved by a coupling capacitor followed by a connection to a shunt resistor such amplifiers are called resistance capacitance (RC) coupled amplifiers. When an ac signal is applied to the input of the first stage it is amplified with a phase reversal by the transistor. The frequency response is a graph of the gain (in decibels) versus the frequency (in logarithmic scale). This characteristic can be subdivided into low, medium and high frequency regions. In the low frequency range, the gain drops due to increasing reactance of coupling capacitor, source capacitance and emitter capacitor. As the frequency increases, the capacitive reactance reduces and the gain increases. After this if the frequency is increased further, i.e. in the high frequency range, the gain drops due to the increased flow of the a.c signal through CE. To fix the boundaries of frequency where the gain is relatively high and constant, 0.707Amid is chosen to be the voltage gain at the cut-off levels. The corresponding frequencies f1 and f2 are generally called the corner, cut-off, band, break or half power frequencies. The multiplier 0.707 is chosen because at this level the output power is half the mid-band power output. This is illustrated in the Ideal graph. CIRCUIT DIAGRAM:

15

DESIGN: Let Vcc=12 V,Ic=4.5 mA, =100(SL 100) To find RE :

Choose VE=Vcc/10=12/10 =1.2 V VE=Ie* RE =1.2 V RE =1.2/Ic=1.2/4.5m =0.267 K

To find RC:
Choose Vce=Vcc/2 =12/2=6 V Apply KVL in CE loop: Vcc-(IcRc)- Vce- Vre=0 12-(4.5Rc)-6-1.2=0 Rc=1.07 K Rc =1 K

To find R1 & R2:

VB=Vbe+VE=0.7+1.2=1.9v Ib=Ic/ =0.045mA Assume 10Ib flows thro` R1 & 9Ib flows thro` R2 Then R1=(Vcc-VB)/10Ib=22K and R2=VB/9Ib=4.7 K

RE =270

To find Bypass cap. CE:

Let Xce= RE /10, at f=100 Hz; 1/2*f* CE= RE /10 Therefore,CE=10/2*100*270=59 F micro farad Choose CE =47F (electrolytic)

To find Cc1 and CC2: assume CC1 & CC2= 0.1 F

To design: Xcc1 = (Hie||Rb)/10, Xcc1 =1/ (2*f*Cc1), Cc1=? Xcc2 = (Rc||Rl)/10, Xcc2 =1/ (2*f*Cc2), Cc2=?

TABULAR COLUMN: Vi (P-P) = Frequency (Hz) 100 200 400 500 800 1K 2K 5K 10K 20K 50K 100K 200K 500K 700K 900K 1M Output Voltage(Vo) (P-P) (Volts) volts

Voltage Gain= Vo / Vi

Gain =20 log (Vo / Vi) dB

16

PROCEDURE: 1. Connect the circuit as shown above without applying Vin, check the DC voltage conditions Vce =6v and Vbe =0.6v as designed, by applying Vcc=12v. 2. Measure the sine wave signal of amplitude 20 mV from signal generator using CRO and apply to the circuit. 3. Vary the input sine wave frequency from 100 Hz to 1 MHz in suitable steps. Note down output voltage amplitude at each step using CRO. 4. Caluculate the gain in decibels (dBs),Plot Gain in dB versus frequency on the semi log graph, determine Bandwidth and G.B.W product from the plot.

IDEAL GRAPH (FREQUENCY RESPONSE):

TO FIND INPUT RESISTANCE:

PROCEDURE: 1. Connect a DRB(value should be Zero) in series for the existing RC coupled amplifier circuit as shown above. 2. Put the frequency of the input in midband (around 10kHz),keeping Vin same(20mV),note down the value of output voltage. 3. Increase the value of DRB linearly such that the output voltage should be half of its initial value, the current value of DRB is the Input Resistance.

17

TO FIND OUTPUT RESISTANCE:

PROCEDURE: 1. Connect a DRB (value should be maximum) in parallel for the existing RC coupled amplifier circuit as shown above. 2. Put the frequency of the input in midband (around 10 kHz), keeping Vin same (20mV), note down the value of output voltage. 3. Decrease the value of DRB linearly such that the output voltage should be half of its initial value, the current value of DRB is the output Resistance. RESULT: Thus the RC Coupled Amplifier has following features. Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance value

(Signature of the Staff with Date)

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EXPERIMENT: 6 FULL WAVE CENTER TAPPED RECTIFIER AIM: Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for Full wave center tapped rectifier with and without filter. APPARATUS REQUIRED: Transformer (TR: 12-0-12), Voltmeter (0 to 25V), Ammeter (0 to 100mA), Resistors, CRO, Diodes (BY 127) and capacitor. THEORY: A full wave rectifier is equivalent to two half wave rectifiers. Because of the center tapping, each of these rectifiers has an input voltage equal to half the secondary voltage. Diode D1 conducts in the positive half cycle and D2 conducts in the negative half cycle. As a result, the rectified load current flows during both the half cycles.
CIRCUIT DIAGRAM:

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DESIGN: Vin(ac) = rms value of input,

Vo(dc) = Average value of input

Vo(ac) = rms value of ac component of the output voltage Ripple factor, r = rms value of ac component / Value of dc component = Vo(ac)/Vo(dc) % Efficiency = output power /Input power =Idc2 * 100 /( Iac2+ Idc2)) x100 % Regulation = [(Vnl Vfl)/Vfl]*100 Find Vin (ac) (Transformer secondary voltage) Let Vo(dc) = 10V dc Vm = Vo(dc) x /2 = 15.7V Vin(rms) = Vm/2 = 15.7/2 =11.1V(12v-0-12v) ( For center tap circuit , connect two end terminals of transformer secondary to anode of the two diodes and consider center tap as ground potential. Let Idc =100mA Then RL =10V/100mA =100 /10 watts With Filter : Vdc=Vm-Vr(p-p)/2 Let Ripple factor, r = 0.0615 r = 1 / (4 x3 f x RL x C) C = 1/ (4 x3 f x RL x r) =1/ (4 x3 x 50 x 100x 0.0615) = 470 F TABULAR COLUMN: With out C-filter Vnl = V ( With load RL removed ), Vfl = V ( With load RL at maximum)

% Regulation = Ripple = Vo(ac)/Vo(dc) Efficiency =

Idc2 / ( Iac2 + Idc2)

(RL+DRB) 100 + 20 100 + 40

Iac(mA)

Idc(mA)

Vo(dc)

Vo(ac )

20

With C-filter Ripple = Vo(ac)/Vo(dc) Efficiency =

Idc2 / ( Iac2 + Idc2)

(RL+DRB) ( 100 + 0)

Iac(mA)

Idc(mA)

Vo(dc)

Vo(ac )

PROCEDURE: 1. Rig up the circuit as shown in the diagram 2. Switch on the input ac signal and connect the output to CRO, take the same on the tracing sheet 3. Note down readings as in the tabular column for different values of output resistor (RL) and find out ripple factor and efficiency. 4. To calculate load regulation, put the designed value of RL=100 ,note down the output DC voltage i.e.Vfl.Then open the load resistance (RL & DRB) ,note down the output DC voltage i.e.Vnl,now we can calculate regulation using the formula % Regulation = [(Vnl Vfl)/Vfl]*100 5. Repeat the steps 1,2 & 3 by connecting the suitable capacitor across the load and a separate tabular column should be maintained. RESULT: Parameter Ripple Factor Regulation Efficiency Theoretical value With C Without C 0.0615 0.483 81.2 Practical value With C Without C

(Signature of the Staff with Date)

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EXPERIMENT: 7 FULL WAVE BRIDGE RECTIFIER AIM: Testing of Rectifier circuit: determine ripple factor, regulation, efficiency for Full wave bridge rectifier with and without filter. APPARATUS REQUIRED: Transformer (TR: 12-0-12), Voltmeter (0 to 25V), Ammeter (0 to 100mA), Resistors, CRO, Diodes (BY 127) and capacitor. THEORY: The bridge rectifier is similar to a full wave rectifier because it produces a full wave output voltage. Diodes D1 and D3 conduct on the positive half cycle and D2 and D4 conduct on the negative half cycle. As a result, the rectified load current flows between both half cycles in one direction. The advantage is the PIV of diodes is Vm, instead of 2Vm in Full wave rectifier with center tap transformer. The disadvantage is it uses four diodes.
CIRCUIT DIAGRAM:

Note: The design, procedure and out put waveform is similar to Experiment 6, i.e.except circuit diagram everything is same. TABULAR COLUMN: With out C-filter Vnl = V ( With load RL removed ), Vfl = V ( With load RL at maximum)

% Regulation = Ripple = Vo(ac)/Vo(dc) Efficiency =

Idc2 / ( Iac2 + Idc2)

(RL+DRB) 100 + 20 100 + 40

Iac(mA)

Idc(mA)

Vo(dc)

Vo(ac )

22

With C-filter Ripple = Vo(ac)/Vo(dc) Efficiency =

Idc2 / ( Iac2 + Idc2)

(RL+DRB) 100 + 0

Iac(mA)

Idc(mA)

Vo(dc)

Vo(ac )

RESULT: Parameter Ripple Factor Regulation Efficiency Theoretical value With C Without C 0.0615 0.483 81.2 Practical value With C Without C

(Signature of the Staff with Date)

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EXPERIMENT: 8 DARLINGTON EMITTER FOLLOWER WITHOUT BOOTSTRAP AIM: Wiring of BJT Darlington Emitter follower & determine the gain, input & output impedances without bootstrapping. COMPONENTS REQUIRED: Transistors (SL100), Resistors, Capacitors, DC power supply, CRO and signal generator. THEORY: The circuit diagram shows the direct coupling of two stage emitter follower. In order to improve the values of the circuit current gain and input impedance this cascaded arrangement is done. Actually the connection of one more stage should increase the input impedance and the current gain. But unfortunately this is not possible because the leakage current is high which is not desired. Therefore the result is that the emitter current of the first transistor is the base current of the second transistor. The current gain of the pair is equal to the product of individual current gains
CIRCUIT DIAGRAM:

DESIGN:

Let Vcc =12 V ,Vce = 3V, IeQ=5mA (Q point of transistor Q2), Ie = Ic = 5 mA VRe = Vcc - Vce= 12 3 = 9V Re= VR3 / Ie = 9V / (5 mA) = 1800 (use 2.2k) VCC = VR1 +VR2 ,let VR1 = VR2=6v, i.e. same (approximately) current flows through R1 & R2. Using emperical relations: IR1=IR2=Ic/85 R1=R2=6v/60A=100k To find Cc: XcC 0.2 Ri (Ri = R1|| R2 || hie = hie) Choose Ri = 1.5 K and f = 1KHz. 1 2 f CE x 0.1 R i; Cc 1 / 2 f x 0.1 Ri = 1/(2 x 3.14 x 1000 x 0.2 x 1500) = 0.53F(use 0.47 F)

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PROCEDURE: 1. Connect the circuit as shown above 2. Measure the sine wave signal of amplitude 1V peak to peak from signal generator using CRO and apply to the circuit. 3. Vary the input sine wave frequency from 1 Hz to 1 MHz in suitable steps. Note down output voltage amplitude at each step using CRO. 4. Calculate the gain in decibels (dBs), Plot Gain in dB versus frequency on the semi log graph, determine Bandwidth and G.B.W product from the plot. TABULAR COLUMN: Vi (P-P) = Frequency (Hz) 1 3 5 8 100 200 400 500 800 1K 10K 100K 200K 500K 700K 900K 1M IDEAL GRAPH (FREQUENCY RESPONSE): Output Voltage(Vo) (P-P) (Volts) volts

Voltage Gain= Vo / Vi

Gain =20 log (Vo / Vi) dB

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TO FIND INPUT RESISTANCE:

PROCEDURE: 1. Connect a DRB(value should be Zero) in series for the existing Darlington Emitter follower circuit as shown above. 2. Put the frequency of the input in midband (around 10 kHz),keeping Vin same(1V),note down the value of output voltage. 3. Increase the value of DRB linearly such that the output voltage should be half of its initial value, the current value of DRB is the Input Resistance. TO FIND OUTPUT RESISTANCE:

PROCEDURE: 1. Connect a DRB (value should be maximum) in parallel for the existing Darlington Emitter follower circuit as shown above. 2. Put the frequency of the input in midband (around 10 kHz), keeping Vin same (1V),note down the value of output voltage. 3. Decrease the value of DRB linearly such that the output voltage should be half of its initial value, the current value of DRB is the output Resistance. RESULT: Thus the Darlington Emitter follower without bootstrap has following features. Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance
value

(Signature of the Staff with Date)

26

EXPERIMENT: 9 DARLINGTON EMITTER FOLLOWER WITH BOOTSTRAP AIM: Wiring of BJT Darlington Emitter follower & determine the gain, input & output impedances with bootstrapping.

COMPONENTS REQUIRED: Transistors (SL100), Resistors, Capacitors, DC power supply, CRO and signal generator.

CIRCUIT DIAGRAM:

Note: Except circuit diagram (additional one Resistance & one Capacitor) everything is same as previous experiment.

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TABULAR COLUMN: Vi (P-P) = Frequency (Hz) 1 3 5 8 100 200 400 500 800 1K 10K 100K 200K 500K 700K 900K 1M Output Voltage(Vo) (P-P) (Volts) volts Voltage Gain= Vo / Vi

Gain =20 log (Vo / Vi) dB

RESULT: Thus the Darlington Emitter follower with bootstrap has following features.

Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance

Value

(Signature of the Staff with Date)

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EXPERIMENT: 10 RESONANT CIRCUITS AIM: To plot the frequency response and determine Resonance frequency, Band width and Q-factor of resonant circuits: a) Series resonant. b) Parallel resonant COMPONENTS REQUIRED: Signal generator, Ammeter, resistor, Capacitor or Decade Capacitance Box (DCB), Inductor or Decade inductance Box (DIB). THEORY: Resonance is a phenomenon and study of AC circuits, when an inductance coil and capacitance are connected either in series or parallel across an alternating supply of varying frequency. Resonance condition can be achieved either by keeping network elements same and varying frequency or by keeping frequency same and varying the frequency dependent circuit elements. Resonance circuits are classified into two categories: Series resonance circuit and Parallel resonance circuit. a) SERIES RESONANT CIRCUIT
CIRCUIT DIAGRAM:

IDEAL GRAPH:

c) PARALLEL RESONANT CIRCUIT

CIRCUIT DIAGRAM:

IDEAL GRAPH:

DESIGN: (same for both) Let fr=5kHz and C=0.1F We know that Resonant frequency,fr = 1/ (2LC) Then L=0.01 H, choose a current limiter R=100 .

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TABULAR COLUMN: a) Series Resonance Frequency(Hz) 500 1K 2K 4K 4.5K 5K 5.5K 6K 8K 10k PROCEDURE: (same for both) 1. Connections are made as shown in the diagram. 2. An Input of 10 Vp-p sine wave signal from signal generator is applied. 3. The Input frequency is varied from 500 Hz to 10kHz and the corresponding Iac readings are noted down in the tabular column. 4. The frequency response plot is plotted Iac v/s frequency,from the plot the resonant frequency(fo),Bandwidth(BW)=f2-f1 and Q-factor=fo/BW are calculated. Note: we can also calculate Q-factor=(Wr*L)/R.where Wr=2fr RESULT: Parameter Resonant frequency Band width Q-factor Series Resonance Parallel Resonance Iac(mA) b) Parallel Resonance Frequency(Hz) 500 1K 2K 4K 4.5K 5K 5.5K 6K 8K 10k Iac(mA)

(Signature of the Staff with Date)

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EXPERIMENT: 11 RC PHASE SHIFT OSCILLATOR AIM:Wiring & testing for the performance of BJT-RC phase shift oscillator for range f0 <= 10kHz (i.e. 2 kHz). COMPONENTS REQUIRED:NPN transistor (SL100),Resistors,Potentiometer,Capacitors, DC power supply (0-30v) and CRO. THEORY: The basic criterion to be followed by any network to get oscillations is the Barkhausen criteria: it states two conditions.1)A>=1,where A is the gain of the amplifier stage and is the gain of the feedback..2) The total phase shift should be 3600. RC phase shift Oscillator basically consists of an amplifier and feed back network consisting of resistors and capacitors in ladder fashion. The transistor (CE) amplifier provides 1800 degree phase shift and the other 1800 phase shift is provided by RC feed back network i.e. each RC network provides 600 phase shift. The major application of this oscillator is in low frequency audio range CIRCUIT DIAGRAM:

DESIGN: Given Vcc=+12 v,Ic=4mA and hfe=100 Let Ve=2v,Vce=6v. RE=Ve/(Ie orIc)=500(use 470 ) Applying KVL to CE loop Vcc-IcRc-Vce-Ve=0 Rc=( Vcc -Vce-Ve)/ Ic =1k From the circuit Vb(voltage across R2)=(VccxR2)/(R1xR2) and Vb=Vbe+Ve=2+0.7=2.7v Then by using previous equation,R1=3.44R2 If R2=6.8k, then R1=23.3k (use 22k ) Use CE = 47F, Co=0.47F, For RC-network: fo=1/(2RC(6+4K)),Let fo=2kHz and R=2.2K Where K=Rc/R=0.454, Then C= 0.01F.

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OUTPUT WAVEFORM:

PROCEDURE: 1) Connections are made as shown in the circuit diagram without connecting RC network. 2) The DC voltages Ve=2v, Vce=6v are measured using multimeter,then connect RC network. 3) The potentiometer, RL (10k pot) in the feedback path is varied till stable oscillations are observed on the CRO. 4) The output signal is traced into a tracing sheet and the frequency=(1/T)Hz of same is measured, where T is time period of the output signal.

EXERCISE: The lissageous patterns representing different phase shifts from input to output of RC network (one stage provides 600 ) can be observed on the CRO. RESULT: Parameter Frequency Theoretical value Practical value

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EXPERIMENT: 12 HARTLEY OSCILLATOR AND COLPITTS OSCILLATOR AIM: Wiring & testing for the performance of Oscillator for RF oscillator for RF range f0 >= 100 kHz: a) Hartley oscillator. b) Colpitts oscillator. COMPONENTS REQUIRED: NPN transistor (SL100), Resistors, potentiometer, Capacitors, Inductors, DC power supply (0-30v) and CRO. THEORY: In phase shift oscillator, RC circuit is used to get the oscillation whose frequency is in the audio range. To get higher frequency of oscillation, feedback circuit to have inductor and capacitors. The oscillators that employ L&C elements are called tuned oscillators.Hartley and Colpitts oscillators belong to LC tuned oscillator. A Hartley oscillator has an Potential divider biased BJT amplifier and LC feedback circuit. Its feedback or tank circuit consists of 2 inductor in series and one capacitor in parallel. Colpitts oscillator is similar to the Hartley oscillator except the change in the tank circuit. Here the tank circuit consists of 2 capacitors in series and one capacitor. The amplifier is single stage amplifier and has 1800 phase shift. So this tank circuit provides 1800 phase shift due to inductor & capacitor connection to make total phase shift of the circuit as 3600 at the frequency of oscillations.When the feedback is adjusted so that 1, sustained oscillation occurs at the output. a) HARTLEY OSCILLATOR CIRCUIT DIAGRAM:

DESIGN: The frequency of the oscillations, f 1/ 2 LC For Hartley oscillator L =L1+L2, If f=112.5 kHz and C=0.01F Then using above equation, L1= L2=100 H Note:Biasing circuit design for BJT amplifier is same for both Hartley oscillator and Colpitts oscillator.which is same as RC phase shift oscillator.i.e. RE=470, R1=22k, R2=6.8K, Rc=1K, Cc1=Cc2=0.47F, CE=47F.

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b) COLPITTS OSCILLATOR CIRCUIT DIAGRAM:

DESIGN: The frequency of the oscillations, f 1/ 2 LC For Colpitts Oscillator C= C1C2/(C1+C2) If f=100.65 kHz, L=5mH, Then by using above equation, C1=C2=1000pF. OUTPUT WAVEFORM:

PROCEDURE: (same for both Hartley oscillator and Colpitts oscillator) 1) Connections are made as shown in the circuit diagram without connecting tank circuit. 2) The DC voltages Ve=2v, Vce=6v are measured using multimeter and then connect tank circuit. 3) The potentiometer (1k pot) is varied till stable oscillations are observed on the CRO. 4) The output signal is traced into a tracing sheet and the frequency= (1/T) Hz of same is measured, where T is time period of the output signal.

RESULT: Parameter Frequency (KHz) Type Hartley Oscillator Colpitts Oscillator Theoretical value Practical value

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EXPERIMENT: 13 CRYSTAL OSCILLATOR AIM: Testing for the performance of BJT crystal oscillator for f0 > 100 kHz (2MHz). COMPONENTS REQUIRED: Crystal (2MHz), NPN transistor (SL100), Resistors, potentiometer (1K), Capacitors, DC power supply (0-30v) and CRO. THEORY: Crystal oscillators are made from quartz (piezoelectric material). A crystal can be operated in the series resonant or parallel resonant mode. In the series mode crystal offers minimum impedance at resonance and in parallel mode it offers maximum impedance and is inductive. Since the parallel resonant frequency of a crystal is slightly higher than its series resonant frequency, the method of connection is important. They are used for generating accurate, stable and fixed values of frequencies in the order of few Mega Hertz, which cannot be achieved through LC or RC circuits. CIRCUIT DIAGRAM:

Note:Biasing circuit design for BJT amplifier is same as RC phase shift oscillator.i.e. RE=470, R1=22k, R2=6.8K, Rc=1K, and use C1=300pF, C2=0.1F,CE=47F. The procedure of conduction is same as experiment 12. RESULT: Parameter Frequency Theoretical value Practical value

(Signature of the Staff with Date)

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EXPERIMENT: 14 VOLTAGE SERIES FEEDBACK AMPLIFIER AIM: Wiring of a two stage BJT voltage series feedback amplifier and determine the gain, frequency response, input & output impedances. a) Without the feedback. b) With the Feedback COMPONENTS REQUIRED: Transistors (SL100), Resistors, Capacitors, DC power supply, CRO and signal generator.
THEORY: The bipolar transistor common emitter amplifier can be used as voltage-series

feed back amplifier. In this amplifier the feed back voltage is in series with the source voltage. The proper use of negative feedback is the significant improvement in the frequency response (as in ideal graph) and in the linearity of operation of the feedback amplifier compared with that of the amplifier without feedback. The other advantage of negative feedback is it increases the input resistance and decreases the output resistance of the amplifier. The characteristics of this circuit are: Input impedance is high (M) and Output impedance is low as in the order of hundreds of ohms. a) Without the feedback CIRCUIT DIAGRAM:

DESIGN: Given Vcc=+12 v,Ic=4mA and hfe=100, Let Ve=2v,Vce=6v.

RE1= RE2=Ve/(Ie orIc)=500(use 470 ) Applying KVL to CE loop Vcc-IcRc-Vce-Ve=0 Rc1=Rc2=( Vcc -Vce-Ve)/ Ic =1k From the circuit Vb(voltage across R2)=(VccxR2)/(R1xR2) and Vb=Vbe+Ve=2+0.7=2.7v Then by using previous equation, R1=3.44R2 If R2=R4=4.7k, then R1=R3=16.18 k (use 15 k) Use CE1 = CE2=47F, Ci=Cc= Co=0.47F, Rf1=330

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Note: For with feedback the only Rf =10k will be the additional component. b) With the feedback CIRCUIT DIAGRAM:

PROCEDURE: (same for both with and without feedback) 1. Connect the circuit as shown above without applying Vin, check the DC voltage conditions Vce =6v and Vbe =0.6v as designed, by applying Vcc=12v for both stages. 2. Measure the sine wave signal of amplitude 20 mV from signal generator using CRO and apply to the circuit. 3. Vary the input sine wave frequency from 100 Hz to 1 MHz in suitable steps. Note down output voltage amplitude at each step using CRO. 4. Caluculate the gain in decibels (dBs),Plot Gain in dB versus frequency on the semi log graph, determine Bandwidth and G.B.W product from the plot.

IDEAL GRAPH:

Note: To find input and out put impedances, the procedure is same as followed in RC coupled amplifier for both with and without feedback.

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TABULAR COLUMN: a) Without the Feedback :- Vi (P-P) = Frequency (Hz) 100 200 400 500 800 1K 2K 5K 10K 20K 50K 100K 200K 500K 700K 900K 1M b) With the Feedback :- Vi (P-P) = Frequency (Hz) 100 200 400 500 800 1K 2K 5K 10K 20K 50K 100K 200K 500K 700K 900K 1M Output Voltage(Vo) (P-P) (Volts) Voltage Gain= Vo / Vi volts Output Voltage(Vo) (P-P) (Volts) Voltage Gain= Vo / Vi

volts

Gain =20 log (Vo / Vi) dB

Gain =20 log (Vo / Vi) dB

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RESULT: Thus the voltage series feedback amplifier with and without the feedback has following features:

Parameter Midband Gain Bandwidth Gain-Bandwidth product Input Resistance Output Resistance .

Without the feedback

With the feedback

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EXPERIMENT: 15 CLASS B PUSH PULL AMPLIFIER AIM: Testing of a transformer less Class B push pull amplifier and determine its conversion efficiency. COMPONENTS REQUIRED: Transistors (SL100 and SK100), Resistors (fixed and DRB), DC power supply, Ammeter, CRO and signal generator. THEORY: In a transformer less Class B push pull power amplifier two complementary symmetric transistor stages are used to avoid the use of a centre tapped transformer at the input and output stages. It is basically a class B amplifier, in which a transistor conducts for a half cycle. For complete conduction, such an amplifier uses two transistors. During the positive half cycle of the input signal, the NPN transistor conducts and during the negative half cycle PNP transistor conducts. The transistors conduct only if the input voltage crosses the threshold voltage of 0.7v.During this interval no transistors conducts .This causes a distortion called crossover distortion. CIRCUIT DIAGRAM:

OUTPUT WAVEFORM:

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PROCEDURE: 1) Connect circuit as shown in the diagram. 2) Measure a sine wave signal of 5v, 5 kHz and apply it as input (Vi) to the circuit. 3) Observe the crossover distorted sine wave as shown on the CRO, takedown same waveform on the tracing sheet. 4) By varying the Value of DRB (RL), note down the value of Vo(p-p) across DRB also note the value of Idc,then calculate conversion efficiency.

TABULAR COLUMN:

RL(DRB) Vo(p-p)v 100 200

Idc

Pdc=VccX Idc

Pac=[Vo(p-p)/22] 2/RL

Conversion efficiency, =Pac/Pdc

RESULT: The value of conversion efficiency of a transformer less Class B push pull Amplifier is:

(Signature of the Staff with Date)

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