Reg.No. KAMBAN ENGINEERING COLLEGE, THIRUVANNAMALAI MODEL EXAM Department of Electronics and Communication Engineering M.

E VLSI Design First Semester 248102/ADVANCED DIGITAL SYSTEM DESIGN Answer ALL Questions Time: Three Hours PART A 1. What are the steps involved in the design process of synchronous sequential systems. 2. Draw the block diagram of a mealy machine. 3. What is meant by State Assignment. 4. Define static and dynamic hazards. 5. State any two properties of Boolean difference method. 6. Define a test vector. 7. Name any two IC of PLD. 8. Differentiate between PAL and PLA 9. List any four VHDL operators. 10. Explain the concurrent Statements in VHDL. PART B 11. (i) Design a Moore and Mealy based serial adder. (OR) (ii) Construct an ASM block for State s1, that has two input variables x1 and x2 and one output variable Z. The output is asserted if x1 = 0 and x2 =1. The block exits to state s2 unless x1=x2=1, in which case the block exits to state s3. (16) Design an asynchronous sequential circuit that has two inputs X1 and X2 and one output Z.When X1 = 0, the output Z is 0. The first change in X2 that occurs while x1 is 1, will cause output Z to be 1. The output Z is 1, until X1 changes to 0. (16) (OR) 1 (16) Max. Marks : 100

12.

(i)

(ii) a. b. 13. (i) a. b.

Discuss Static and Dynamic Hazards in asynchronous circuits through example. (10) Explain Races in ASC. (6) Explain fault tolerance in PLA for sequential circuit. Discuss Compact Algorithm. (OR)

(ii) a. b. 14. (i)

Explain Boolean Difference method. Briefly explain Built-in-Self-Test method. Design an Up-Down Converter using PAL. (OR)

(ii) 15. (i)

Explain in detail about the CLB and i/o block of a Xilinx 2000 series FPGA. Write the VHDL code for Serial Adder, Binary multiplier and Binary Divider. (OR)

(ii)

With diagrams explain the process of designing a simple microprocessor using VHDL.