Dsk6713 TechRef Reva

TMS320C6713 DSK
Technical
Reference
2003 DSP Development Systems

TMS320C6713 DSK
Technical Reference
506735-0001 Rev. A
May 2003
SPECTRUM DIGITAL, INC.

12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: 281.494.5310
sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE
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Please be aware that the products described herein are not intended for use in life-support
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Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
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WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
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Copyright © 2003 Spectrum Digital, Inc.

Contents
1 Introduction to the TMS320C6713 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Provides you with a description of the TMS320C6713 DSK Module, key features, and
block diagram.
1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Power Supply ......................................................... 1-6
2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the major board components on the TMS320C6713 DSK.
2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 CPLD Overview .................................................... 2-2
2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.3 USER_REG Register .............................................. 2-3
2.1.4 DC_REG Register .................................................. 2-4
2.1.5 Version Register .................................................. 2-4
2.1.6 MISC Register ..................................................... 2-5
2.2 Codec Interface ..................................................... 2-6
2.3 SRAM Interface ..................................................... 2-7
2.4 Flash ROM Interface ................................................ 2-7
2.5 LEDs and DIP Switches .............................................. 2-7
2.6 Daughter Card Interface .............................................. 2-8
3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the physical layout of the TMS320C6713 DSK and its connectors.
3.1 Board Layout ........................................................ 3-2
3.2 Connector Index .................................................... 3-3
3.3 Expansion Connectors ................................................ 3-3
3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.1 J201, USB Port .................................................... 3-10
3.6.2 J8, External JTAG Connector ........................................ 3-10
3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7 System LEDs ....................................................... 3-11
3.8 Reset Switch ....................................................... 3-11
A Schematics .............................................................. A-1
Contains the schematics for the TMS320C6713 DSK
B Mechanical Information .................................................. B-1
Contains the mechanical information about the TMS320C6713 DSK
About This Manual
This document describes the board level operations of the TMS320C6713 DSP
Starter Kit (DSK) module. The DSK is based on the Texas Instruments
TMS320C6713 Digital Signal Processor.
The TMS320C6713 DSK is a table top card to allow engineers and software
developers to evaluate certain characteristics of the TMS320C6713 DSP to determine
if the processor meets the designers application requirements. Evaluators can create
software to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The TMS320C6713 DSK will sometimes be referred to as the DSK.
Program listings, program examples, and interactive displays are shown is a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.

This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents
Texas Instruments TMS320C67xx DSP CPU Reference Guide

Texas Instruments TMS320C67xx DSP Peripherals Reference Guide
Table 1: Manual History
Revision History
A Alpha Release
Chapter 1
Introduction to the
TMS320C6713 DSK
Chapter One provides a description of the TMS320C6713 DSK along

with the key features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-2
1.2 Functional Overview 1-3
1.3 Basic Operation 1-4
1.4 Memory Map 1-5
1.5 Configuration Switch Settings 1-6
1.6 Power Supply 1-6
1-1
Spectrum Digital, Inc
1.1 Key Features
The C6713 DSK is a low-cost standalone development platform that enables users to
evaluate and develop applications for the TI C67xx DSP family. The DSK also serves
as a hardware reference design for the TMS320C6713 DSP. Schematics, logic
equations and application notes are available to ease hardware development and
reduce time to market.
LINE OUT
HP OUT
LINE IN
MIC IN
Memory Exp
32
McBSPs
AIC23 EMIF
MUX
Host Port Int

Codec 8 8 32
JP1 1.26V
SDRAM
CPLD
6713
Flash
JP2 3.3V
JTAG DSP
MUX
Voltage
Reg HPI
Embedded Peripheral Exp
JTAG
BOOTM 1
BOOTM 0
JP4 5V
ENDIAN
HPI_EN
Config
Ext. LED DIP
PWR
USB
SW3
JTAG 1 2 3 4 0123 0123
Figure 1-1, Block Diagram C6713 DSK

The DSK comes with a full compliment of on-board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments TMS320C6713 DSP operating at 225 MHz.
• An AIC23 stereo codec
• 8 Mbytes of synchronous DRAM
• 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default

configuration)
• 4 user accessible LEDs and DIP switches
• Software board configuration through registers implemented in CPLD
• Configurable boot options
• Standard expansion connectors for daughter card use
• JTAG emulation through on-board JTAG emulator with USB host

interface or external emulator
• Single voltage power supply (+5V)

1-2 TMS320C6713 DSK Module Technical Reference
1.2 Functional Overview of the TMS320C6713 DSK
The DSP on the 6713 DSK interfaces to on-board peripherals through a 32-bit wide
EMIF (External Memory InterFace). The SDRAM, Flash and CPLD are all connected
to the bus. EMIF signals are also connected daughter card expansion connectors
which are used for third party add-in boards.
The DSP interfaces to analog audio signals through an on-board AIC23 codec and four
3.5 mm audio jacks (microphone input, line input, line output, and headphone output).
The codec can select the microphone or the line input as the active input. The analog
output is driven to both the line out (fixed gain) and headphone (adjustable gain)
connectors. McBSP0 is used to send commands to the codec control interface while
McBSP1 is used for digital audio data. McBSP0 and McBSP1 can be re-routed to the
expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties
the board components together. The CPLD has a register based user interface that
lets the user configure the board by reading and writing to its registers.
The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide the
user with interactive feedback. Both are accessed by reading and writing to the CPLD
registers.
An included 5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. The
board is held in reset until these supplies are within operating specifications.
Code Composer communicates with the DSK through an embedded JTAG emulator
with a USB host interface. The DSK can also be used with an external emulator
through the external JTAG connector.
1-3
1.3 Basic Operation
The DSK is designed to work with TI’s Code Composer Studio development
environment and ships with a version specifically tailored to work with the board.
Code Composer communicates with the board through the on-board JTAG emulator.
To start, follow the instructions in the Quick Start Guide to install Code Composer.
This process will install all of the necessary development tools, documentation and
drivers.
After the install is complete, follow these steps to run Code Composer. The DSK must
be fully connected to launch the DSK version of Code Composer.
1) Connect the included power supply to the DSK.
2) Connect the DSK to your PC with a standard USB cable (also included).
3) Launch Code Composer from its icon on your desktop.
Detailed information about the DSK including a tutorial, examples and reference
material is available in the DSK’s help file. You can access the help file through Code
Composer’s help menu. It can also be launched directly by double-clicking on the file
c6713dsk.hlp in Code Composer’s docs\hlp subdirectory.

1.4 Memory Map
The C67xx family of DSPs has a large byte addressable address space. Program code
and data can be placed anywhere in the unified address space. Addresses are always
32-bits wide.
The memory map shows the address space of a generic 6713 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of the internal memory
can be reconfigured in software as L2 cache rather than fixed RAM.
The EMIF has 4 separate addressable regions called chip enable spaces (CE0-CE3).
The SDRAM occupies CE0 while the Flash and CPLD share CE1. CE2 and CE3 are
generally reserved for daughtercards.
C67x Family
Address Memory Type 6713 DSK
0x00000000
Internal
Internal Memory
Memory
0x00030000
Reserved Space Reserved
or or
Peripheral Regs Peripheral
0x80000000
EMIF CE0 SDRAM
0x90000000 Flash
EMIF CE1 0x90080000
CPLD
0xA0000000
EMIF CE2
Daughter
0xB0000000 Card
EMIF CE3
Figure 1-2, Memory Map, C6713 DSK
1-5
1.5 Configuration Switch Settings
The DSK has 4 configuration switches that allows users to control the operational state
of the DSP when it is released from reset. The configuration switch block is labeled
SW3 on the DSK board, next to the reset switch.
Configuration switch 1 controls the endianness of the DSP while switches 2 and 3
configure the boot mode that will be used when the DSP starts executing.
Configuration switch 4 controls the on-chip multiplexing of HPI and McASP signals
brought out to the HPI expansion connector. By default all switches are off which
corresponds to EMIF boot (out of 8-bit Flash) in little endian mode and HPI signals on
the HPI expansion connector.
Table 1: Configuration Switch Settings
Switch 1 Switch 2 Switch 3 Switch 4 Configuration Description

Off Little endian (default)
On Big endian
Off Off EMIF boot from 8-bit Flash (default)
Off On HPI/Emulation boot
On Off 32-bit EMIF boot
On On 16-bit EMIF boot
Off HPI enabled on HPI pins (default)
On McASP1 enabled on HPI pins
1.6 Power Supply
The DSK operates from a single +5V external power supply connected to the main
power input (J5). Internally, the +5V input is converted into +1.26V and +3.3V using
separate voltage regulators. The +1.26V supply is used for the DSP core while the
+3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The
power connector is a 2.5mm barrel-type plug.
There are three power test points on the DSK at JP1, JP2 and JP4. All I/O current
passes through JP2 while all core current passes through JP1. All system current
passes through JP4. Normally these jumpers are closed. To measure the current
passing through remove the jumpers and connect the pins with a current measuring
device such as a multimeter or current probe.
It is possible to provide the daughter card with +12V and -12V when the external power
connector (J6) is used.

Chapter 2
Board Components
This chapter describes the operation of the major board components on

the TMS320C6713 DSK.
Topic Page
2.1 CPLD (Programmable Logic) 2-2
2.1.1 CPLD Overview 2-2
2.1.2 CPLD Registers 2-3
2.1.3 USER_REG Register 2-3
2.1.4 DC_REG Register 2-4
2.1.5 Version Register 2-4
2.1.6 MISC Register 2-5
2.2 AIC23 Codec 2-6
2.3 Sychronous DRAM 2-7
2.4 Flash Memory 2-7
2.5 LEDs and DIP Switches 2-7
2.6 Daughter Card Interface 2-8
2-1
2.1 CPLD (Programmable Logic)
The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic

Device (CPLD) device to implement:
• 4 Memory-mapped control/status registers that allow software

control of various board features.
• Control of the daughter card interface and signals.
• Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the DSK. Your own
hardware designs will likely implement a completely different set of functions or take
advantage of the DSPs high level of integration for system design and avoid the use
of external logic completely.
The CPLD implements simple random logic functions that eliminate the need for
additional discrete devices. In particular, the CPLD aggregates the various reset
signals coming from the reset button and power supervisors and generates a global
reset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides
128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is
EEPROM-based and is in-system programmable via a dedicated JTAG interface
(a 10-pin header on the DSK). The CPLD source files are written in the industry
standard VHDL (Hardware Design Language) and included with the DSK.

2.1.2 CPLD Registers
The 4 CPLD memory-mapped registers allows users to control CPLD functions in

software. On the 6713 DSK the registers are primarily used to access the LEDs and
DIP switches and control the daughter card interface. The registers are mapped into
EMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with a
simple asynchronous memory interface. The following table gives a high level
overview of the CPLD registers and their bit fields:
The table below shows the bit definitions for the 4 registers in CPLD.
Table 1: CPLD Register Definitions
Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 USER_REG USR_SW3 USR_SW2 USR_SW1 USR_SW0 USR_LED3 USR_LED2 USR_LED1 USR_LED0

R R R R R/W R/W R/W R/W
0(Off) 0(Off) 0(Off) 0(Off)
1 DC_REG DC_DET 0 DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0

R R R R R/W R/W
0(No reset) 0(low) 0(low)
4 VERSION CPLD_VER[3.0] 0 BOARD VERSION[2.0]

R R
6 MISC SCR_5 SCR_4 SCR_3 SCR_2 SCR_1 FLASH_PAGE McBSP1 McBSP0

R/W R/W R/W R/W R/W R/W ON/OFF ON/OFF
0 0 0 0 0 0 Board Board
(Flash A19=0) R/W R/W
0 0
(Onboard) (Onboard)
2.1.3 USER_REG Register
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or
off to allow the user to interact with the DSK. The DIP switches are read by reading the
top 4 bits of the register and the LEDs are set by writing to the low 4 bits.
Table 2: CPLD USER_REG Register
Bit Name R/W Description
7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)

3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)
2-3
2.1.4 DC_REG Register
DC_REG is used to monitor and control the daughter card interface. DC_DET detects
the presence of a daughter card. DC_STAT and DC_CNTL provide simple
communications with the daughter card through readable status lines and writable
control lines.
The daughter card is released from reset when the DSP is released from reset.
DC_RST can be used to put the card back in reset.
Table 3: DC_REG Register
7 DC_DET R Daughter Card Detect (1= Board detected)

6 0 R Always zero
5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)
4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)
3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)
2 0 R Always zero
1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)
0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)
2.1.5 VERSION Register
The VERSION register contains two read only fields that indicate the BOARD and
CPLD versions. This register will allow your software to differentiate between
production releases of the DSK and account for any variances. This register is not
expected to change often, if at all.
Table 4: Version Register Bit Definitions
Bit # Name R/W Description
7 CPLD_VER3 R Most Significant CPLD Version Bit

6 CPLD_VER2 R CPLD Version Bit
5 CPLD_VER1 R CPLD Version Bit
4 CPLD_VER0 R Least Significant CPLD Version Bit
3 0 R Always zero
2 DSK_VER2 R Most Significant DSK Board Version Bit
1 DSK_VER1 R DSK Board Version Bit
0 DSK_VER0 R Least Significant DSK Board Version Bit

2.1.6 MISC Register
The MISC register is used to provide software control for miscellaneous board
functions. On the 6713 DSK, the MISC register controls how auxiliary signals are
brought out to the daughter-card connectors.
McBSP0 and McBSP1 are usually used as the control and data ports of the on-board
AIC23 codec. The power-on state of these bits (both 0s) represents that situation.
Set the corresponding McBSP select bit to use the McBSP with a daughter card
instead.
The Flash and CPLD share CE1 which means that the highest DSP address bit (A21)
is used to differentiate between the two. The FLASH_PAGE bit is driven to the Flash as
a replacement for that address line which is connected to A19 of the Flash. On a
standard DSK, the on-board Flash is not large enough for this bit to be significant.
FLASH_PAGE is only useful if the board is re-populated with a larger pin-compatible
Flash chip.
The scratch bits are unused. They can be set to any value.
Table 5: MISC Register
7 SCRATCH_5 R/W Scratch bit 5

2 FLASH_PAGE R/W Flash address bit 19
1 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)
0 MCBSP0SEL R/W McBSP0 on/off board (0 = on-board, 1 = off-board)
2-5
2.2 AIC23 Codec
The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input
and output of audio signals. The codec samples analog signals on the microphone or
line inputs and converts them into digital data so it can be processed by the DSP.
When the DSP is finished with the data it uses the codec to convert the samples back
into analog signals on the line and headphone outputs so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. McBSP0 is
used as the unidirectional control channel. It should be programmed to send a 16-bit
control word to the AIC23 in SPI format. The top 7 bits of the control word should
specify the register to be modified and the lower 9 should contain the register value.
The control channel is only used when configuring the codec, it is generally idle when
audio data is being transmitted,
McBSP1 is used as the bi-directional data channel. All audio data flows through the
data channel. Many data formats are supported based on the three variables of
sample width, clock signal source and serial data format. The DSK examples generally
use a 16-bit sample width with the codec in master mode so it generates the frame
sync and bit clocks at the correct sample rate without effort on the DSP side. The
preferred serial format is DSP mode which is designed specifically to operate with the
McBSP ports on TI DSPs.
The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB
sample rate mode, named because many USB systems use a 12MHz clock and can
use the same clock for both the codec and USB controller. The internal sample rate
generate subdivides the 12MHz clock to generate common frequencies such as
48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATE
register. The figure below shows the codec interface on the C6713 DSK.
AIC23 Codec
0 LEFTINVOL
1 RIGHTINVOL
2 LEFTHPVOL MIC IN
Control Registers
3 RIGHTHPVOL
FSX1 McBSP0 CS 4 ANAPATH
CLKX1 SCLK 5 DIGPATH LINE IN
TX1 SDIN 6 POWERDOWN
SPI Format 7 DIGIF
8 SAMPLERATE
Digital 9 DIGACT Analog
15 RESET LINE OUT
DR2 McBSP1
DOUT MIC IN
FSX2 ADC
CLKR LRCOUT LINE IN
DSP Format BCLK
CLKX LRCIN
FSR2 DIN DAC LINE OUT
DX2 HP OUT HP OUT
Figure 2-1, TMS320C6713 DSK CODEC INTERFACE

2.3 Synchronous DRAM
The DSK uses a 64 megabit synchronous DRAM (SDRAM) on the 32-bit EMIF. The
SDRAM is mapped at the beginning of CE0 (address 0x80000000). Total available
memory is 8 megabytes. The integrated SDRAM controller is part of the EMIF and must
be configured in software for proper operation. The EMIF clock is derived from the PLL
settings and should be configured in software at 90MHz. This number is based on an
internal PLL clock of 450MHz required to achieve 225 MHz operation with a divisor of
2 and a 90MHz EMIF clock with a divisor of 5.
When using SDRAM, the controller must be set up to refresh one row of the memory
array every 15.6 microseconds to maintain data integrity. With a 90MHz EMIF clock,
this period is 1400 bus cycles.
2.4 Flash Memory
Flash is a type of memory which does not lose its contents when the power is turned
off. When read it looks like a simple asynchronous read-only memory (ROM). Flash
can be erased in large blocks commonly referred to as sectors or pages. Once a block
has been erased each word can be programmed once through a special command
sequence. After than the entire block must be erased again to change the contents.
The DSK uses a 512Kbyte external Flash as a boot option. It is visible at the beginning
of CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to support
the DSK's 16-bit boot option. However, the software that ships with the DSK treats the
Flash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit boot
mode. In this configuration, only 256Kbytes are readily usable without software
changes.
2.5 LEDs and DIP Switches
The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) that
provide the user a simple form of input/output. Both are accessed through the CPLD
USER_REG register.
2-7
2.6 Daughter Card Interface
The DSK provides three expansion connectors that can be used to accept plug-in
daughter cards. The daughter card allows users to build on their DSK platform to
extend its capabilities and provide customer and application specific I/O. The
expansion connectors are for memory, peripherals, and the Host Port Interface (HPI)
The memory connector provides access to the DSP’s asynchronous EMIF signals to
interface with memories and memory mapped devices. It supports byte addressing on
32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals like
McBSPs, timers, and clocks. Both connectors provide power and ground to the
daughter card
The HPI is a high speed interface that can be used to allow multiple DSPs to
communicate and cooperate on a given task. The HPI connector brings out the HPI
specific control signals.
Most of the expansion connector signals are buffered so that the daughter card cannot
directly influence the operation of the DSK board. The use of TI low voltage, 5V tolerant
buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be
used on the daughter card.
Other than the buffering, most daughter card signals are not modified on the board.
However, a few daughter card specific control signals like DC_RESET and
DC_DET exist and are accessible through the CPLD DC_REG register. The DSK
also multiplexes the McBSP0 and McBSP1 of on-board or external use. This function
is controlled through the CPLD MISC register.

Chapter 3
Physical Description
This chapter describes the physical layout of the TMS320C6713 DSK

and its connectors.
Topic Page
3.1 Board Layout 3-2
3.2 Connector Index 3-3
3.3 Expansion Connectors 3-3
3.3.1 J4, Memory Expansion Connector 3-4
3.3.2 J3, Peripheral Expansion Connector 3-5
3.3.3 J1, HPI Expansion Connector 3-6
3.4 Audio Connectors 3-7
3.4.1 J301, Microphone Connector 3-7
3.4.2 J303, Audio Line In Connector 3-7
3.4.3 J304, Audio Line Out Connector 3-8
3.4.4 J302, Headphone Connector 3-8
3.5 Power Connectors 3-9
3.5.1 J5, +5 Volt Connector 3-9
3.5.2 J6, Optional Power Connector 3-9
3.6 Miscellaneous Connectors 3-10
3.6.1 J201, USB Connector 3-10
3.6.2 J8, External JTAG Connector 3-10
3.6.3 JP3, PLD Programming Connector 3-11
3.7 System LEDs 3-11
3.8 Reset Switch 3-11
3-1
3.1 Board Layout
The C6713 DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which is
powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the
C6713 DSK.
J301 J303 J304 J302 J3 J4 J1
J6 J5 J201 JP3 SW1 D7-10 SW2 J8

Figure 3-1, TMS320C6713 DSK
3-2 TMS320VC6713 DSK Module Technical Reference

3.2 Connector Index
The TMS320C6713 DSK has many connectors which provide the user access
to the various signals on the DSK.
Table 1: TMS320C6713 DSK Connectors
Connector # Pins Function
J4 80 Memory
J3 80 Peripheral
J1 80 HPI
J301 3 Microphone
J303 3 Line In
J304 3 Line Out
J303 3 Headphone
J5 2 +5 Volt
J6 * 4 Optional Power Connector
J8 14 External JTAG
J201 5 USB Port
JP3 10 CPLD Programming
SW3 8 DSP Configuration Jumper
Note: “*” Not populated
3.3 Expansion Connectors
The TMS320C6713 DSK supports three expansion connectors that follow the Texas
Instruments interconnection guidelines. The expansion connector pinouts are
described in the following three sections.
The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profile
connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors
are designed for high speed interconnections because they have low propagation
delay, capacitance, and cross talk. The connectors present a small foot print on the
DSK. Each connector includes multiple ground, +5V, and +3.3V power signals so that
the daughter card can obtain power directly from the DSK. The peripheral expansion
connector additionally provides both +12V and -12V to the daughter card. The
recommended mating connector, whose part number is TFM-140-32-S-D-LC, is a
surface mount connector that provides a 0.465” mated height.
Note: I is on an Input pin

O is on an Output pin
Z is on a High Impedance pin
3-3
3.3.1 J4, Memory Expansion Connector
Table 2: J4, Memory Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description

1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin
3 AEA21 O EMIF address pin 21 4 AEA20 O EMIF address pin 20
11 GND Vss System ground 12 GND Vss System ground
27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2
29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0
33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30
41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable
75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready
77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2

3.3.2 J3, Peripheral Expansion Connector
Table 3: J3, Peripheral Expansion Connector

1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin
11 N/C - No connect 12 N/C - No connect
19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin
21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source
23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data
27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect
29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data
33 CLKX1 I/O McBSP1 transmit clock 34 CLKS1 I McBSP1 clock source
35 FSX1 I/O McBSP1 transmit frame sync 36 DX1 O McBSP1 transmit data
39 CLKR1 I/O McBSP1 receive clock 40 N/C - No connect
41 FSR1 I/O McBSP1 receive frame sync 42 DR1 I McBSP1 receive data
45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input
47 N/C - No connect 48 EXT_INT5 I External interrupt 5
49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input
53 EXT_INT4 I External interrupt 4 54 N/C - No connect
59 RESET O System reset 60 N/C - No connect
63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control
65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status
67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7
69 ACE3# O Chip enable 3 70 N/C - No connect
75 DC_DET# Vss System ground 76 GND Vss System ground
77 GND Vss System ground 78 ECL KOUT O EMIF Clock
3-5
3.3.3 J1, HPI Expansion Connector
Table 4: J1, HPI Expansion Connector

3 GND Vss System ground 4 HPI_RESETn I HPI reset input
5 CLKOUT3 O Clock output3 6 N/C - No connect
9 HD1/AXR1[7] I/O HPI data 1 10 N/C - No connect
11 HD3/AMUTE1 I/O HPI data 3 12 HD0/AXR1[4] I/O HPI data 0
13 HD5/AHCLKX1 I/O HPI data 5 14 HD2/AFSX1 I/O HPI data 2
15 HD7/GP0[3] I/O HPI data 7 16 HD4/GP0[0] I/O HPI data 4
17 GND Vss System ground 18 HD6/AHCLKR1 I/O HPI data 6
19 HD8/GP0[8] I/O HPI data 8 20 GND Vss System ground
27 GND Vss System ground 28 HD15/GP0[15] I/O HPI data 15
29 HDS2z/AXR1[5] I/O Host data strobe 2 30 GND Vss System ground
31 GND Vss System ground 32 HASz/ACLKX1 I/O Host address strobe
33 HDS1z/AXR1[6] I/O Host data strobe 1 34 GND Vss System ground
35 GND Vss System ground 36 HCNTL0/AXR1[3] I/O Host control 1
37 HCSz/AXR1[2] I/O Host chip select 38 GND Vss System ground
39 GND Vss System ground 40 HHWIL/AFSR1 I/O Host half-word select
41 HCNTL1/AXR1[1] I/O Host control 1 42 GND Vss System ground
43 GND Vss System ground 44 HINTz/GP0[1] I/O Host interrupt
45 HRDYZ/ACLKR1 I/O Host Ready 46 GND Vss System ground
47 GND Vss System ground 48 N/C - No connect
49 HR/Wz/AXR1[0] I/O Host R/W strobe 50 N/C - No connect
55 N/C - No connect 56 GND Vss System ground
67 N/C - No connect 68 SCL0 I/O I2C0 Clock
71 GND Vss System ground 72 SDA0 I/O I2C0 Data
79 GND Vss System ground 80 CLKOUT2/GP0[2] I/O GP I/O 0 bit 2

3.4 Audio Connectors
The C6713 DSK has 4 audio connectors. They are described in the following
sections.
3.4.1 J301, Microphone Connector
The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is
monaural. The signals on the plug are shown in the figure below.
Ground
Microphone In
Microphone Bias
Figure 3-2, Microphone Stereo Jack
3.4.2 J303, Audio Line In Connector
The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.
Ground
Right Line In
Left Line In
Figure 3-3, Audio Line In Stereo Jack
3-7
3.4.3 J304, Audio Line Out Connector
The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.
Ground
Right Line Out
Left Line Out
Figure 3-4, Audio Line Out Stereo Jack
3.4.4 J303, Headphone Connector
Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high

impedance speaker directly. The standard 3.5 mm jack is shown in the figure below.
Ground
Right Headphone
Left Headphone
Figure 3-5, Headphone Jack

3.5 Power Connectors
The C6713 DSK has 2 power connectors. They are described in the following
sections.
3.5.1 J5, +5 Volt Connector
Power (+5 volts) is brought onto the TMS320C6713 DSK via the J5 connector. The
connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The
A diagram of J5 is shown below.
+5V
J5 Ground
PC Board
Front View
Figure 3-6, TMS320C6713 DSK Power Connector
3.5.2 J6, Optional Power Connector
Connector J6 is an optional power connector. It will operate with the standard personal
computer power supply. To populate this connector use a Molex #15-24-4041. The
table below shows the voltages on the respective pins.
Table 5: J6, Optional Power Connector
Pin # Voltage Level
1 +12 Volts
2 -12 Volts
3 Ground
4 +5 Volts
WARNING !
Do not plug into J5 and J6 at the same time.
3-9
3.6 Miscellaneous Connectors
The C6713 DSK has 3 additional connectors to aid the user in developing with this
product. They are described in the following sections.
3.6.1 J201, USB Connector
Connector J201 provides a Universal Serial Bus (USB) Interface to the embedded
JTAG emulation logic on the DSK. This allows for code development and debug
without the use of an external emulator. The signals on this connector are shown in the
below.
Table 6: J201, USB Connector
Pin # USB Signal Name
1 USBVdd
2 D+
3 D-
4 USB Vss
5 Shield
6 Shield
3.6.2 J8, External JTAG Connector
The TMS320C6713 DSK is supplied with a 14 pin header interface, J8. This is the
standard interface used by JTAG emulators to interface to Texas Instruments DSPs.
The pinout for the connector is shown in the figure below.
TMS 1 2 TRST-
TDI 3 4 GND Header Dimensions
PD (+3.3V) 5 6 no pin (key) Pin-to-Pin spacing, 0.100 in. (X,Y)
TDO 7 8 GND Pin width, 0.025-in. square post
TCK-RET 9 10 GND Pin length, 0.235-in. nominal
TCK 11 12 GND
EMU0 13 14 EMU1
Figure 3-7, J8, JTAG INTERFACE

3.6.3 JP3, PLD Programming Connector
This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for the
programming of the CPLD. This connector is not intended to be used outside the
factory.
3.7 System LEDs
TheTMS320C6713 DSK has four system light emitting diodes (LEDs). These
LEDs indicate various conditions on the DSK. These function of each LED is shown in
the table below.
Table 7: System LEDs
Reference On Signal
Color Function
Designator State
D4 Green USB Emulation in use. When External JTAG 1

Emulator is used this LED is off.
D3 Green +5 Volt present 1
D6 Orange RESET Active 1
DS201 Green USB Active, Blinks during USB data transfer 1
3.8 Reset Switch
There are three resets on the TMS320C6713 DSK. The first reset is the power on
reset. This circuit waits until power is within the specified range before releasing the
power on reset pin to the TMS320C6713.
External sources which control the reset are push button SW2, and the on board
embedded USB JTAG emulator.
3-11

Appendix A
Schematics
This appendix contains the schematics for the TMS320C6713 DSK.

Board components with designators over 200 (e.g. DS201, R211) are part
of Spectrum Digital’s embedded JTAG emulator and are not included in
these schematics.
A-1
A
REVI SI ONS
A-2
REV DESCRI PTI ON DATE APPROVED
A B E TA 2 3-J an-20 03
2 3 -A p ril-2 00 3
T he T M S 3 2 0 C 6 71 3 D S K d e sign is b as ed o n
T M S 3 2 0 C 6 71 3 d e vice d e vice da ta sh e e t
S P R S 1 8 6 B a n d e rra ta S P R Z1 7 3 E . T his
sch e m a tic is su b je ct to ch a n ge w itho u t n otification.
S p e ctru m D ig ita l In c. a ssu m e s n o lia bility for
a p plica tio ns a ss ista n ce , cu sto m e r p rod u ct d e sign
o r in frin g e m e n t o f p a te n ts d e scrib ed herein.
DWN DATE
REVI SI ON STATUS OF SHEETS
CHK DATE
REV
ENGR DATE S P E C T R U M D IG IT A L IN C O R P O R A T E D
SH
ENGR- MGR DATE
REV A B A A A A A
QA DATE T itle
SH 8 9 10 11 12 13 14
MFG DATE
T M S 3 2 0 C 67 13 D SK
REV B A A A A A B NEXT ASSY USED ON S ize D ocum e nt N umb er R ev
RLSE DATE B B
SH 1 2 3 4 5 6 7 APPLI CATI ON
50 6 73 2
D a te: Tu esd ay, A pril 29, 20 03 S h eet 1 of 13
TMS320C6713 DSK Module Technical Reference

3 .3V
3 .3V
U S B _D S P _ R S T # R 35 10K
D C _E M IF A _OE # R 56 10K
3
D11 C P LD _ M CB S P 0_ M U X R 40 10K
R84
1 0K M M B D 414 8 C P LD _ M CB S P 1_ M U X R 23 10K
U8
5
SW 2 D C _S T A T0 R 97 10K
R 83 S N 7 4A HC 1G 14
1 4
1
2 3 2 4 D C _S T A T1 R 98 10K
RES ET F LS H C E n R 57
DGND PUS HBUTTON 33 C 119 10 K
3
0.1uF
3 .3V
DGND
DGND D SP_R ST# R 22

1K
B R D _R S T # R 24
1K
39
91
3
18
34
51
66
82
U 12 F LAS H _ P AG E R 39
1K
T D [0..3 1]
TD 0 42 25 DGND
VC C IO
VC C IO
VC C IO
VC C IO
VC C IO
VC C IO
DSP_DQ0 D C _S T A T 0 D C _S T A T0
VC C IN T
VC C IN T
TD 1 64 96 P U L LU P /D O W N T O K E E P LO G IC IN R E S E T
DSP_DQ1 D C _S T A T 1 D C _S T A T1
TD 2 41 W H E N TH E C P LD IS N O T P R O G R A M M E D .
3 .3V TD 3 DSP_DQ2
63 75 D C _C N T L 0
10K R N 19D TD 4 DSP_DQ3 D C _C N T L 0
44 81 D C _C N T L 1
10K R N 19E TD 5 DSP_DQ4 D C _C N T L 1
45
10K R N 19F TD 6 DSP_DQ5
46 52 D C_ E M IFA _DIR
10K R N 19G TD 7 DSP_DQ6 D C _ D BU F _D IR
58 37 D C _E M IF A _OE #
DSP_DQ7 D C _D B U F _O E n
T E A [2..21] 54 D C _C N T L _O E #
TEA2 D C _C N TL _O E n
40 79 D C _R S T #
SW 1 TEA3 D S P _ AD D R 0 DC_RES ETn 3 .3V
13 31 D C _D E T
TEA4 D S P _ AD D R 1 DC_DE Tn
4 5 1 00
D S P _ AD D R 2
3 6 69 C P L D _M CB S P 0 _M U X
M C B S P _S E L 0 R 78 R 79 R 80 R 81 R82
2 7 98 83 C P L D _M CB S P 1 _M U X
T C E 1n T E A 21 DSP_CSn M C B S P _S E L 1 150 15 0 1 50 150 1 50
1 8 8
C P L D /FL A S H n
76 BRD_R ST#
DGND S W D IP-4 /S M BRD_RSn
85 DSP_R ST#
DSP_RSn D6 D7 D8 D9 D 10
10 84
P A D D LE S W IT C H T C E 2n D S P _ D C _C S 0 n D S P _ R S n_ LE D
12
T C E 3n D S P _ D C _C S 1 n Y E L LO W GREEN GREEN GREEN G REEN
90
TSDW En D S P _ D C _W E n
9
3.3V TSDCASn D S P _ D C _R E n
14 D S P _ D C _O E n C P LD _ C L K _ O U T 80
TSDRASn
97 67 U S E R _ LE D 3
R 53 R 34 R 33 USER_SW 3 U S E R _L E D 3 U S E R _ LE D 2
94 47
NU NU NU USER_SW 2 U S E R _L E D 2 U S E R _ LE D 1
93 68
USER_SW 1 U S E R _L E D 1 U S E R _ LE D 0
35 71
USER_SW 0 U S E R _L E D 0
P W B _R E V 2 29 60
P W B _R E V 1 23 P W B _ RE V 2 S P AR E 0 30
P W B _ RE V 1 S P AR E 1
P W B _R E V 0 20 48 TP TP10
P W B _ RE V 0 S P AR E 2 21
R 54 R 37 R 36 S P AR E 3 TP TP16
C O D E C _C LK 87 C L KIN
1K 1K 1K 6 16
E M U _R S Tn R SV 0 TP TP19
36 56
PONRSn R SV 1
92 61
PUSHBRSn R SV 2 TP TP20
99
H P IR S n
57
DGND IS R _ TC K F LAS H _P AG E TP TP15
62 32
IS R _ TM S 15 TC K F LS H _ C E n 19
TM S F LS H _ W E n
IS R _TD I 4 17
U S B _ D S P _R S T # IS R _ TD O TDI FL S H _O E n F LAS H _P AG E
73
S V S _R S T # TD O
F LS H C E n
P U S H B _R S
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H P I_ R E S E T# F LS H W E n
11
26
33
38
43
53
59
65
74
78
86
88
89
95
E P M 31 28A T C 10 0-10
F LS H O E n
3 .3V
JP 3
2 1
4 3 DGND
6 5 3 .3V
8 7 CPLD
10 9
C38 C68 C 69 C71 C 72 C39 C 70 C40
DGND H E AD E R 5X 2 T itle
0 .1 0.1 0 .1 0 .1 0.1 0 .1 0.1 0 .1 T M S 3 2 0 C 67 13 D SK
10K R N 19A
10K R N 19B S ize D ocum e nt N umb er R ev
10K R N 19C B 50 6 73 2 A
DGND
A-3
C 121
A-4
X DS _4.1 V
0 .1 D G N D
U21
24
V cc
3 2 E IN T 4
D C _E IN T4 1 A1 1B1
4 5 E IN T 5
D C _E IN T5 1 A2 1B2
7 6 E IN T 6
D C _E IN T6 1 A3 1B3
8 9 E IN T 7
D C _E IN T7 1 A4 1B4
11 10 TIN P 0
D C _T IN P 0 1 A5 1B5
1
1OE
14 15 TIN P 1
D C _T IN P 1 2 A1 2B1
17 16 T OUT 0
D C _ TO U T 0 2 A2 2B2
18 19 T OUT 1
D C _ TO U T 1 2 A3 2B3
21 20
2 A4 2B4
22 23
2 A5 2B5
13 12
2OE GND
S N 74 C B T D 3 3 84P W
R 77 DGND
36 0
M a x im ize the dista nce be tw ee n sw itc hing sign als

D G N D and th e PLL extern al c om pone nts .
P la ce a ll P LL e xte rna l co m p one nts a s clo se

U 10 E
to t he D SP . A ll P L L externa l com pon en ts
m u s t be on a sin gle side of the bo ard . A 13
D S P _R S T # RESE Tn
TP28 C13
R51 NU N MI
C2
G P 4 /E X TINT 4/A M U T E IN 1
C1
G P 5 /E X TINT 5/A M U T E IN 0
D2
E X C C E T 10 3U G P 6 /E X TIN T6
E3
E 1 E M I FILTE R G P 7 /E X TIN T7
D S PIO _3 .3V
G2 G1
T INP 0/A X R0_ 3 T O U T 0/A X R 0 _2
1 3 F2 F1
I O T IN P1/A H C LK X 0 T O U T 1/A X R 0 _4
GN D
CT1 0 C 92
+ 10 0.1 A7 A8
D S P _ TD I TDI TD O DSP_TDO
2
DSP_ TM S B7
TM S
DSP_ TCK A6
TC K
D S P _T R S T # B6
TR ST n
D9 DSP_EMU0
DGND EMU0
B9 DSP_EMU1
C5 EMU1 D3
P LLH V EMU2 DSP_EMU2
B 10 DSP_EMU3
EMU3 C11
EMU4 DSP_EMU4
C LK M O D E 0 C4 C LK M O D E 0 EMU5 B 12 DSP_EMU5
C22 A3 Y 12 R25 33
C LKIN C LK O U T 2 /G P 2 C LK O U T 2
R17 Y11 D10 R26 33
N O -P O P E C LK IN CLKO UT3 C LK O U T 3
N O -P O P T M S 3 20 C 67 13 G D P
DGND O P T ION A L
3.3V
L5
C 1 14 C 11 3
0 .1 0.0 1 F errite C hip
U14
1 8
O F Fn V CC DGND
4 5 R 50 33 D S P _ C O R E _ C LK
GND CLK T itle
DGND 50 MHz
T M S 3 2 0 C 67 13 D SK
S ize D ocum e nt N umb er R ev
B 50 6 73 2 A

T E A [2..2 1]
U13
3 .3V T E A 14 23 2 TD 0
U 15 T E A 13 B A1 DQ0 TD 1
22 4
TE A 2 T E A 15 B A0 DQ1 TD 2
25 37 21 5
TE A 3 A0 V CC T E A 12 NC DQ2 TD 3
24 24 7
TE A 4 A1 TD 0 T E A 11 A 10 DQ3 TD 4
23 29 66 8
TE A 5 A2 DQ0 TD 1 T E A 10 A9 DQ4 TD 5
22 31 65 10
TE A 6 A3 DQ1 TD 2 TEA9 A8 DQ5 TD 6
21 33 64 11
20 35 63 13
19 38 62 74
18 40 61 76
TE A 10 A7 DQ5 TD 6 TEA5 A4 DQ9 TD1 0
8 42 60 77
TE A 11 A8 DQ6 TD 7 TEA4 A3 D Q 10 TD1 1
7 44 27 79
TE A 12 A9 DQ7 TD 8 TEA3 A2 D Q 11 TD1 2
6 30 26 80
TE A 13 A 10 DQ8 TD 9 TEA2 A1 D Q 12 TD1 3
5 32 25 82
TE A 14 A 11 DQ9 TD1 0 3 .3V A0 D Q 13 TD1 4
4 34 83
TE A 15 A 12 D Q 10 TD1 1 TBE 3n D Q 14 TD1 5
3 36 59 85
TE A 16 A 13 D Q 11 TD1 2 TBE 2n DQM3 D Q 15 TD1 6
FL AS H _ P AG E 2 39 28 31
TE A 17 A 14 D Q 12 TD1 3 R41 TBE 1n DQM2 D Q 16 TD1 7
1 41 71 33
TE A 18 A 15 D Q 13 TD1 4 TBE 0n DQM1 D Q 17 TD1 8
T D [0..31 ] 48 43 16 34
TE A 19 A 16 D Q 14 TD1 5 DQM0 D Q 18 TD1 9
17 45 36
TE A 20 A 17 D Q 15/A -1 D Q 19 TD2 0
16 73 37
A 18 1 0K NC D Q 20 TD2 1
9 15 57 39
A 19 R Y /B Y NC D Q 21 TD2 2
30 40
NC D Q 22 TD2 3
10 14 42
NC1 NC D Q 23
TD 0
TD 1
TD 2
TD 3
TD 4
TD 5
TD 6
TD 7
TD 8
TD 9
3.3V R58 1 0K TD2 4
TD 1 0
TD 1 1
TD 1 2
TD 1 3
TD 1 4
TD 1 5
TD 1 6
TD 1 7
TD 1 8
TD 1 9
TD 2 0
TD 2 1
TD 2 2
TD 2 3
TD 2 4
TD 2 5
TD 2 6
TD 2 7
TD 2 8
TD 2 9
TD 3 0
TD 3 1
47 13 45
BYT E NC2 TCE 0n D Q 24 TD2 5
FL S H C E n 26 14 20 47
CE NC3 TSD RASn CS D Q 25 TD2 6
FL S H O E n 28 19 48
OE TSDCASn R AS D Q 26 TD2 7
FL S H W E n 11 27 18 50
RN 6 A
RN 6 B
RN 6 C
RN 6 D
RN 6 E
RN 6 F
RN 6 G
RN 6 H
RN 5 A
RN 5 B
RN 5 C
RN 5 D
RN 5 E
RN 5 F
RN 5 G
RN 5 H
RN 4 A
RN 4 B
RN 4 C
RN 4 D
RN 4 E
RN 4 F
RN 4 G
RN 4 H
RN 3 A
RN 3 B
RN 3 C
RN 3 D
RN 3 E
RN 3 F
RN 3 G
RN 3 H
WE V SS TSDW En C AS D Q 27 TD2 8
B R D _R S T # 12 46 17 51
RES ET V SS WE D Q 28 TD2 9
53
A M 29LV 4 00B D Q 29 TD3 0
70 54
NC D Q 30
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
DGND TE A 16 69 56 TD3 1
256 K x 16 TE C LK O U T NC D Q 31
68
3.3V R59 1 0K CLK
67
CKE
86 43
V SS V DD
72 29
V SS V DD
ED 0
ED 1
ED 2
ED 3
ED 4
ED 5
ED 6
ED 7
ED 8
ED 9
ED 10
ED 11
ED 12
ED 13
ED 14
ED 15
ED 16
ED 17
ED 18
ED 19
ED 20
ED 21
ED 22
ED 23
ED 24
ED 25
ED 26
ED 27
ED 28
ED 29
ED 30
ED 31
58 15
V SS V DD
44 1
V SS V DD
84 81
V S SQ V D DQ
78 75
K18
K19
L1 8
L1 9
M 19
M 20
N18
N19
N20
P18
P20
R19
R20
T18
T20
T19
V4
W4
Y3
V2
V1
U2
U1
U3
T1
T2
R3
R2
P1
P2
P3
N3
V S SQ V D DQ
52 V S SQ V D DQ 55
46 49
38 V S SQ V D DQ 41 3.3V
ED 0
ED 1
ED 2
ED 3
ED 4
ED 5
ED 6
ED 7
ED 8
ED 9
V S SQ V D DQ
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30
ED31
32 35
V S SQ V D DQ
12 9
R 42 33 TE C LK O U T V S SQ V D DQ
6 3
TP 3 TP R 55 33 V S SQ V D DQ
J1 7 Y 10 TA E C L K O U T 2
HOLDn E C LK O U T M T 48 LC 2M 32B 2T G -6
TA R D Y Y5
A R DY DGND
NEAR DSP V 12 A S DW E # R 48 33 2 M x 32
A W E n /S D W E n /S S W E n TSDW En
W 10 A SD R A S# R 45 33
A O E n /S D R A S n /S SO E n TSDRASn
TEA2 33 R N 8H E A2 Y6 V 11 A SD C A S# R 47 33
E A2 A R En/S D C AS n/S S A DS n TSDCASn
TEA3 33 R N 8G E A3 V7
TEA4 33 R N 8F E A4 E A3 TP TP 5
W7 J18
TEA5 33 R N 8E E A5 E A4 H O LD A n TP TP 4
V8 J19
TEA6 33 R N 8D E A6 E A5 BUSREQ
W8
TEA7 33 R N 8C E A7 E A6
Y8
TEA8 33 R N 8B E A8 E A7
V9
TEA9 33 R N8 A E A9 Y9 E A8 V 17 33 R N 12D TC E 0n 3.3V
E A9 A C E0 n
T E A 10 33 R N 9H E A1 0 V 10 W 18 33 R N 12C
T E A 11 33 R N 9G E A1 1 E A1 0 A C E1 n 33 R N 7D TCE 1n C T1 3 CT 5
W 13 W6 TCE 2n
T E A 12 33 R N 9F E A1 2 E A1 1 A C E2 n 33 R N 7C + 10 + 10 C73 C 75 C 95 C97 C 74 C45
V 14 E A1 2 A C E3 n V6 TCE 3n
T E A 13 33 R N 9E E A1 3 W 14
T E A 14 33 R N 9D E A1 4 E A1 3 33 R N 12B
Y14 V 20 T B E 0n 0 .1 0.1 0.1 0.1 0.1 0 .1
T E A 15 33 R N 9C E A1 5 E A1 4 A B E0 n 33 R N 12A
W 15 E A1 5 A B E1 n U 19 T B E 1n
T E A 16 33 R N 9B E A1 6 Y15 Y4 33 R N 7B
T E A 17 33 R N9 A E A1 7 E A1 6 A B E2 n 33 R N7 A T B E 2n
V 16 V5 T B E 3n
T E A 18 33 R N 12H E A1 8 E A1 7 A B E3 n DGND
Y16
T E A 19 33 R N 12G E A1 9 E A1 8
W 17 E A1 9
T E A 20 33 R N 12F E A2 0 Y18
E A2 0
T E A 21 33 R N 12E E A2 1 U18 E A2 1
F L A S H & S D R A M & C O N F IG
T itle
U 10A
T M S 3 2 0 C 67 13 D SK
T M S 320 C 6 713 G D P S ize D ocum e nt N umb er R ev
B 50 6 73 2 A
A-5
A-6
5V
R1
D CIS O -4.1V
1
1 .6K
D1
L M 4 04 0D CIM 3-4.1
2
DGND
C 13 C 28
U4 0 .1 0.1 U9
16 16
V CC DGND DGND V CC
2 2 D C _C L K S 0
D C _C LK S 1 1B1 CLKS0 1B1
3 4 4 3
1B2 1A 1A 1B2
5 5 D C _C L K R 0
D C _C LK R 1 2B1 U 10 D CLKR 0 2B1
BCLK 6 7 7 6
2B2 2A 2A 2B2
11 CLKS1 E1 K3 11
3B1 C LK S /S C L1 C LK S 0/A HC L K R 0 3B1 D C _D R 0
D C _CL K X 1 10 9 CLKR1 M1 H3 DR0 9 10
3B2 3A C L KX 1 C LKR 1/A X R0 _6 C LK R 0/AC L K R 0 3A 3B2
14 L3 G3 14 D C _F S R 0
D C _D R 1 4B1 DR1 C LK X 1/AM U TE 0 C LK X 0 /AC LKX 0 FSR0 4B1
13 12 12 13
A IC 23S D A T A OU T 4B2 4A 4A 4B2
M2 J1
D X1 D R 1/SD A 1 D R0/A X R0_ 0
1 L2 H2 1
S D X1 A XR 0 _5 D X0/AX R 0 _1 S
15 8 8 15
OE GND FSR1 GND OE
M3 J3
F SX 1 FS R1/A X R0 _7 F S R 0/AF S R 0
L1 H1
S N 74 C B T3 25 7P W FSX 1 F SX 0 /AFS X0 S N 7 4C B T 3 2 57P W
N1
U3 SCL0 U1
N2
S DA 0
16 16
V CC V CC
2 2 D C _CL K X 0
D C _D X 1 1B1 C L KX 0 1B1
3 4 T M S 3 20 C 67 13 G D P 4 3 C T L_C L K X 0
A IC 2 3S D AT A IN 1B2 1A 1A 1B2
5 5 D C _D X 0
D C _F S R 1 2B1 D X0 2B1
6 7 7 6 C T L_D X 0
LRC O UT 2B2 2A 2A 2B2
11 11 D C _FS X 0
D C _FS X 1 3B1 3.3V F SX 0 3B1
10 9 9 10 C T L_F S X 0
L R CIN 3B2 3A 3A 3B2
14 14
4B1 4B1
13 12 12 13
4B2 4A 4A 4B2
1 1 C P LD _ M CB S P 0_ M U X
C P LD _M CB S P 1_M U X S R49 R 46 R 44 R43 S
15 8 8 15
OE GND 1 0K 10 K 10K 10 K GND OE
S N 74 C B T3 25 7P W S N 7 4C B T 3 2 57P W R 18
R12 36 0
3 60 DGND
DGND
R 27 33 S C L0
DGND DGND
R 28 33
S DA 0
MCB SP
T itle
T M S 3 2 0 C 67 13 D SK
B 50 6 73 2 A

E ND IAN
D E V IC E C O NFIGUR ATION
B O O T -1
B O O T -0
H P I_ E N
O FF - O P E N
O N - C LO S E D 3 .3V
SW 3
HD8 iP U 1 8 R85 1K
HD4 iP D 2 7 R86 1K
HD3 iP U 3 6 R87 1K
HD14 iP U 4 5 R3 1K
S W D IP-4/S M
P E N C IL SW IT C H
DGND
HD12 R29 1K
iP U R30 1K
C LK M O D E 0
H P I D A U GH T E R C A R D C AN R E S E T
U 10 C
D S P V IA THIS S IG N A L. S IGN A L IS
J1
C O M B IN E D W IT H O TH E R D S P
B14 H D 15 1 2
H D 15/G P 15 H D 14 1 2 RESET S O URCES.
C14 3 4
H D 14/G P 14 H D 13 3 4 3.3V
A 15 C LK O U T 3 5 6
H D 13/G P 13 H D 12 5 6
C15 7 8
H D 12/G P 12 H D 11 HD1 7 8
A 16 9 10
H D 11/G P 11 H D 10 HD3 9 10 HD0
B16 11 12
H D 10/G P 10 HD9 HD5 11 12 HD2 R 19
C16 13 14
H D 9 /G P 9 HD8 HD7 13 14 HD4 10K
B17 15 16
H D 8 /G P 8 HD7 15 16 HD6
A 18 17 18
H D 7 /G P 3 HD6 HD8 17 18
C17 19 20
H D 6 /A HC LK R 1 HD5 H D 10 19 20 HD9
B18 21 22
H D 5/A H C L KX 1 HD4 H D 12 21 22 H D 11 H P I_ R E S E T#
C19 23 24
H D 4 /G P 0 HD3 H D 14 23 24 H D 13
H D 3 /A M U TE 1 C20 25 25 26 26
D18 HD2 27 28 H D 15
H D2/A F SX 1 D20 HD1 H D S 2n 29 27 28 30
H D1 /A X R1 _7 HD0 29 30 H AS n
E20 31 32
H D0 /A X R1 _4 H D S 1n 31 32
33 34
33 34 H C N T L0
35 36
H IN T n HCSn 35 36
J2 0 37 38
H IN Tn /G P 1 H C N T L1 37 38 H HW IL
G 19 39 40
H C N T L1/A X R 1 _1 G 18 H C N T L0 H C N T L1 41 39 40 42
H C N T L0/A X R 1 _3 41 42
H20 H HW IL 43 44 H IN T n
H H W IL /A FSR 1 G 20 HRW n HRDYn 45 43 44 46
H R W n /A X R1 _0 H AS n 45 46
H AS n/AC L K X1 E18 47 47 48 48
F 20 HCSn HRW n 49 50
H C Sn /A X R1 _2 H D S 1n 49 50
E19 51 52
H D S1n /A X R1 _6 H D S 2n 51 52
F 18 53 54
H D S2n /A X R1 _5 HRDYn 53 54
H19 55 56
H D R Y n/A C LK R 1 55 56
57 58
57 58
59 60
61 59 60 62
61 62
63 63 64 64
65 66
TM S 32 0 C 6 71 3G D P 65 66
67 67 68 68 S C L0
69 69 70 70
71 72 S DA 0
71 72
73 73 74 74
75 75 76 76
77 78
77 78
79 80 C LK O U T 2
79 80
S F M 140 L2 S D LC
DGND DGND
H O S T P O R T /M c A S P
T itle
T M S 3 2 0 C 67 13 D SK
B 50 6 73 2 A
A-7
A-8
TE A [2 ..21 ]
D C _ D [31 ..0 ]
3.3V
3 .3V
3.3V D C _A[2 1..2 ]

TD [0.. 31]
U 17
42 7 R 13 U5
V cc V cc 10 K
31 18 42 7
V cc V cc V cc V cc
31 18
TD 0 D C _D 0 V cc V cc
47 2
TD 1 1 A1 1B 1 D C _D 1 T E A 17 D C _A 1 7 3 .3V
46 3 47 2
TD 2 1 A2 1B 2 D C _D 2 T E A 16 1A1 1B1 D C _A 1 6
44 5 46 3
43 6 44 5
TD 4 1 A4 1B 4 D C _D 4 T E A 14 1A3 1B3 D C _A 1 4 C17 C 15 C16 C 14
41 8 43 6
40 9 41 8
38 11 40 9 0.1 0.1 0 .1 0.1
37 12 38 11
TD15 1 A8 1B 8 D C _D 1 5 T E A 10 1A7 1B7 D C _A 1 0
36 13 37 12
TD14 2 A1 2B 1 D C _D 1 4 TEA9 1A8 1B8 D C_ A 9
35 14 36 13
TD13 2 A2 2B 2 D C _D 1 3 TEA8 2A1 2B1 D C_ A 8 DGND
33 16 35 14
32 17 33 16

30 19 32 17
29 20 30 19
TD 9 2 A6 2B 6 D C _D 9 TEA4 2A5 2B5 D C_ A 4
27 22 29 20
TD 8 2 A7 2B 7 D C _D 8 TEA3 2A6 2B6 D C_ A 3 3 .3V
26 23 27 22
2 A8 2B 8 TEA2 2A7 2B7 D C_ A 2
26 23
2A8 2B8
48
1OE C20 C 19 C21 C 18
1 48
1 DIR 1O E
25 1
2OE 1DIR
24 25 0.1 0.1 0 .1 0.1
2 DIR 2O E
24
2DIR
4 28
GND GND
10 34 4 28
GND GND GND GND DGND
15 39 10 34
GND GND GND GND
21 45 15 39
GND GND GND GND
21 45
GND GND 3 .3V
DGND S N 74 LV TH 1 62 45A DGND S N 74L V TH 1 624 5A
DGND DGND
C 1 16 C 11 5 C94 C 96
3.3V 3 .3V
0.1 0.1 0 .1 0.1
U 16 U6
42 7 42 7 DGND
V cc V cc V cc V cc
31 V cc V cc 18 31 V cc V cc 18
TD 1 6 47 2 D C _D 1 6 T E A 21 47 2 D C _A 2 1
TD 1 7 1 A1 1B 1 D C _D 1 7 T E A 20 1A1 1B1 D C _A 2 0 3 .3V
46 3 46 3
TD 1 8 1 A2 1B 2 D C _D 1 8 T E A 19 1A2 1B2 D C _A 1 9
44 5 44 5
TD 1 9 1 A3 1B 3 D C _D 1 9 T E A 18 1A3 1B3 D C _A 1 8
43 6 43 6
TD 2 0 1 A4 1B 4 D C _D 2 0 1A4 1B4 C 118 C 98 C99 C 11 7
41 8 T B E 3n 41 8 D C _B E 3#
TD 2 1 1 A5 1B 5 D C _D 2 1 1A5 1B5
40 9 T B E 2n 40 9 D C _B E 2#
TD 2 2 38 1 A6 1B 6 11 D C _D 2 2 38 1A6 1B6 11 0.1 0.1 0 .1 0.1
1 A7 1B 7 T B E 1n 1A7 1B7 D C _B E 1#
TD 2 3 37 12 D C _D 2 3 37 12
1 A8 1B 8 T B E 0n 1A8 1B8 D C _B E 0#
TD 3 1 36 13 D C _D 3 1 36 13
2 A1 2B 1 T C E 3n 2A1 2B1 D C _C E 3#
TD 3 0 35 14 D C _D 3 0 35 14
2 A2 2B 2 T C E 2n 2A2 2B2 D C _C E 2#
TD 2 9 33 16 D C _D 2 9 33 16 DGND
2 A3 2B 3 TSDCASn 2A3 2B3 D C _AR E #
TD 2 8 32 17 D C _D 2 8 TSDRASn 32 17 D C _AO E #
TD 2 7 2 A4 2B 4 D C _D 2 7 2A4 2B4
30 19 TSDW En 30 19 D C _AW E #
TD 2 6 2 A5 2B 5 D C _D 2 6 2A5 2B5
29 20 D C _ AR D Y 29 20 TARDY
TD 2 5 2 A6 2B 6 D C _D 2 5 2A6 2B6
27 22 27 22
TD 2 4 2 A7 2B 7 D C _D 2 4 2A7 2B7 R15 33
26 23 T A E C L K O U T2 26 23 D C _E C L K O U T
2 A8 2B 8 2A8 2B8
48 R14 48
1OE 1K 1O E
1 1
1 DIR 1DIR R 403
25 2OE 25 2O E
24 24 1K 3 .3V
2 DIR 2DIR
4 28 DGND 4 28
GND GND GND GND #O E DIR O P E R AT IO N
10 GND GND 34 10 GND GND 34
15 39 15 39 L L A <-- B
GND GND GND GND
21 45 21 45 L H A --> B
GND GND GND GND
H X IS O LA TION
DGND S N 74 LV TH 1 62 45A DGND DGND S N 74L V TH 1 624 5A DGND
D C _E M IF A _OE #
D A U G H T E R C A R D B U F F E R IN G
D C_E M IFA _ DIR
D C _E MIFA _ D IR =1 F O R W RITE S
T itle
T M S 3 2 0 C 67 13 D SK
D C _C N T L _O E # B 50 6 73 2 B

D C _D [31..0]
D C _ A[21..2]
5V 5V
-12V 12V
3.3V 3.3V 3 .3V 3.3V

E xte rna l P erip he ral Interfa ce E xterna l M e m ory In terface
5V J3 5V J4
2 1 2 1
2 1 D C _A 2 0 2 1 D C _A 21
4 3 4 3
4 3 D C _A 1 8 4 3 D C _A 19
6 5 6 5
6 5 D C _A 1 6 6 5 D C _A 17
8 7 8 7
8 7 D C _A 1 4 8 7 D C _A 15
10 9 10 9
10 9 10 9
12 11 12 11
12 11 D C _A 1 2 12 11 D C _A 13
14 13 14 13
14 13 D C _A 1 0 14 13 D C _A 11
16 15 16 15
16 15 D C_ A 8 16 15 D C_A 9
18 17 18 17
18 17 D C_ A 6 18 17 D C_A 7
20 19 20 19
20 19 20 19
22 21 D C _ CLK X 0 22 21
D C _ C LK S 0 22 21 D C_ A 4 22 21 D C_A 5
24 23 D C _ FS X 0 24 23
D C _D X 0 24 23 D C_ A 2 24 23 D C_A 3
26 25 26 25
26 25 26 25
28 27 D C _ C LK R 0 D C _ B E 2# 28 27 D C _B E 3 #
28 27 28 27
30 29 D C _ FS R 0 D C _ B E 0# 30 29 D C _B E 1 #
DC_DR0 30 29 30 29
32 31 32 31
32 31 D C _D 30 32 31 D C _D 3 1
34 33 D C _ CLK X 1 34 33
D C _ C LK S 1 34 33 D C _D 28 34 33 D C _D 2 9
36 35 D C _ FS X 1 36 35
D C _D X 1 36 35 D C _D 26 36 35 D C _D 2 7
38 37 38 37
38 37 D C _D 24 38 37 D C _D 2 5
40 39 D C _ C LK R 1 40 39
40 39 40 39
42 41 D C _ FS R 1 42 41
DC_DR1 42 41 D C _D 22 42 41 D C _D 2 3
44 43 44 43
44 43 D C _D 20 44 43 D C _D 2 1
46 45 DC_ TOUT 0 46 45
D C _ TIN P 0 46 45 D C _D 18 46 45 D C _D 1 9
D C _ E IN T 5 48 47 48 47
48 47 D C _D 16 48 47 D C _D 1 7
50 49 DC_ TOUT 1 50 49
D C _ TIN P 1 50 49 50 49
52 51 52 51
52 51 D C _D 14 52 51 D C _D 1 5
54 53 D C _ E IN T 4 54 53
54 53 D C _D 12 54 53 D C _D 1 3
56 56 55 55 56 56 55 55
58 57 D C _D 10 58 57 D C _D 1 1
60 58 57 59 D C _D 8 60 58 57 59 D C _D 9
60 59 DC_RS T# 60 59
62 61 62 61
62 61 3 .3V 3.3V D C _D 6 62 61 D C _D 7
64 63 D C _ C N T L1 64 63
D C _ C N T L0 64 63 D C _D 4 64 63 D C _D 5
DC_ST AT0 66 65 DC_ST AT1 66 65
66 65 D C _D 2 66 65 D C _D 3
68 67 D C _ E IN T 6 68 67
D C _ E IN T 7 68 67 68 67
70 69 R 65 R 16 D C _D 0 70 69 D C _D 1
70 69 10K 4.7K 70 69
72 71 72 71
72 71 72 71
74 73 D C _ AW E # 74 73 D C _AR E #
74 73 74 73
76 75 DC_D ET D C _AR D Y 76 75 D C _AO E #
76 75 76 75
DC_ECL KO UT 78 78 77 77 D C _ C E 2# 78 78 77 77 D C _C E 3 #
80 79 80 79
80 79 80 79
C O N N E C T O R 40 X 2 C O N N E C T O R 40 X 2
DGND DGND DGND DGND

R2 0
D A U G H T E R CA R D I/F
T itle
T M S 3 2 0 C 67 13 D SK
B 50 6 73 2 A
A-9
5V O P T IO N A L, P OW E R S U P P L Y
L O A D R ES IS TO R S , 2 512
A-10
BODY
C on nec t at pin 1
S e ts Voltage
R 3 46 R 34 7
NU NU 0.0 25 O H M S FO R P O W E R
M EASUREM EN T R10
3 .74 K 1%
SYSTEM PO W ER M EASUREM ENT A G ND R11 C 36

DGND DGND P O IN T S . R IS 25 12 B O DY , 6 V IA S R31 3 .3 s q in A G N D, m in 2 K 1% 82 00 pF 3.3V
FR O M P A D T O P L A N E C65 C 66 th ermal pad
71 .5K 1% C 12
0 .1u F 0.0 39u F U7 4 70 pF 3 30 0pF 10 7 1 %
21 C37 R 20 R38 TP 1
P O W E RP A D
20 1
RT A G ND 1 0K 1 % 10 K TP
19 2
SYNC V S E NS E R 21
POWER INPUT 18 3
5V L4 S S /EN A COMP
17 4 S V S _ R S T#
J5 0 VB IA S PW RGD C 10
5
R 99 BOO T 3.3V C 127
CENT ER 16
VIN3 0.047 uF D S PIO _3 .3V
SHU NT 15
B LM 41P 7 50 S P T CT 9 VIN2 L3 N O -P O P
S LE EV E 14 6
+ CT16 C63 + C64 VIN1 PH1 2.7 u H

R 52 7
2.5 M M JA C K 47 uF 0 .1u F PH2 CT 4 C 11 3 .3V @ 1.5Am p M ax
18 0 13 8 D S PIO _3 .3V
R A SM 7 12 10 uF LE S R 0 .1u F PGND3 PH3 + D 12
12 9
PGND2 PH4 0
11 10
PGND1 PH5
1
2
10 0uF 4 V 100 0p F M U R S 12 0T 3 R 66 TP31
TP
T P S 54 3 1 0P W P C T1 5
JP 4 D3 +
N O -P O P D 13 1 00 uF
G REEN
M U R S 12 0T 3 0 .02 5 O H M S F O R P O W E R
1
2
E M I S U P P R E S IO N . LOC A T E N E A R E A C H R E G UL A TO R . N O -P O P M EASU REM ENT
TP3 2 1.26V -> 24.3K 1% O P T IO N A L C R OS S C O U P LE
6 V IA S F R O M P A D T O P L AN E O R D IR E C T T IE .
1.2V -> 2 8.0 K 1% DSP PO W ER M EASUREM ENT
1 C on ne ct a t pin 1 D 14
JP 2 P O IN T S . R IS 2 512 B O DY , 6 V IA S
T estP o int F R O M P A D T O P LA N E
DGND M U R S 12 0T 3
JP 1
R6
24 .3K 1%
J6 D 15
-12V 12V R9 A G ND R5 C4
1
2
3 .3 s q in A G N D, m in 1.6 5K 1% 0.01u F M U R S 12 0T 3 N O -P O P
4 C6 C8 th ermal pad D S P _ CV D D
+5 TO BE POPULATED BY 71 .5K C2 M U R S 12 0T 3
3
GND 0 .1u F 0.0 39u F U2 5 60 pF D 16
-12 2 T H E U S E R IF
1 NEEDED. 21 C5 R8 0 D S P _CV D D
+ 12 20 P O W E RP A D 1 3 300 pF 107 1% R4
RT A G ND TP 2
19 2
NU SYNC V S E NS E R7 S E N S E _D SP _C V D D TP
18 3
M ole x 5 3-109-04 10 L2 S S /EN A COMP 10 K 1% CT1
17 4
VB IA S PW RGD C3 +
5
BOO T 1 00 uF
16
15 VIN3 0.047 uF 1 .26V @ 1.5Am p M ax
WARNI NG: VIN2
B LM 41P 7 50 S P T CT 3 14 6 L1
DO NOT SUPPLY POWER TO BOTH C9 + C7 VIN1 PH1 7 2.7 u H
0 .1u F PH2
POWER CONNECTORS AT THE 13 PGND3 PH3 8
10 uF LE S R 0 .1u F 12 9 + CT 2 C1
SAME TI ME! PGND2 PH4 100 uF 4V 10 00p F
11 10
PGND1 PH5
T P S 54 3 1 0P W P
E A C H R E G U LA T O R C AN S U P P L Y U P T O 3 A O F
DAUGHTERCARD STANDOFF GR OUNDING C U R R E N T . H O W E V E R C O M P O N E N T V A LU E S
H A V E B E E N S E L E C TE D FOR 1.5 A O P E R A TIO N .
M1 M2 M3 M4
1 25_ P H 12 5_P H 1 25_ P H 12 5_P H V A L U E S C A LC U LA T E D W IT H SW IF T D E S IG N T O O L 2 .0.
K E EP T R A C ES A M IN IM U M F O L LO W TP S 5 431 0 E V M LA Y O U T
O F 0.0 70 IN C HE S F R O M
TH E S E H O LE S .
POW ER
T itle
DGND T M S 3 2 0 C 67 13 D SK
B 50 6 73 2 B

D S P _CV D D D S PIO _3 .3 V
U 10G U 1 0H U 10I
A4 A 17 A1 P19
C V DD D V DD V SS V SS
A9 B3 A2 T4
A 10 B8 A 11 T1 7
B2 B 13 A 14 U4
C V DD D V DD U 10J V SS V SS
B 19 C 10 A 19 U8
C3 D1 A5 A 20 U9
C V DD D V DD R SV V SS V SS
C7 D 16 B5 B1 U 13
C 18 D 19 C 12 B4 U 17
D5 F3 D7 B 15 U 20
D6 H 18 D 12 B 20 W1
D 11 J2 A 12 C6 W5
D 14 M 18 B 11 C8 W 11
C V DD D V DD R 60 R SV V SS V SS
D 15 R1 C9 W 16
C V DD D V DD 1 0K V SS V SS
F4 R 18 D4 W 20
F 17 T3 TM S 32 0 C 671 3G D P D8 Y1
K1 U5 D 13 Y2
K4 U7 D 17 Y13
K 17 U 12 E2 Y19
C V DD D V DD DGND V SS V SS
L4 U 16 E4 Y20
L17 V 13 E 17
C V DD D V DD V SS
L20 V 15 F 19
C V DD D V DD V SS
R4 V 19 G4
C V DD D V DD V SS DGND
R 17 W3 G 17
C V DD D V DD V SS
U6 W9 H4
C V DD D V DD V SS
U 10 W 12 H 17
C V DD D V DD V SS
U 11 Y7 J4
C V DD D V DD V SS
U 14 Y 17 J9
C V DD D V DD V SS
U 15 J10
C V DD V SS
V3 TM S 32 0 C 6 71 3G D P J11
C V DD V SS
V 18 J12
C V DD V SS
W2 K2
C V DD V SS
W 19 K9
C V DD V SS
K 10
V SS
T M S 32 0 C 671 3G D P K 11
V SS
K 12
V SS
K 20
A ll c a p a c ito rs o n t h is s h e e t a r e d e c o u pli n g c a p a c it o rs for the D S P . T he y sho uld be pla ced as close as po ssible to the D S P . V SS
L9
D S P _CV D D V SS
L10
V SS
L11
V SS
L12
D S P _ CV D D V SS
M4
CT14 C T1 1 C 30 C 32 C 1 05 C 10 8 C50 C 46 C 23 C25 C 34 C58 C 88 C 112 C 1 10 C 104 C 1 01 C 52 C54 C 56 C 85 C83 C 81 C27 V SS
M9
+ 10 + 10 0.1 0.1 0 .1 0.1 0 .1 0.1 0 .1 0 .1 0.1 0 .1 0.1 0 .1 0.1 0.1 0 .1 0.1 0 .1 0.1 0 .1 0.1 0.1 0 .1 V SS
M 10
V SS
M 11
V SS
M 12
V SS
M 17
V SS
N4
V SS
N 17 V SS
P4
DGND C 77 C79 V SS
P 17
0.1 0 .1 V SS
T M S 32 0 C 671 3G D P
DGND
DGND
D S PIO _ 3.3V
D S PIO _3.3 V
CT 6 CT 8 C 24 C29 C 33 C62 C 90 C 109 C35 C 100 C 1 06 C 10 3 C 1 02 C 78 C 80 C47 C 48 C59
+ 10 + 10 0 .1 0 .1 0.1 0 .1 0.1 0 .1 0.1 0.1 0 .1 0.1 0 .1 0.1 0 .1 0.1 0.1 0 .1
DGND
C 41 C26 C 31 C51
0 .1 0.1 0.1 0 .1
D S P P O W E R & D E C O U P L IN G
DGND T itle
T M S 3 2 0 C 67 13 D SK
B 50 6 73 2 A
A-11
42 RN2C
DSP JTAG HEADER D S P _E M U 0
A-12
42 RN2D
42 R N2 A
D S P _E M U 1
42 RN2B
42 RN2E
D S P _E M U 2
3.3V 3.3V 42 RN2F
D S P _E M U 3
42 RN2G
D S P _E M U 4
J8 ROUTE TR ACES AS 42 RN2H
D S P _E M U 5
1 2 R 88
1K
ONE GROUP. MATCH
3 4
X D S_T V D 5 S IG NAL LENGTH.
7 8 3.3V
9 10
11 12
13 14 R 94
L O C A CT E R -P A C K N E AR D S P 3 0.1 K
H E AD E R 7 x2, E m ulation DGND J7
C2 A1 H U R R ICA N E _D E T n
EM U18 GND
B3 A2
JTAG MULTI PLEXERS EM U17 GND C 12 5
C4 A3
EM U16 GND
C5 A4
5V EM U15 GND
B5 A5 0.1
R93 EM U14 GND
C6 A6
X DS _4.1 V EM U13 GND
X DS _4.1 V B6 A7
EM U12 GND DGND

C7 A8
1
1.6K C 12 3 EM U11 TY P E 0
C9 A9
D5 EM U10 GND
B9 A 10
L M 4 04 0D CIM 3-4.1 EM U9 GND
0.1 C 10 A 11
EM U8 GND
B 10 A 12
EM U7 GND
C 11 A 13
EM U6 GND
2
DGND HUR_EMU5 B 11 A 14
HUR_EMU4 EM U5 GND
C 12 A 15
HUR_EMU3 EM U4 GND
C 13
HUR_EMU2 EM U3
B 13 D1
HUR_EMU1 EM U2 GND
C 14 D2
3 .3V DGND HUR_EMU0 EM U1 GND
B 14 D3
EM U0 GND
C8 D4
R 67 U 19 TC K R T N GND
B 12 D5
4 7K TC L K GND
16 B7 D6
X D S _T D O V CC TD O GND
2 B4 D7
T_ TDO 1B1 TD I GND
3 4 B2 D8
T _T D O X D S_ TD I 1B2 1A TM S TY P E 1
5 C3 D9
T_ T D I 2B1 TR S T n GND
6 7 C 15 D 10
T _T D I X D S _T M S 2B2 2A ID3 GND
11 C1 D 11
T_ T MS 3B1 ID2 GND
10 9 B 15 D 12
T _ T MS X D S _T R S T # 3B2 3A 3.3V ID1 GND
14 B1 D 13
T_ T R S Tn 4B1 R 91 1K ID0 GND
13 12 B8 D 14
T_TR STn 4B2 4A D S P _ TR S T # TV D GND
D 15
GND
1
3 .3V S D S P _ TM S H E AD E R 4x1 5
15 OE GND 8
DGND DGND
S N 74 C B T3 25 7P W D S P _ TD I
U 18 DGND R 10 0 3.3V
33 D S P _ TD O
5
S N 74 A HC 1G 1 4
U 26
H U R R ICA N E _ D E Tn 2 4
5
S N 7 4L VC 1 G 32
1
4 R96
DSP_TCK
3
2 33
3
3 .3V
DGND 3 .3V C 12 4
U 25 .1 uF
R90 16
4 7K X D S _E M U 0 2 V CC DGND
1B1
T _E M U 0 3 4 M U X _E M U 0 DGND
T _E M U 0 X D S _E M U 1 1B2 1A
5
5
T _E M U 1 2B1 M U X _E M U 1 U 24
6 2B2 2A 7
T _E M U 1 X D S _T C K 11 1
T_T CK 3B1 HUR_ TCK R 92
10 9 4
T _T C K X D S _T C K R E T 3B2 3A 33
14 4B1 2
T_ TCK_ R ET 13 12 HUR_ TCKR TN S N 74 LVC 1G 32
T_TCK_ RET 4B2 4A
3
1 DGND
3 .3V S
U 23 15 OE GND 8
C 126
5
5
U22 S N 74 C B T3 25 7P W R95
R89 D4 1 DGND 100 1% DGND
4 4 2
E M U L A T IO N
2 S N 74A HC 1 G 14 2 2p F
DGND
C 12 2 15 0 L TS T -C 15 0G K T S N 74L VC 1 G 3 2
3
3
U S B IN U S E T itle
.1uF
T M S 3 2 0 C 67 13 D SK
DGND S ize D ocum e nt N umb er R ev
B 50 6 73 2 A
DGND

5 4 3 2 1
3.3V
C 67
.1uFD G N D
U 11
5
D D
1 C LK _12M H Z
R 32 4
C O D E C _C LK 33 2
S N 74LVC 1G 32
3
DGND
3.3V U S B /Em ulation 5V
A IC 23 A udio 5V
C O D E C _S Y S C LK 3.3V
T_ TR ST n T_ TR STn
3.3V
B C LK D A T A _B C LK T_ TC K T _T C K
LR CIN D A TA _S Y N CIN PONRSn T_ TM S T _ T MS
S V S _R S T #
A IC 23S D AT A IN D AT A _DIN A IC 3.3V T _T D I T _T D I
C A IC 23S D A T A OU T D A T A _D O U T T_ TD O T _T D O C
LR C O U T D A T A _S Y N C O U T T _E M U 0 T _E M U 0
T _E M U 1 T _E M U 1
U S B _D S P _R S T # U S B _D S P _R S T #
C T L_D X 0 C T L_D A T A
C T L_C LK X 0 C T L_ C LK
C T L_F S X 0 C T L _C S GND C LK _12M H Z T _ T C K _R E T T_ TCK_ RET
A IC 23 A udio
C LK _24M H Z
GND
DGND
U S B /Em ulation DGND
B B
A A
Hierarc h aric al B loc k s
T it le
T M S 3 2 0 C 67 13 D SK
S ize D ocum ent N umber R ev
B A
506732
D ate: T uesday, A pril 29, 2003 S heet 12 of 13
5 4 3 2 1
A-13
5 4 3 2 1
L301
H Z 0805E 601R
C O D E C _S Y S C LK
A-14
J301 3 R 325
2.2K 3.3VA
4
C 315 R 326 4.7K
2
+
1
M icrophone In C 316
C 318 1uF NO POP L302 C 317
+
R 327 NO POP R 328 10uF C 319 B LM 21P 221S N NO POP
NO POP C 321 C 323220uF
0
+
D C 320 C 322 J302 D
3
NO POP 47pF 0.1uF
4
+
2
+
10uF C 325 1
C 324 220uF H ead P hone O ut
C 326 L303
0.1uF B LM 21P 221S N
C 327 C 328
C 329 NO POP NO POP
+
NO POP L304 C 330 10uF C 331 R 331
B LM 21P 221S N NO POP U 307 PW Package R 332 R 333 0
R 334 4.7K C 332 14 15 47K 47K
J303 C 333 0.1uF AV dd A G ND
3 8 11
H P Vdd HPGND
470nF 16
R 335 4.7K VM ID
4 25
C 334 X T I/MC LK
2 17 26
470nF M IC _BIAS XTO
1 18 2
Line In M IC _IN C LK O U T
20
L305 R 336 R 337 LLIN E _IN
19 10
B LM 21P 221S N 4.7K 4.7K R LIN E _IN RHPO UT
R 338 9
LH P O U T
0 23
C 335 C 336 S DIN R LIN E _O U T C 337
24 13
NO POP NO POP S P IM OD E S C LK R LIN E _O U T 470nF
C 22 12 C
MODE LLIN E _O U T LLIN E _O U T C 338
4 470nF
A IC 23LR C IN D IN C 339
5 6
LR CIN DOUT NO POP L306 C 340
7
A IC 3.3V LR C O U T A IC 3.3V B LM 21P 221S N NO POP
3 1
B C LK B Vdd R 339 100
R N 314 27
A IC 23CS D Vdd J304
1 8 21 28 3
CS DGND
2 7
3 6 T LV320A IC23 C 341 C 342 + R 340 100 4
4 5 C 343 2
0.1uF 0.1uF 1
10uF Line O ut
10K L307
B LM 21P 221S N
C T L_D A T A
R 341
47K R 342
C T L_ C LK
47K C 344 C 345 R 343
NO POP NO POP 0
C T L _C S
C ontrol P ort
B B
A IC 3.3V
R N 315
1 8
2 7 A IC 3.3V 3.3VA
3 6 L308 B LM 21P 221S N
4 5 R 344 2.2
10K R N 316
1 8 + +
D AT A _DIN
2 7 C 346 C 347
D A TA _S Y N CIN
D A T A _B C LK 3 6
10uF 10uF
D A T A _D O U T 4 5
33 A IC 3.3V
R 345 33 R 312 0
D A T A _S Y N C O U T A IC 3.3V
A A
A U D IO
GND
L309 B LM 21P 221S N T it le
T M S 320 C 6713 D SK
S ize D ocum ent N umber R ev
B A
506732
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5 4 3 2 1

Appendix B
Mechanical Information
This appendix contains the mechanical information about the

TMS320C6713 DSK produced by Spectrum Digital.
B-1
THIS DRAWING IS NOT TO SCALE
B-2 TMS320C6713 DSK Module Technical Reference

Printed in U.S.A., May 2003
506735-0001 Rev. A

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TMS320C6713 DSK

2003 DSP Development Systems

SPECTRUM DIGITAL, INC.

Copyright © 2003 Spectrum Digital, Inc.

1 Introduction to the TMS320C6713 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

This document uses the following conventions.

The TMS320C6713 DSK will sometimes be referred to as the DSK.

Information About Cautions

This book may contain cautions.

Texas Instruments TMS320C67xx DSP CPU Reference Guide

Chapter One provides a description of the TMS320C6713 DSK along

Host Port Int

Figure 1-1, Block Diagram C6713 DSK

• A Texas Instruments TMS320C6713 DSP operating at 225 MHz.

• An AIC23 stereo codec

• 8 Mbytes of synchronous DRAM

• 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default

• 4 user accessible LEDs and DIP switches

• Software board configuration through registers implemented in CPLD

• Configurable boot options

• Standard expansion connectors for daughter card use

• JTAG emulation through on-board JTAG emulator with USB host

• Single voltage power supply (+5V)

1.3 Basic Operation

1) Connect the included power supply to the DSK.

3) Launch Code Composer from its icon on your desktop.

1-4 TMS320C6713 DSK Module Technical Reference

1.4 Memory Map

Figure 1-2, Memory Map, C6713 DSK

1.5 Configuration Switch Settings

Table 1: Configuration Switch Settings

Switch 1 Switch 2 Switch 3 Switch 4 Configuration Description

1.6 Power Supply

1-6 TMS320C6713 DSK Module Technical Reference

This chapter describes the operation of the major board components on

2.1 CPLD (Programmable Logic)

The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic

• 4 Memory-mapped control/status registers that allow software

• Control of the daughter card interface and signals.

• Assorted "glue" logic that ties the board components together.

2.1.1 CPLD Overview

2-2 TMS320C6713 DSK Module Technical Reference

2.1.2 CPLD Registers

The 4 CPLD memory-mapped registers allows users to control CPLD functions in

Table 1: CPLD Register Definitions

0 USER_REG USR_SW3 USR_SW2 USR_SW1 USR_SW0 USR_LED3 USR_LED2 USR_LED1 USR_LED0

1 DC_REG DC_DET 0 DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0

4 VERSION CPLD_VER[3.0] 0 BOARD VERSION[2.0]

6 MISC SCR_5 SCR_4 SCR_3 SCR_2 SCR_1 FLASH_PAGE McBSP1 McBSP0

2.1.3 USER_REG Register

Table 2: CPLD USER_REG Register

Bit Name R/W Description

7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)

2.1.4 DC_REG Register

Table 3: DC_REG Register

Bit Name R/W Description

7 DC_DET R Daughter Card Detect (1= Board detected)

2.1.5 VERSION Register

Table 4: Version Register Bit Definitions

Bit # Name R/W Description

7 CPLD_VER3 R Most Significant CPLD Version Bit

2-4 TMS320C6713 DSK Module Technical Reference

2.1.6 MISC Register