MOOKAMBIGAI COLLEGE OF ENGINEERING Srinivasa Nagar, Kalamavur 622 502 ANNA UNIVERSITY, CHENNAI PRACTICAL EXAMINATION NOV12 SUB

UB CODE & NAME: EC2207 DIGITAL ELECTRONICS LAB SEMESTER: III DATE: 29.10.12-31.10.12
1. a) Design and implement a logic circuit to add two bits at a time. b) Implement a logic circuit to count from 0 to 15 and 15 to 0 in binary in asynchronous mode and test its operation using JK flip-flop. 2. a) Design and implement a logic circuit to subtract two bits at a time. b) Design and implement a logic circuit to convert a 4 bit gray code to 4 bit binary code.

3. Construct and test a 4 bit shift register to operate in parallel in serial out mode and serial
in parallel out mode using D flip-flop.

4. a) Design and implement a logic circuit to add three bits at a time.

b) Design and implement a combinatorial circuit to encode 8 data inputs. 5. a) Design and implement a combinatorial circuit to subtract three bits at a time. b) Construct a combinatorial circuit to add/subtract two, 4 bit numbers using MSI device.

6. Construct and test a sequential circuit to count from 0 to 7 and 7 to 0 in binary in a)

synchronous mode and b) asynchronous mode using JK flip-flop.

7. Construct and test a MOD 10, MOD 12 ripple counter. 8. a) Simulate a 4 bit serial in serial out shift register using verilog code.
b) Construct and test a 4 bit serial in serial out shift register using D flip-flop.

9. a) Simulate a 4 bit parallel in parallel out shift register using verilog code.
b) Construct and test a 4 bit parallel in parallel out shift register using D flip-flop.

10. a) Simulate a the operation of a full adder circuit using verilog code.
b) Design and implement a combinatorial circuit to convert a 4 bit binary code to 4 bit gray code.

11. a) Simulate a the operation of a half subtractor circuit using verilog code.
b) Design and implement a combinatorial circuit to convert a BCD code to Excess-3 code.

12. a) Simulate a the operation of a full subtractor circuit using verilog code.
b) Design and implement a combinatorial circuit to convert a Excess-3 code to BCD code.

13. a) Simulate the operation of a 4:1 MUX using verilog code.

b) Construct and test the working of a combinatorial circuit to add two, 2-digit BCD numbers using MSI device.

14. a) Simulate the operation of a 1:4 DMUX using verilog code.

b) Construct and test the working of a combinatorial circuit to compare two 8-bit data using MSI device.

15. a) Simulate the operation of a half adder circuit using verilog code.
b) Construct and test the working of a 16-bit even parity generator and checker using MSI device.

16. Design and implement a combinatorial circuit to compare two, 2-bit numbers using logic
gates.

17. a) Design and implement a combinatorial circuit to select one out of 4 data using logic
gates. b) Design and implement a combinatorial circuit to decode one out of 4 data using logic gates.

18. a) Design and implement a combinatorial circuit to route the input data to one of the
outputs using select lines. b) Simulate the working of a 3 bit synchronous up/down counter using verilog code.

19. a) Simulate a the operation of a half subtractor circuit using verilog code.
b) Design and implement a combinatorial circuit to convert a 4-bit Gray code to 4-bit binary code.

20. a) Simulate a the operation of a full adder circuit using verilog code.
b) Design and implement a combinatorial circuit to convert a BCD code to Excess-3 code. 21. Construct and test the working of a MOD16 synchronous up counter and down counter. 22. Construct and test the working of a 4 bit serial in serial out and parallel in parallel out shift registers. 23. Design and implement the combinatorial circuit to select one out of 4 data inputs using logic gates. Also write a verilog code and simulate its behaviour using test bench waveform. 24. Design and implement the combinatorial circuit to distribute the input data to one of the four outputs. Also write a verilog code and simulate its behaviour using test bench waveform.

INTERNAL EXAMINER

EXTERNAL EXAMINER

MOOKAMBIGAI COLLEGE OF ENGINEERING Srinivasa Nagar, Kalamavur 622 502 ANNA UNIVERSITY, CHENNAI PRACTICAL EXAMINATION NOV12 SUB CODE & NAME: EC2207 DIGITAL ELECTRONICS LAB SEMESTER: III DATE: 29.10.12-31.10.12 MARK ALLOCATION
S.No. Particulars Max. Mark 1. Aim & Apparatus required 10 2. Design & Procedure 40 3. Implementation & 35 4. 5. Verification Result Viva-voce Total 05 10 100 Mark Obtained

INTERNAL EXAMINER

EXTERNAL EXAMINER

EC 2207

DIGITAL ELECTRONICS LAB

1. Design and implementation of Adder and Subtractor using logic gates. 2. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa 3. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC7483 4. Design and implementation of 2 bit Magnitude Comparator using logic gates 8 Bit Magnitude Comparator using IC 7485 5. Design and implementation of 16 bit odd/even parity checker generator using IC74180. 6. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154 7. Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147 8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 9. Design and implementation of 3-bit synchronous up/down counter 10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops 11.Design of experiments 1, 6, 8 and 10 using Verilog Hardware Description Language