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Soft-Switching in DC-DC Converters: Principles, Practical Topologies, Design Techniques, Latest Developments

Raja Ayyanar Arizona State University Ned Mohan University of Minnesota Eric Persson International Rectifier
Some of the slides in this presentation are used for the course EE5741 Advanced Power Electronics given by Prof Robbins and Prof Mohan at the University of Minnesota

2002, N. Mohan, R. Ayyanar, E. Persson

APEC 2002

Objectives
What is soft-switching? Basic principles Concentration on a few popular topologies Design techniques Computer simulations New developments
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What is Soft-Switching
Switching transitions occur under favorable conditions device voltage or current is zero Reduced switching losses, switch stress, possibly low EMI, easier thermal management A must for very high frequency operation, (also medium frequency at high power levels) Usually involves compromises in conduction loss, switch rating, passive components etc.
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Relationship Between Efficiency and Power Density


500
450 500

400
350

400

300

300

Pout Pout + Ploss

Power Rating

250

200
150

200

Ploss = 20W Ploss = 10W

Pout

= Ploss 1

100
50

100

0 0 0.8

0 .8

0.82

0.84

0.84

0.86

0.88

0.88

0.9

0.92

0.92

0.94

0.96

0.96

Efficiency
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Hard-Switching
iL
Vd
iT

+ -

vT

-+

vdiode +

iL Io

vgate

vT

idiode vdiode

iT
Ploss

Psw f s tc( on ) + tc( off )

MOSFET Characteristics
Output characteristics
Cross-sectional view of an n-channel MOSFET

source

gate

n+

Cgs

p
Cgd

n+
Transfer characteristics

Cds

n
n+

drain-body depletion layer

drain
7

MOSFET Characteristics

Df Vin RG VGG C gs

Io

C gd

iD = f Vgs

( )

MOSFET model valid in active and cutoff regions

Variation of capacitances with Vds

Simulation of Hard Switching Converters


L2 40nH D2 80 R3 1m V1 50V IRF150 25.0 R2 M1 1A I3

Ideal diode

IRF150
0
20

vDS
10

vGS
0

iD
gate input

-10 0s V(M1:d)/4 0.5us ID(M1)*2 1.0us V(R2:2) 1.5us V(V3:+) 2.0us Time 2.5us 3.0us 3.5us 4.0us

Simulation of Hard Switching Converters


Diode reverse recovery
55 40

R_LOAD = 1 fs = 100k

MUR2020R

vds
V1
20

PARAMETERS:
5A D5 I1

vgs Io ids

100

MUR2020R
M1 10 V1 = 0 V2 = 15 TD = 1u TR = 1n TF = 1n PW = 2u PER = {1/fs} V4 MTB20N20E R2

-10 30.0us 30.4us 30.8us 31.2us -I(R3) V(M1:1)/2 V(M1:2) I(I1)


3 5 8.

31.6us

32.0us Time
3. 85

32.4us

32.8us

33.2us

33.6us

34.0us

vds
2 0 0.

vds
2. 00

MTB20N20E

ids Io
0

vgs
0

vgs ids Io
3.0s 31u 3.5s 31u Tm ie 3.0s 32u 3.5s 32u 3 . 0 s3 . 4 s 33u 33u

3 915 s 0. 4u 30 00 .95 us 31 000 .0 us - R3 V 1: /3 V( :2 I 1) I( ) (M 1) M1 ) (I Tim e

31 50 s .0 0u

3 00 s 3 12 us 1.1 0u 1. 99

3.5s 29u 3.0s 30u 3.5s 30u -(3 VM:)3 VM:) II) IR) (11/ (12 (1

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Problems of Hard-Switching
Switching losses Device stress, thermal management EMI due to high di/dt and dv/dt Energy loss in stray L and C

Possible Solutions (combination)


Snubbers to reduce di/dt and dv/dt
usually no change in losses (unless loss recovery)

Circuit layout to reduce stray inductances Gate drive


circuit layout turn on / off speeds

Soft switching to achieve ZVS and/or ZCS


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Snubbers
Passive components (R, L, C) and a diode to shape switching trajectories Turn-on snubber (seldom used)
iT +v T
-

Vd

At turn-on V iT (t ) = d t Ls low di/dt


Io

Ls

Rs

lower turn-on losses in the device low reverse recovery current

Price to be paid at turn-off


vT
0
t t

1/2 LI2 energy dissipated during off interval


off interval > 2 to 3 times LS/RS time constant switch voltage rating increases by RSIO
12

iT
0

Turn-off Snubbers
RS

iT

Vd

+ DS vT -

iCS
CS

At turn-off
while vT builds up

iT = Io iCS
Io

(iC flows through DS )


S

iT Io
C S3

switch turn-off loss decreases lower dv/dt


CS = 0
C S1 C S2 Vd

Issues at turn-on
1/2 CV2 energy dissipated in RS and switch switch current rating increases by Vd / R S ON interval > 2 to 3 times RSCS time constant

00

C S3 > C S2 > C S1

vT

13

Soft-Switching
ZVS (Zero Voltage Switching) ZCS (Zero Current Switching) Advantages - Lower losses (may be !) - Low EMI (may be !) - Allows high frequency operation
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ZVS (Zero Voltage Switching)


Turn ON Turn OFF

Switch voltage brought to zero before gate voltage is applied Ideal, zero-loss transition

Low-loss transition Parallel capacitor as a loss-less snubber

Preferred scheme for very high frequency applications using MOSFETs


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ZCS (Zero Current Switching)


Turn OFF Switch current brought to zero before gate voltage is removed Ideal, zero-loss transition Turn ON Low-loss transition Series inductor as a loss-less snubber Energy in junction capacitance is lost Best suited for converters with IGBTs due to tail current at turn-off
16

ZVS and Hard-Switched Waveforms


Zero-voltage switched
vdrain source vgate source

Hard-switched
12V vdrain source vgate source 0V 0V

12V

12V

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An Example: Zero Voltage Transition (ZVT)


Synchronous Buck Converter
At t = 0 , T + is turned off
T+
+

A
C+

( 0) = 0 v - ( 0 ) = Vd C
v
C+

v
iL

C+

C+

+v

C-

= Vd

Vd

D T

iL

C-

Vo

18

Zero Voltage Transition (ZVT)


Since v
Cs dv
C+
C+

+v

C-

= Vd
C-

Also, i i
C+

C+

-i

C-

= iL
= iL 2
Vd

dt
C+

+ Cs
C-

dv

dt

=0

= -i

C-

i
T
+

+i
i

=0
v v
iL

Cs+

C+

C+

=0 = Vd

Vd

C-

D+
A

C-

Vo

Cs-

At the end of this charge/discharge interval, positive iL is carried by D Subsequently, T is turned on; iL must reverse direction
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Zero Voltage Transition


v (t ) vaA ( t )
T
+

Cs+

C+

Vd
iL

Vo
t0 t0 t" t1 t1 t2 0

Vd

D
A

0
+

t3

C-

Vo

Cs-

iL
0
t

Conducting T + Devices

D T
None

D+

T+

None

None

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Simulation of a ZVT Buck Converter


PARAMETERS:
PulseWidth = 4.5us TDLY1 = 5.5us TDLY2 = 0.5us V7 25 V1 21V IRF150 L1 20uH IC = 2A R8 V8 25 M2 1000uF IC = 10V IRF150 C2 R6 10.0 Period = 10us R7 M1

TD = {TDLY1}

TD = {TDLY2}

ZVT_buck.opj
gate input

0
20

10

vDS vGS iL iD

-10

-20 9us V(M2:d)/2

10us ID(M2)*2

11us V(M2:g)

12us I(L1)*2 V(V8:+)

13us Time

14us

15us

16us

17us

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Classification of Soft-Switching Schemes


Load Resonant Converters Converters with Resonant Switches (Quasiresonant, Multi-resonant) Resonant Transition Converters ZVT and ZCT

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Phase Shift Controlled Full-Bridge Converter (ZVT)


Makes use of switch capacitances and transformer leakage inductance and magnetizing current
+ TA + TB

Vd

+
TA

A
TB

+ Da

D+ b
b D b

Io

Poles A & B switched at nearly 50% duty-cycle Output voltage regulation is achieved by phase modulating the two pole outputs
47

Switching waveforms
vA

Vd + 2 ficticious Vin 0
Vd + 2

+ A

+ DA

T
iAB

+ B

+ DB

vB
LlT

D A

+
B

v AB

iL

vAB

+ Da

D+ b
a

Io

Da

b D b

DB

iAB

In pole A T to T
A

A+

v AB =0 v AB =0

+Vd -Vd

In pole B T to T
B

B+ B

v AB = +Vd v AB = -Vd

A+

to T

B+

to T

0 0
48

Transitions - Pole B
TB to TB+
+ TA + TB
+ iL D a

v AB

TB- to TB+

iAB

Vd

A B
TB

Io
b D b
TB+ to TB-

v AB = +Vd iL stays at I o

v AB = -Vd

iL stays at - I o
49

Transitions - Pole A
+ TA + TB
+ Da iL

v AB

Vd

+
TA

Io
b D b

iAB

TA + to TA-

A B

A+

to T

v AB = 0

-Vd

All four diodes conduct Leakage inductance resonates with switch capacitance Determination of Tdel critical for ZVS design Load dependent ZVS
50

Methods to increase ZVS range


Use of external series inductor
+

Lo

iAB
Vin

A L series

vrect

Vo

vAB
0

Disadvantages Loss of volt-sec


higher turns-ratio higher conduction loss increased VA ratings
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iAB

vrect
left-leg

Load dependent ZVS

Use of magnetizing current


+

Vin

i load + i mag
A

i mag
B

Disadvantages higher conduction loss due to peak circulating current current through right-leg MOSFETs peak magnetizing current independent of Vin

vAB

i mag

left leg

52

Factors Affecting ZVS


ZVS Load Range Capacitance across MOSFETs internal and external Leakage inductance Delay time Magnetizing current Design of other parameters like Lo, Co, transformer etc identical to hard switched PWM

53

Designing for ZVS


MOSFET voltage during critical turn-on transition
vds = Vin I mag _ pk + I refl
=
1 2 Leq Cds

vds

Leq 2 Cds

sin ( t )

t
LLk 2Cds

Conditions for ZVS


1.

( I mag _ pk + I refl )

Leq 2 Cds

Vin,max

2. Tdelay =

Leq .2 Cds
54

Designing for ZVS


A Possible Design Approach Using MathCAD Sweep for all practical values of Cds - based on limiting voltage rise during turn-off Tdelay - as a percentage of switching period Calculate required Imag,pk and Llk for each set Calculate switch peak current and RMS current Turn-off loss Conduction loss

Calculate total losses. Iterate for different ZVS ranges


55

Designing for ZVS


Total Losses (W)

j Cds i Tdel
Total_loss
56

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