Design of RAKE Receiver

Dr. Chih-Peng Li ()
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Table of Contents
Maximal Ratio Combining (MRC) Implementation for Uplink RAKE Receiver Implementation for Downlink RAKE Receiver Multipath Searcher (Acquisition or Delay Estimation) RAKE Finger Management Hardware Functions Partitioning of Baseband Signal Processing

Maximal Ratio Combining

Introduction to RAKE Receiver

To utilize the advantages of diversity techniques, channel parameters are necessary to be estimated.
Arrival time of each path, Amplitude, and Phase.

Maximal Ratio Combiner (MRC):

The combiner that achieves the best performance is one in which each output is multiplied by the corresponding complex-valued (conjugate) channel gain. The effect of this multiplication is to compensate for the phase shift in the channel and to weight the signal by a factor that is proportional to the signal strength.
4

Maximum Ratio Combining (MRC)

MRC: Gi=Aie-ji
G1 G2 GL

Coherent Combining Channel Estimation Best Performance

Receiver

Maximum Ratio Combining (MRC)

Received Envelope:rL = Gl rl
l =1 2 Total Noise Power: = Gl n ,l 2 n 2 l =1 L L L

r = SNR: SNRL = 2 2 n

2 L

G r
l =1 L l 2 l =1

2 2 Gl n ,l

Since

G r
l =1 l

rl = Gl n ,l l =1 n ,l
L

Maximum Ratio Combining (MRC)

Chebychev's Inequality : Gl rl Gl n ,l
2 l =1 l =1 l =1 L 2 L L

n ,l

rl

SNRL

G 1
l =1 l

2 n ,l

l =1 2

n ,l

rl

2 L rl 1 = 2 = SNRl 2 l =1 n ,l l =1 L 2

2 Gl n ,l l =1

With equality hold : Gl n ,l = k

n ,l

rl*

Output SNR = Sum of SNRs from all branches @ Gl rl*

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General Block Diagram of the Receiver

The receiver is built up of four blocks: sub-chip tracking, multipath searcher and rake finger manager, the rake receiver and the decoder.
Transmitter

Channel

Multi-path Searcher and Rake Finger Manager

RF

SRRC

Sub-chip Time Tracking

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Rake Receiver

Channel Decoder

Implementation of Uplink RAKE Receiver

Example of Uplink Receiver Functional Block

Ci+jCq H(f)* W-D1 Cch1 Rake Receiver 1 Finger 1 Integrate & Dump Buffer Soft DPDCH

Uplink Transmitter

Soft DPDCH

Cch256,1 Ci+jCq W-Dn Finger Delay Adjustment Cch1 Integrate & Dump

Channel Estimator

Buffer

Finger 1 Soft DPCCH

Soft DPCCH

Rake Receiver N
Integrate & Dump Buffer Finger N Soft DPDCH Channel Estimator Finger N Integrate & Dump Buffer Soft DPCCH SIR -for Power Control

C256,1

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RAKE Receiver Architecture

Slot Number
Slow CE Fast CE

Pilot Table DelayF Channel Estimation DelayS

Power Control MRC

Control OVSF

SRRC Delay Element Frequency Offset Delay D Delay Estimation (Searcher) (Acquisition) Scramble Code Data OVSF 11

MRC

Interpolation

MRC

Channel Decoder

Detail of RAKE Receiver

1.

2.

3.

4. 5.

6.

First, the received signal is delayed by the Delay Element by DE chips, which is the same for all RAKE fingers. The delay of DE chips has to be larger than the overall multipath delay spread. The interpolator performs the tracking (fine timing adjustment) and reduces the sampling rate down to one sample per chip. The scramble code de-scrambles the received signals. The OVSF code of control channel reduces the control channel from chip rate to symbol rate. The OVSF code of data channel reduces the data channel from the chip rate to maximal symbol rate of data channel.

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Detail of RAKE Receiver

7.

8.

9.

10.

Frequency offset of the baseband signal is compensated by a phase rotation. Channel estimation parameters are obtained by measuring pilot symbols. Due to the different processing requirements for the control channel, both fast and slow channel estimation are computed for the DPCCH. All the channel estimation algorithms introduces certain delay, which needs to be compensated in both the data channel and the control channel.

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Implementation Issues
In processing the data in DPDCH, the TFCI information in one frame of DPCCH is needed before the associated DPDCH can be fully processed. This introduces 10 ms delay before DPDCH can be processed. As a result, a buffer is needed to store the 10 ms data. According to the location of this buffer with respect to the RAKE finger operations, there are chiefly three candidates: Buffer in front of RAKE finger operations. Buffer after MRC Two-stage despreading. Data modulation in the uplink direction is BPSK.

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Buffer in Front of RAKE Finger Operation

User 1, Finger 1 DPDCH(1) Despreading DPDCH(n) Despreading DPCCH Despreading/ Interpolation
. . .

Channel Compensation

DPDCH(1)
. . .

Interpolation

Channel Compensation Channel Compensation Channel Estimation

. . . DPDCH(n)

RAM (Bufer: 10ms + Multipath Delay)

Interpolation

MRC
TPC, FBI.
. . .

. . .

User 1, Finger L

DPDCH(1) Despreading DPDCH(n) Despreading DPCCH Despreading/ Interpolation

. . .

Channel Compensation

Interpolation

Channel Compensation Channel Compensation Channel Estimation TFCI Decoder

Interpolation

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Buffer in Front of RAKE Finger Operation Approximation of Required Buffer Size

Assumptions:
3 sectors. 2 antennas/sector. 5 bits/sample after SRRC. 2 samples/chip.

Buffer size (when neglecting multipath delay) = 3 sectors * 2 antennas/sector * 2(I/Q data) * 5 bits/sample * 2 samples/chip * 3840000 chips/sec * 0.01 sec/frame = 4,608,000 bits = 576 KByte.

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Buffer after MRC

User 1, Finger 1 Channel Compensation DPCCH Despreading/ Interpolation

Interpolation

Channel Compensation Channel Estimation RAM (Buffer: 10ms) MRC

DPDCH(1) Despreading
. . .

DPDCH(1)

RAM (Bufer: Multipath Delay) User 1, Finger L . . .

DPDCH(n) Despreading

DPDCH(n)

Channel Compensation DPCCH Despreading/ Interpolation TFCI Decoder Channel Compensation Channel Estimation

Interpolation

TPC, FBI.

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Buffer after MRC

The buffer can be located after MRC and this architecture can simplify the despreading operation. This architecture can be achieved with the expense of a faster rate of channel compensation and MRC.
Note that both channel compensation and MRC have to be operated at chip rate.

This architecture has the advantage of that the RAKE finger complexity is not increased by multiple DPDCHs. There is only one despreading operation per DPDCH.
Note that there is one despreading operation per DPDCH and per RAKE finger when buffer is located in front of RAKE finger operation.

The despreading process operates with real-value only. This reduces the complexity by half.
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Buffer after MRC

Approximation of Required Buffer Size
Assumptions:
5 bits/sample after the SRRC. All the finger operations and MRC increase each sample by 10 bits.

Buffer size = 15 bits/sample * 3840000 chips/sec * 0.01 sec/frame = 576,000 bits = 72 KByte.

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Two-Stage Despreading
User 1, Finger 1 DPDCH Despreading SF=4 Interpolation DPCCH Despreading/ Interpolation Channel Compensation Channel Estimation . . . User 1, Finger L DPDCH Despreading SF=4 Interpolation DPCCH Despreading/ Interpolation Channel Compensation Channel Estimation Channel Compensation TFCI Decoder MRC RAM (Buffer: 10ms) Channel Compensation

2nd stage despreading.

DPDCH Despreading

RAM (Bufer: Multipath Delay)

TPC, FBI.

1st stage despreading.

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Tow-Stage Despreading
Two-stage despreading can be adopted in the uplink direction. This architecture exploits the fact that all data channel have a common root in the OVSF code tree. As a result, the despreading operation from the chip rate to the symbol rate can be split into two stages: 1st stage: fixed rate despreading with the common root code. 2nd stage: variable rate despreading with the residual despreading code. The 2nd stage despreading can be applied once TFCI has been decoded. A buffer is required after MRC to store the soft MRC outputs of the DPDCh for 10 ms.
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Tow-Stage Despreading
In case of multi-code transmissions, all the spreading factors of DPDCH are 4. As a consequence, the despreading can be done in one step.

Approximation of Required Buffer Size

Assumptions:
5 bits/sample after the SRRC. All the finger operations and MRC increase each sample by 10 bits. Two buffers are needed after MRC since new data comes in while decoding old TFCI bits.

Buffer size = 15 bits/sample * 3840000 chips/sec * 0.01 sec/frame / 4 (SF) * 2 Buffers = 288,000 bits = 36 KByte.
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Maximal Ratio Combining (MRC)

If exact coherence is achieved, the contribution of a BPSK signal to the output is strictly real and the imaginary component contains noise only. Any MRC for BPSK modulated signal has the basic structure as shown in the figure of the following page titled Basic MRC. It is inefficient to implement the basic MRC since L complex multiplications are needed. It is mathematically equivalent to move the real part operation in front of the summing operator into each branch. In this case, only the real part of each complex multiplication needs to be computed as shown in the figure following next page titled Efficient MRC. This reduces the overall number of real multiplication by half.
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Basic Maximum Ratio Combinig

G*1(n) d1(n) G*2(n) d2(n) . . . G*L-1(n) dL-1(n) G*L(n) dL(n)
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Re{}

Efficient Maximal Ratio Combining (MRC)

Real Part of Channel Estimation.

Real Part

Despreaded DPDCH Imaginary Part

Finger 1 Finger 2

Adder
Finger L

Imaginary Part of Channel Estimation. 25

Implementation of Downlink RAKE Receiver

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Downlink RAKE Receiver

Data modulation in the downlink direction is QPSK. The RAKE fingers have been despread and at this point carry information in QPSK format.
Channel Estimation
G*i

Despread RAKE Finger (L)

Despread RAKE Finger (2) Despread RAKE Finger (1)

Delay

MRC

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Example of Downlink Receiver Functional Block

Finger Delay Adjustment H(f)* Integrate W D1 & Dump Cip - jCqp Cch0 . Buffer Channel Estimator Integrate & Dump Finger Delay Adjustment W - DN Ci - jCq Cchi Integrate & Dump Channel Estimator Integrate & Dump Buffer Finger N Soft CPICH Buffer Buffer Finger 1 Soft CPICH Soft CPiCH Finger N Soft DPCH Pilot + Sync Word Cip - jCqp Cch0 Ci - jCq Cchi Finger1 Sort DPCH Soft DPCH

Downlink Transmitter

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Multipath Searcher (Acquisition or Delay Estimation)

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Multipath Searcher for Acquisition

To maximize the sensitivity of the base station, the energy from all of the paths is combined to form an aggregate signal. Since the receiver has no a-priori knowledge of the possible paths, it must continuously search through all the possible paths. Multi-path searcher searches and detects the multi-paths from the transmitter. These signals once detected, and selected (via the RAKE finger manager), are combined within the RAKE receiver. Typically, acquisition determines the timing offset to within 1/2n for a over-sampling rate of n. The fine timing correction is achieved through the sub-chip timing tracker.
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Searcher Ranges
If the coarse synchronization is not provided by the cell search (downlink) or PRACH preamble detection (uplink), the searcher may be required to search a wide range of propagation delays, which have two components: The delay associated with the base station coverage: this is related to the maximum cell radius that the base station is designed to support. This delay corresponds, in general, to the shortest propagation path that is detected and is usually referred to as the main path. (Coarse Synchronization) The additional delays that come after the main path. The difference in time between the main path and the last path is usually referred to as the multi-path delay spread.
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Acquisition Mechanisms
The method of searching has the following approaches:
Coherent approach: The searches are performed on the DPCCH or CPICH, where symbol accumulation is achieved only on the pilot symbols. This method give the best results in terms of false alarm and probability of detection. Rely on a more complicated code generator controlling mechanism since multipath searcher must have additional control logic to ensure that only pilot symbols are accumulated.
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Acquisition Mechanisms
Non-coherent approach: This approach uses any of the symbols within the radio frame and this simplifies the timing control mechanism. The performance is much lower that of coherent approaches. Semi-coherent (most popular): The pilot symbols are coherently accumulated over a number (I) of time slots. Typically, one time slot coherent accumulation is adopted (I=1). The final acquisition outputs are the results of the noncoherent accumulation of J of I coherently accumulated time slots. Typically, non-coherent accumulation is made within one frame, i.e., 15 time slots (J=15).
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Searcher Architecture
The mechanism of multipath searching is based on correlating the incoming data samples with a locally generated code sequence. The correlation results indicate the potential multipath locations. There are two approaches for implementing the searcher: sliding correlator or matched filter. Bother approaches perform the same function. Typically, since approximate propagation delay has been estimated before this stage, searcher can concentrate its efforts on the multipath delay spread of the channel. As a result, a serial and parallel matched filter architecture can be adopted. However, in certain systems, the approximate propagation delay may not be known by the receiver. Under such situation, the search has to obtain the coarse synchronization.
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Searcher Architecture
The searcher is typically implemented as a length N code matched filter that has complex code-coefficient. N usually takes a value of 128 or 256, which corresponds to delay spreads of 5 Km or 10 Km.
Delay Line Length = N Over-sampling Rate

Length = N Over-sampling Rate

CN CN-1

C1

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Example of Semi-coherent Searcher Architecture

Over-sampling=2 Sampled Data Serial Parallel MF N=256
# PilotSymbo l

15TimeSlot

256 Chips Delay 512 data

||

256 Chips Delay 512 data

Over-sampling=2 Sampled Data Serial Parallel MF N=256

# PilotSymbo l

256 Chips Delay 512 data

||

15TimeSlot

256 Chips Delay 512 data

Peak Search

RAKE Finger Management

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Approximation of Square Root Circuit

Approximation of Non-Coherent Detection 1.5

1 Amplitude

0.5

|sin| |cos|

a=max(|sin|,|cos|) b=min(|sin|,|cos|)

(sin)2+(cos)2 |sin|+|cos| a+b/2 a+(sqrt(2)-1)*b max((a+b/8),(53a+37b)/64) 0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 Radian (pi) 0.4 0.6 0.8 1

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Peak Search Algorithm

Once all of the pilot energy has been accumulated semicoherently, the outputs are usually processed by DSP firmware entities. Example of peak search algorithm (over-sampling rate =2):
1.

2. 3. 4. 5.

The profile of semi-coherently accumulated pilot energy is compared with a threshold. The collection is denoted by S. Find the maximum value of the peaks in S. Store the peak in set T. Remove two peaks that are chip on either side of the peak in 2. Repeat steps 2 and 3 until S is empty. If the number of peaks in T is greater than the maximum number (L) preset by the algorithm, find the maximum L peaks in T.
Alternatively, we can select the best N peaks in set T.

6.

The peaks ( min(L,T) ) are processed by the RAKE finger manager.

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Uplink Timing of Matched Filter

At the UE, the uplink DPCCH/DPDCH frame transmission takes place approximately T0 chips after the reception of the first significant path of the corresponding downlink DPCCH/DPDCH frame. T0 is a constant defined to be 1024 chips. At t =0, the UE is x Km away from the base station. This corresponds to 2x Km propagation delay and is shown in the page titled Uplink Timing of Matched Filter 1/6. We assume a 256 taps of matched filter. At this moment, the coefficients in the matched filter is still empty. However, the searcher begins to generate the first 256 code coefficients.
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Uplink Timing of Matched Filter 1/6

Matched filter begins to generate code coefficients. BS frame boundary + T0 Chips
Frame boundary at UE.
2 Pilot Symbol #2, Path #3 Pilot Symbol #1, Path #3 Pilot Symbol #1, Path #2 Pilot Symbol #1, Path #1 1

Pilot Symbol #2, Path #2

Pilot Symbol #2, Path #1

t =x/c t =2x/c

t =0
Matched Filter (N=256) Empty

Time

10 Km
40

10 Km

Uplink Timing of Matched Filter

When the searcher starts to generate the code coefficients for the matched filter at rate 1 code coefficient per chip, the signals propagate towards the base station and over-sampled signal samples are stored in the delay line of the matched filter. After the first 256 chips of data (512 samples for oversampling rate =2) are shift into the delay line of the matched filter, the 256 code coefficients are also generated and are loaded into the filter. This is the moment shown in the page titled Uplink Timing of Matched Filter 2/6. When the first 256 chips of data samples immediately after the frame boundary are shifted into the filter delay line, the matched filter generated no output since code coefficients have not loaded into the filter.
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Uplink Timing of Matched Filter

The filter is thus operated since the first set of code coefficients will not be matched to the received data samples. The first matched filter output, that are stored in the 1st stage of the 256 chips delay for accumulation, are generated on receiving the first sample of the 256th chip of data. This is to ensure the searcher will function properly when the propagation delay equal to zero. In fact, for a matched filter of length 256/128 chips, the search range is slightly less than 10.0/5.0 Km. For a over-sampling rate of 2, the difference is: 0.5 [chip] / 3.84 [Mcps] 3.0e8 [m/sec] / 2 (round trip delay) = 19.53125 meter.
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Uplink Timing of Matched Filter 2/6

Matched filter begins to generate outputs and store in the 1st stage of the 256 chips delay.
2 Pilot Symbol #3, Path #3 Pilot Symbol #2, Path #3

2x/c
1

x/c

Pilot Symbol #1, Path #3 Pilot Symbol #1, Path #2 Pilot Symbol #1, Path #1

Pilot Symbol #3, Path #2

Pilot Symbol #2, Path #2

Pilot Symbol #3, Path #1

Pilot Symbol #2, Path #1

t =256 chips

First output is generated. 10 Km

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Time

Matched Filter (N=256)

256 Code Coefficients #1

10 Km

Uplink Timing of Matched Filter

In the next 256 chips of duration, the output of the matched filter is accumulated in the first stage of the 256 chips delay. At the same time, the new code coefficients are generated. When the 256 chips duration of outputs (512 samples for oversampling rate =2) are generated, the new coefficients are loaded into the filter. Accumulation continues until t = {256(# Pilot Symbol +1) (1/Over-sample Rate)} chips. At this time instant, the first stage of coherent detection ends. All the outputs stored in the 1st stage of the 256 chips delay are shifted into the 2nd stage of the 256 chips delay for non-coherent accumulation.
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Uplink Timing of Matched Filter 3/6

2x/c
2 Pilot Symbol #3, Path #3 1

x/c
Pilot Symbol #1, Path #3 Pilot Symbol #1, Path #2 Pilot Symbol #1, Path #1

Pilot Symbol #2, Path #3

Pilot Symbol #3, Path #2

Pilot Symbol #2, Path #2

Pilot Symbol #3, Path #1

Pilot Symbol #2, Path #1

t =512 chips
Matched Filter (N=256)

Time

Accumulated matched filter output stored in the 1st stage of the 256 chips delay.

256 Code Coefficients #2

2x/c

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Uplink Timing of Matched Filter 4/6

2x/c x/c
Pilot Symbol #3, Path #3 Pilot Symbol #2, Path #3 Pilot Symbol #2, Path #2 Pilot Symbol #2, Path #1

Pilot Symbol #3, Path #2

Pilot Symbol #3, Path #1

t =768 chips
Matched Filter (N=256)

Time

Accumulated matched filter output stored in the 1st stage of the 256 chips delay.

256 Code Coefficients #3

2x/c

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Uplink Timing of Matched Filter 5/6

2x/c x/c
Pilot Symbol #3, Path #3 Pilot Symbol #3, Path #2 Pilot Symbol #3, Path #1

t =1023.5 chips
Matched Filter (N=256)

Time

Accumulated outputs stored in the 1st stage of the 256 chips delay are shifted to the 2nd stage of the 256 chips delay.

256 Code Coefficients #3

Shift to the 2nd stage

2 1 2x/c

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Uplink Timing of Matched Filter 6/6

2x/c x/c
Pilot Symbol #3, Path #3 Pilot Symbol #3, Path #2 Pilot Symbol #3, Path #1

t =1024 chips
Matched Filter (N=256)
Empty

Time

Accumulated outputs stored in the 1st stage of the 256 chips delay are shifted to the 2nd stage of the 256 chips delay.

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RAKE Finger Management

49

Introduction to RAKE Finger Management

The multipath searcher tries to detect the valid multipaths and results are further processed by the RAKE finger manager to validate and keep track the multipaths during transmission. The performance of a multipath searcher can be evaluated in terms of detection probability and false alarm. However, the cost of error is unbalanced. The function of RAKE finger management, which performs by the RAKE finger manager (RFM), is to minimize the cost due to errors. Certain reports show that the cost of erroneous addition of an improper multi-path due to false alarm is higher than missing a correct multi-path. (Need to be verified.)
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Multipath Verification Processes

When the searcher has found a set of multipath candidates, these potential fingers have to be further processed to confirm their validity. Typically, this consists of two major steps: The multipath confirmation process will be done by the RAKE finger manager. This process is typically implemented by the multipath verification function, which utilizes the information from both the searcher outputs and the channel estimation to assign a RAKE finger to a multipath. In addition, the finger tracking function uses the output of each RAKE fingers (fast) channel estimation to validate the existence of fingers and decides to drop/add or replace fingers.
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Status of RAKE Fingers

According to the multipath verification procedures, there are three states that a finger in a RAKE receiver can be designated: Inactive or idle finger: Finger that is not being used. Candidate finger: Finger that is under monitoring after being assigned by RAKE finger manager to work on a new multipath peak. This finger is not being used in MRC. Active finger: Finger which is used in MRC.

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Principles of RAKE Finger Management 1/2

After receiving inputs from the multipath searcher, the RAKE finger manager (RFM) compares them with a pre-set threshold to verify the inputs. If the peak of a multipath is above the pre-set threshold, the RFM regards the peak as a candidate multipath and assigns a RAKE finger, if available. If the new multipath found is within chip offset from an active finger, they are to be regarded as an identical multipath. At this moment, the candidate multipath peak is only regarded as a candidate RAKE finger and not a member of the active RAKE finger set yet. The candidate RAKE fingers (fast) channel estimation metric is compared to an active finger with the lowest (fast) channel estimation metric in the active RAKE finger set.
53

Principles of RAKE Finger Management 2/2

The ratio for replacing the RAKE fingers between the two metrics is parameterized as minimum finger substitution ratio. If a candidate RAKE finger channel estimation metric is larger than the active finger with the lowest channel estimation metric by the minimum finger substitution ratio, then RFM waits for another period for further verification of the candidate RAKE finger. The period of a candidate finger verification is parameterized as minimum RAKE hold time [time slots]. If all the verification of a candidate RAKE finger pass for the minimum RAKE hold time, the RFM replaces the active RAKE finger which has the lowest channel estimation metric with the candidate RAKE finger.
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Channel Estimation Metric

The (fast) channel estimation metric of an active and candidate finger may be obtained from a first order IIR low pass filter, for example, once per time slot.
X

Y(i)= X(i)+(1- )Y(i-1)

1-

Selection of : The should be large enough to respond to the channel variation. The should be small enough to reduce the error due to the instantaneous noise and interference that passes through the channel estimation filter.
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Operation of RAKE Finger Management

1.

2.

3.

Initialization of RAKE Finger Management: RFM (typically implemented in DSP) initializes the multipath search and RAKE finger verification/tracking process by updating related parameters, which includes the active finger set, candidate finger set, inactive finger set, etc. Then, searcher starts to search the multipaths and RFM is ready to read searcher output. After receiving multipaths from the searcher, RFM launches the multipath verification process, which is followed by the finger tracking process. Read Searcher Output: RFM obtains the peaks, together with the associated delays, and compares with the pre-set threshold. New Multipath Checking: If a new multipath found is
56

Operation of RAKE Finger Management

different in time within chip from any existing active finger, then regards both as an identical multipath and does not act on the new multipath. New Multipath Verification: RFM assigns a RAKE finger to a new multipath if there is an idling RAKE finger available and designate it as a candidate finger. The candidate fingers channel estimation metric will be tested once per time slot for a Minimum RAKE Hold Time (e.g. 15 time slots). If all the tests are larger than that of an active RAKE finger by a pre-set Minimum RAKE Substitution Ratio (e.g. 3dB), replace the old active finger with a newly verified RAKE finger. The verification has to be done for all the new multipaths.
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4.

Operation of RAKE Finger Management

5.

6.

Finger Tracking Function: The RFM checks the output of channel estimation metric of each active RAKE fingers and evaluate whether to keep or drop a RAKE finger from the active finger set. The metric can be tested once per time slot for a pre-set time duration (e.g. 15 time slots). If all the tests fall below a pre-set threshold, the RFM drops the finger. The finger tracking function has to check all the active fingers. The RAKE finger management function will be done, for example, once per frame (15 time slots). All the parameters mentioned above have to be optimized through simulation and field test. The procedures mentioned above is based on the assumption that the cost of false alarm is much higher than miss detection.
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Hardware Functions Partitioning of Baseband Signal Processing

59

DSP and FPGA Partitioning

In early stage of prototype design, baseband signal processing is usually realized by Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). To fully exploit the unique characteristics of the DSPs and the FPGAs, the digital signal processing algorithms are usually partitioned in such a way that those requiring high speed repetitive operations and simple control are run on the FPGAs, while those requiring intensive computations and more elaborate control are run on the DSPs. Most of the time, the algorithms that run on the DPS are those operate at symbol rate and the algorithms that run on the FPGAs are those operate at chip rate.
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Algorithms Run on the DSPs

Channel estimation. Maximal ratio combining. Rake finger management. Tracking. SIR measurement. Power control. Interleaving/De-interleaving. Rate matching/de-matching. CRC generation attachment and detection.
61

Algorithms Run on the FPGAs

Square root raised filtering. Coarse synchronization (acquisition). Spreading/De-spreading. Scrambling/de-scrambling. Channel encoding/decoding.
Including Viterbi decoding and Turbo decoding. Operated at symbol rate. can also be implemented in DSP.

62