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Rohit.

Kumar Roll No: 520776763 BCA 2nd Semester BC0040 01 Computer Organization and Architecture Question 1 - Explain the working of Central Processing Unit (CPU) of a computer. Ans. CPU or Central Processing Unit is the heart and brains of every computer. Many of us do not know what importance it has on the whole performance of a computer. How many of you have wondered, what are the basic functions of CPU? Why it is important to have a good cooling system to keep the CPU at right temperatures? Why it is so important to keep the CPU from overheating The Brains of the Computer Well, as I have mentioned, the CPU is similar to human brain. Every single operation that you do with your computer is processed in CPU. The performance of your computer is based on simple mathematical operations. CPU is the device, that controls all the operations. Let's say we are using a calculator to add two numbers. The numbers are entered from your keyboard. The keyboard controller turns all the information you have entered into the binary code. Binary code consist of sequences of 0 and 1. All this information is sent to the registry and after then it is transferred to the CPU. The CPU has integrated ALU (Arithmetical Logical Unit). This unit is responsible for all mathematical and logical operations. So, your request to add two numbers comes to the CPU. Then it is transferred to the ALU. ALU adds the binary numbers and returns the answer to the CPU. CPU transfers the answer for output device. Adding two numbers is very simple example but it basically illustrates the functions of the CPU. Every single step you perform on your computer is in one way or another connected to your CPU. So it is very important to keep your processor on a good form. Overheating can be critical factor that can lead to system's fail. Primary functions of a CPU As it was mentioned before, CPU process instructions. Instructions are taken in process of decoding various data from programs. CPU has to implement 4 basic functions during instruction cycle: fetch, decode, execute, store. Fetch All the instructions are stored in memory. Each instruction has is address. The processor takes this address number from the program counter. Program counter is

responsible for tracking what instructions CPU should execute next. So fetching basically means taking the instruction from the memory. Decode CPU understands instructions, that are written in Assembly programming language. All the programs, that must be executed, are translated to Assembly instructions. Different CPUs understand different instructions, so Assembly code must be decoded into binary instructions which are understandable to your CPU. This step is called decoding. Execute During the procedure of instruction execution, tree things can be done. Firstly, CPU can do some calculations. To execute calculations ALU is used. Secondly, CPU can move data from one memory location to another. And thirdly, CPU can jump to different address if it is needed. So basically, one of those three options is executed during this step. Store CPU must give some feedback after executing the instruction. The output data is written to the memory. In this phase program counter is incremented.

Question 2 - How is the memory system of computer classified? Explain. Ans. Memory system of a computer can be broadly classified into four groups. Internal Memory Internal memory refers to a set of CPU registers. These serve as working memory, storing temporary result during the computation process. They form a general purpose register file for storing the data as it processed. Since the cost of these registers is very high only few registers can be used in the CPU. Primary memory It is also known as main memory, which operates at electronic speed. CPU can directly access the program stored in the primary memory . main memory consist of large number of semiconductor stored cells. Each cell is capable of storing one bit of information. Word is a group of these cells. Main memory is organized so that the contents of one word, containing n bits, can be stored or retrieved in one operation Secondary Memory

This memory type is much larger in capacity and also much slower than the main memory. It stores system programs, large data files and the information which is not regularly used by the CPU. When the capacity of the main memory is exceeded, the additional information is stored in the secondary memory. Information from the secondary memory is accessed indirectly though the I/O programs that transfer the information between the main memory devices are magnetic hard disk and CD-ROMs. Cache Memory The performance of a computer system will be severely affected if the speed disparity between the processor and the main memory is significant. The system performance can be improved by placing a small, fast acting buffer memory between the processor and the main memory. This buffer memory is called as cache memory. Cost of this memory is very high.

Question 3 - Explain the different type of computer architectures. Ans. The three most popular computer architectures are: 1. The Stuck Machine 2. The Accumulator Machine 3. The load / Store Machine The Stuck Machine: A stuck machine implements a stack with registers. The operands of the ALU are always top two registers of the stack and the result from the ALU is stored in the top register of the stack . the advantage of stack machine is that it can shorten the length of instructions since operands are implicit. This was important when memory was Expensive (20-30 years ago). Now, in java, it is important since we wants to ship executable (class files) over the network. The Accumulator Machine: An accumulator machine has a special register, called an accumulator, whose contents are combined with another operand as input to the ALU with the result of the operation replacing the contents of the accumulator. In fact, many machines have more than one accumulator Pentium: 1,2,4 or 6(depending on how you count) MC68000: 16 The Load/store Machine: Registers: Provide faster access but are expensive.

Memory: Provide slower access but is less expensive.

A smaller amount of high speed memory (expensive), called a register , is provided for frequently accessed variables and much larger but slower memory (less expensive) is provided for the rest of program and data. This is based on the principal of locality at a given time, a program typically accesses a smaller number of variables much more frequently than other. The machine loads and stores the registers from memory. The arithmetic and logic instruction operate with registers, not main memory, for the location of operand. Since the machine addresses only a small number of registers, the instruction field to refer to a register (operand) is short; therefore, these machines frequently have instructions with three operands: Add src 1 , src 2 , dest .

Question 4 - Draw the block diagram of Intel 8085 CPU organization and explain the different flag bits supported by the 8085 CPU. Ans. The CPU of 8085 is organized around a single 8-bit internal bus. Connected to the bus the following components. Accumulator : Used as a temporary buffer to store input to the ALU. It is also user visible and is addressed in some instructions. Temporary register : used as input for ALU which is other than Accumulator. Flag: these are nothing but condition codes. The result of ALU operations are related back in the register as flag.

The different flag bits supported by the 8085 CPU are: 1. Z : It stands for Zero flag. This bit is set when the result of ALU operation is zero 2. S : IT stands for sign flag . This bit is set when the result of ALU operation is negative. 3. P: It stands for Party flag. This bit is set when the result of ALU operation result is even parity. That is the result when expressed in binary has even number of ones in it. 4. CY : It stands for carry flag . this bit is set when the result of ALU operation results in overflow. 5. AC : It stands for auxiliary carry flag. This bit is set when the result of ALU operation Results in carry between Fourth and Fifth bit.

Question 5 - What are the different type of control lines used in computer? Explain about its function. Ans - Generally a "control" line is one which doesn't carry data, but carries a signal which controls the device. As an example, a simple old-style parallel printer interface will have seven or eight data lines, for sending the characters to be printed, plus several other lines to signal things like out-of-paper, ready-for-next-character, and so on. Once these arrive at the computer, however, they frequently become data. You might read the status port on the printer interface to find out if the out-of-paper line is active, for instance. For the processor itself, there are often control lines going out (like address strobes or read/write selectors) and / or going in (such as wait or interrupt signals). > And how we find out how many control line a computer > required while writting a machine code? But this makes me wonder if we're talking about the same thing. I know on a few assemblers I've used there are so-called "control lines" which are used to configure the aseembler. Most folks call them assembler directives or instructions (because they're instructions to the assembler itself rather than instructions destined for the computer). The ORG (origin) statement is a classic example used in a wide variety of assemblers. For x86 ones (our topic here) the ASSUME directive is a good example. Which sort of control line were you asking about? Or did you have something else entirely in mind .

Question 6 - Explain the steps to be followed for the addition of floating point numbers. Ans. The steps are required for the addition of floating point number are following: 1. The exponents of the two floating point numbers to be added are compared to find the number with the smallest magnitude 2. The significant of the number with the smaller magnitude is shifted so that the exponents of the two numbers agree 3. The significant are added 4. The result of the addition is normalized 5. Checks are made to see if any floating point exceptions occurred during the addition, such as overflow 6. Rounding occurs.

Question 7 - Explain Relative addressing mode and Base Register Addressing Mode with Example. Ans. Relative Addressing mode 1. A version of displacement addressing 2. R = Program counter, PC 3. EA = A + (PC) i.e. get operand from A cell from current location pointed to by PC Base Register Addressing Mode 1. A hold displacement 2. R holds pointer to base address 3. R may be Explicit or implicit e.g. segment registers in 80x86

Question 8 - What is memory interleaving? Explain it with necessary figures. Ans . Memory interleaving is a method to increase the speed of the high end microprocessors and it is even applicable to the hard disks too. It can be of 2 types: 2 way interleaving(using 2 complete address buses) & 4 way interleaving(using complete 4 address buses). There is a controller too that generates the addresses. CPU can access alternate sections of memory..while one section is busy processing upon a word at a particular location, the other section accesses the word at the next location....resembling overlapping!!! Non-interleaved Memory System In a non-interleaved memory system, all of the first bank of memory, bank 0, is addressed before the first long word of the second bank of memory, bank 1, all of bank 1 is addressed before the first long word of bank 2, and so on. Figure 1 shows this organization for two banks of N long words. (A long word is 4 bytes, or 32 bits, and is the natural unit of memory for the 68040.) Bank 0 Bank 1 ----------------- ----------------- | 0 | | N | ----------------- ----------------- | 1 | | N+1 | ----------------- ----------------- | 2 | | N+2 | ----------------- ----------------- ~ ~ ~ ~ ---------------- ----------------- | N-2 | | 2N-2 | ----------------- ----------------- | N-1 | | 2N-1 | ---------------- ----------------- ^ ^ | | ---------------------------- | v ----------------- | Buffer | ---------------- ^ | v System Data Bus ----------------------------------------------------Figure 1. Non-interleaved Memory Organization

The 68040 performs burst accesses (a single bus transaction that reads or writes 16 bytes in 4 adjacent long words) to move data between its caches and memory. All 16 bytes come from one bank of DRAM in a non-interleaved memory system, so the time required to complete the transfer depends directly on the access time of the DRAM. Figure 2 shows an example of such a burst access. The time needed to access the 2nd, 3rd, and 4th long words is shorter because a feature of the DRAMs called __ Clock __ __| "page-mode __ |__| __ |__| __ |__| |__| access" __ |__| __ |__| is __ |__| __ |__| used. __ |__|

______________________________________________________ DRAM Accesses | 1st long word | 2nd lwd | 3rd lwd | 4th lwd | -----------------------------------------------------Figure 2 Non-interleaved Burst Access Timing

Interleaved Memory System In an interleaved memory system, there are still two physical banks of DRAM, but logically the system sees one bank of memory that is twice as large. In the interleaved bank, the first long word of bank 0 is followed by the first long word of bank 1, which is followed by the second long word of bank 0, which is followed by the second long word of bank 1, and so on. Figure 3 shows this organization for two physical banks of N long words. All even long words of the logical bank are located in physical bank 0 and all odd long words are located in physical bank 1.

Bank 0 Bank 1 ----------------- ----------------- | 0 | | 1 | ----------------- ----------------- | 2 | | 3 | ----------------- ----------------- | 4 | | 5 | ----------------- ----------------- ~ ~ ~ ~ --------------------------------- | 2N-4 | | 2N-3 | ----------------- ----------------- | 2N-2 | | 2N-1 | --------------------------------- ^ ^ | | v v ----------------- ----------------- | Buffer | | Buffer | ----------------- ---------------- ^ ^ | | v System Data Bus v ----------------------------------------------------Figure 3. Interleaved Memory Organization The interleaved memory configuration is designed to speed up 68040 burst accesses by as much as 30%. (The actual improvement depends on the system clock speed and the DRAM access time.) Since the four long words of a burst access are spread across two physical banks of DRAM, the individual accesses can be overlapped to hide part, or all, of the DRAM access time delay, as shown below in Figure 4.

__ __ __ __ __ __ __ __ __ __ Clock __| |__| |__| |__| |__| |__| |__| |__| |__| |__| _______________________________ | 1st long word | 3rd lwd | ------------------------------ DRAM Accesses ______________________________ | 2nd long word | 4th lwd | Figure That's it!!! Memory interleaving is a method to increase the speed of the high end microprocessors and it is even applicable to the hard disks too. It can be of 2 types: 2 way interleaving(using 2 complete address buses) & 4 way interleaving(using complete 4 address buses). There is a controller too that generates the addresses. CPU can access alternate sections of memory..while one section is busy processing upon a word at a particular location, the other section accesses the word at the next location....resembling overlapping!!! Non-interleaved Memory System In a non-interleaved memory system, all of the first bank of memory, bank 0, is addressed before the first long word of the second bank of memory, bank 1, all of bank 1 is addressed before the first long word of bank 2, and so on. Figure 1 shows this organization for two banks of N long words. (A long word is 4 bytes, or 32 bits, and is the natural unit of memory for the 68040.) 4. Interleaved Burst ------------------------------Access Timing

Bank 0 Bank 1 ----------------- ----------------- | 0 | | N | ----------------- ----------------- | 1 | | N+1 | ----------------- ----------------- | 2 | | N+2 | ----------------- ----------------- ~ ~ ~ ~ ---------------- ----------------- | N-2 | | 2N-2 | ----------------- ----------------- | N-1 | | 2N-1 | ---------------- ----------------- ^ ^ | | ---------------------------- | v ----------------- | Buffer | ---------------^ | v System Data Bus ----------------------------------------------------Figure 1. Non-interleaved Memory Organization The 68040 performs burst accesses (a single bus transaction that reads or writes 16 bytes in 4 adjacent long words) to move data between its caches and memory. All 16 bytes come from one bank of DRAM in a non-interleaved memory system, so the time required to complete the transfer depends directly on the access time of the DRAM. Figure 2 shows an example of such a burst access. The time needed to access the 2nd, 3rd, and 4th long words is shorter because a feature of the DRAMs called "page-mode access" is used. __ __ __ __ __ __ __ __ __ __ Clock __| |__| |__| |__| |__| |__| |__| |__| |__| |__| ______________________________________________________

DRAM Accesses | 1st long word | 2nd lwd | 3rd lwd | 4th lwd | -----------------------------------------------------Figure 2. Non-interleaved Burst Access Timing

Interleaved Memory System In an interleaved memory system, there are still two physical banks of DRAM, but logically the system sees one bank of memory that is twice as large. In the interleaved bank, the first long word of bank 0 is followed by the first long word of bank 1, which is followed by the second long word of bank 0, which is followed by the second long word of bank 1, and so on. Figure 3 shows this organization for two physical banks of N long words. All even long words of the logical bank are located in physical bank 0 and all odd long words are located in physical bank 1.

Bank 0 Bank 1 ----------------- ----------------- | 0 | | 1 | ----------------- ----------------- | 2 | | 3 | ----------------- ----------------- | 4 | | 5 | ----------------- ----------------- ~ ~ ~ ~ --------------------------------- | 2N-4 | | 2N-3 | ----------------- ----------------- | 2N-2 | | 2N-1 | --------------------------------- ^ ^ | | v v ----------------- ----------------- | Buffer | | Buffer | ----------------- ---------------- ^ ^ | | v System Data Bus v ----------------------------------------------------Figure 3. Interleaved Memory Organization The interleaved memory configuration is designed to speed up 68040 burst accesses by as much as 30%. (The actual improvement depends on the system clock speed and the DRAM access time.) Since the four long words of a burst access are spread across two physical banks of DRAM, the individual accesses can be overlapped to hide part, or all, of the DRAM access time delay, as shown below in Figure 4.

__ __ __ __ __ __ __ __ __ __ Clock __| |__| |__| |__| |__| |__| |__| |__| |__| |__| _______________________________ | 1st long word | 3rd lwd | ------------------------------ DRAM Accesses ______________________________ | 2nd long word | 4th lwd | Figure 4. Interleaved Burst Access Timing -------------------------------

Question 9 - Explain the two bus organization and its working principle.

Ans. Two Bus Organization: Figure shows interconnection of various computer units through two independent system buses. Here the I/O units are connected to the processor thought an I/O bus and the processor is connected to the memory thought the memory bus. The I/O bus consists of device address bus, data bus and control bus. Device address bus carries the address of the I/O unit to be accessed by the processor. The data bus carries a word from the addressed input unit to the processor and form the processor to the addressed output unit . the control bus carries control commands such START, STOP etc., from the processor to I/O unit and it also status information of I/O unit to the processor . memory bus also consists of a memory address bus (MAB) , data bus and control bus. In this type of inter-connection the processor completely supervises the transfer of information to and from the I/O units. All the information is first taken to the processor and from there to the memory. Such a data transfer is called as program controlled transfer.

Question 10 - How are numbers represented in computer system ? Explain any number representation briefly. Ans. Number Representations: Computer are built using logic circuits that operate on information represented by two valued electrical signals. We label the two value as 0 and 1; and we define the amount of information represented by such a signal as a bit of information , where bit stands for binary digit. The most natural way to represent a number in a computer system in by a string of bits, called a binary number. A text character can also be represented by a string of bits called character code. We will first describe binary number representations and arithmetic operations on these numbers, and then describe character representation. Non-negative Integers : The easiest number to represent are non-negative integers. To see how this can be done, recall how we represent number in the decimal system. A number such as 2034 is interpreted as: 2* But there is nothing special with the base 10, so we can just as well use base2. In base2, each digit value is either 0or 1, which can represent for instance by false and true, respectively. In fact , we have already hinted at this possibility , since we usually write 0 and 1 instead of false and true.

All the normal algorithms for decimal arithmetic have versions for binary arithmetic, except that they are usually simpler

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