Johannah Mae D.

Abestano Binary Pattern Detector Finite State Machine Finite State Diagram Detect pattern 01110

ECE 195

At state IDLE if the input is 0, then it goes to the first state, which is state 0. Otherwise, it remains in the IDLE state. At state 0, if the input is 0, it remains at state 0. However, if the input is 1, then it proceeds to state 1. At state 1 if the input is 0, then it goes back to state 0, else, if the input is 1, it goes to state 2. At state 2, if the input is 1, it goes to state 3, else it goes back to state 0. At state 3, if the input is 0, it goes to state 4, else it goes to state IDLE. At state 4, if the input is 0, it goes to State 0. Else, it goes to state 1. Thus completing the cycle of the state machine. Wave Form Diagram

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BinaryPatternDetector.v
`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MSU-IIT // Engineer: Johannah Mae D. Abestano // // Create Date: 07:37:37 02/01/2013 // Design Name: // Module Name: BinaryPatternDetector // Project Name: BinaryPatternDetector // Target Devices: Any // Tool versions: Any // Description: Detects binary pattern in the input stream which is 01110. // // Dependencies: N/A // // Revision: 0001 // Revision 0.01 - File Created // Additional Comments: N/A // ////////////////////////////////////////////////////////////////////////////////// module BinaryPatternDetector( clk, stream, rst, enable, detected ); /* PORT DECLARATION */ input clk; input stream; input rst; input enable; output detected; /* INPUT WIRES */ wire clk; wire stream; wire rst; wire enable; /* PARAMETERS */ // list of states. please refer to the FSM diagram in the // documentation of this code. parameter SS_IDLE = 6'b000001; parameter STATE_0 = 6'b000010; parameter STATE_1 = 6'b000100; parameter STATE_2 = 6'b001000; parameter STATE_3 = 6'b010000; parameter STATE_4 = 6'b100000; /* INTERNAL REGISTERS, NEITHER INPUT NOR OUTPUT */ // current state INTERNAL variable. neither OUTPUT nor INPUT,

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// just an internal variable to hold the current state of the // finite state machine. reg[5:0] current_state; reg[5:0] nxt_state; assign detected = ((current_state==STATE_4 && nxt_state==STATE_0) || (current_state==STATE_4 && nxt_state==STATE_1)); always@(posedge clk or negedge rst)begin if (rst) begin current_state <= SS_IDLE; end else begin current_state <= nxt_state; end end /* MAIN PROGRAM LOOP */ // the preceding code is heavily based on the finite state // diagram defined on the documentation of this code. always @(current_state or stream) begin if (enable && !rst) begin case (current_state) SS_IDLE: if (stream == 0) begin nxt_state <= STATE_0; end else begin nxt_state = SS_IDLE; end STATE_0: if (stream == 1) begin nxt_state <= STATE_1; end else begin nxt_state <= STATE_0; end STATE_1: if (stream == 1) begin nxt_state <= STATE_2; end else begin nxt_state <= STATE_0; end STATE_2: if (stream == 1) begin nxt_state <= STATE_3; end else begin nxt_state <= STATE_0; end STATE_3: if (stream == 0) begin nxt_state <= STATE_4; end else begin nxt_state <= SS_IDLE; end STATE_4: if (stream == 0) begin nxt_state <= STATE_0; end else begin nxt_state <= STATE_1; end default: nxt_state <= SS_IDLE; endcase end else begin current_state = SS_IDLE; nxt_state <= SS_IDLE; end end endmodule

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BinaryPatternDetector_tb.v
`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: MSU-IIT // Engineer: Johannah Mae D. Abestano // // Create Date: 07:40:04 02/01/2013 // Design Name: BinaryPatternDetector // Module Name: BinaryPatternDetector/BinaryPatternDetector_tb.v // Project Name: BinaryPatternDetector // Target Device: Any // Tool versions: Any // Description: Detects binary pattern in the input stream which is 01110. // // Verilog Test Fixture created by ISE for module: BinaryPatternDetector // // Dependencies: // // Revision: 0001 // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module BinaryPatternDetector_tb; // Inputs reg clk; reg stream; reg rst; reg enable; // Outputs wire detected; // Instantiate the Unit Under Test (UUT) BinaryPatternDetector uut ( .clk(clk), .stream(stream), .rst(rst), .enable(enable), .detected(detected) ); initial begin // Initialize Inputs. All variables are set to 0. clk = 0; stream = 0; rst = 1; enable = 0; // Wait 100 ns for global rst to finish #110; // Test inputs. Note the enable is 0. so the device should not detect even the // pattern is present. the device is simply turned off in this state. #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 1; #20 stream = 0; #20 stream = 0; #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 0; // Turn on the device by setting enable as 1 // and making sure reset is low. enable = 1; rst = 0; // Test stream input. The output detector switch should rise when the pattern // 01110 is detected. The output is low when the pattern is still not detected.

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// note that the device is turned on as noted by the previous comment. so the // device will detect patterns this time. #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 1; #20 stream = 0; // 1 #20 stream = 0; #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 0; #20 stream = 0; #20 stream = 1; #20 stream = 0; #20 stream = 1; #20 stream = 0; #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 0; #20 stream = 0; #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 1; #20 stream = 0; // 1 #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 1; #20 stream = 0; // 1 #20 stream = 1; #20 stream = 1; #20 stream = 0; #20 stream = 1; #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 0; #20 stream = 1; #20 stream = 0; // reset the device and turn off the device // at the same time. rst = 1; enable = 0; // note that the device is turned off based on the previous comment. so regardless // of data in the input stream. the device will not detect any pattern even if there // is any. #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 1; #20 stream = 0; #20 stream = 0; #20 stream = 0; #20 stream = 1; #20 stream = 1; #20 stream = 0; $finish; // Finish the simulation run. end // This provides the clock of the UUT. always begin #10 clk = !clk; end endmodule

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