Johannah Mae D.

Abestano Four Byte Pattern Detector

// Description: // // // // Detects binary pattern in the input stream which is: 8'h56 8'hAB 8'h89 8'h7F

ECE 195

Finite State Machine Diagram

At IDLE state, if the input is 56, then it FSM moves to STATE 0. However, if input is something else, it remains at IDLE state. At STATE 0, if the input is 56, it remains there, however, if the input is AB it proceeds to STATE 1, if not among both, the FSM goes back to IDLE state. At STATE 1, if the input is 89, then the FSM moves to STATE 2, else if the input is 56 then it goes back to STATE 0, however if the input is not 89 nor 56 then it goes back to IDLE state. At state 2, if the input is 7F, the FSM moves to state 3, else if the input is 56 the FSM moves to STATE 0, otherwise if neither of both, the it goes back to STATE IDLE. At STATE 3, if the input is 56, then the output is 1, and the FSM moves to STATE 0. However, if the input is something else, then the output is still 1 but the FSM moves to STATE IDLE. This completes the cycle of the FSM Machine. 1 of 11

Wave Form Views

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Source Code BytePattern_detector_tb.V

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MSU-IIT // Engineer: Johannah Mae D. Abestano // // Create Date: 07:37:37 02/01/2013 // Design Name: // Module Name: BytePattern_detector_tb // Project Name: BytePattern_detector // Target Devices: Any // Tool versions: Any // Description: Detects binary pattern in the input stream which is: // 8'h56 // 8'hAB // 8'h89 // 8'h7F // // Test bench with embedded stimulus. // Dependencies: N/A // // Revision: 0001 // Revision 0.01 - File Created // Additional Comments: N/A // ////////////////////////////////////////////////////////////////////////////////// module BytePattern_detector_tb; // Inputs reg clk; reg[7:0] stream; reg rst; reg enable; // Outputs wire detected; // Instantiate the Unit Under Test (UUT) BytePattern_detector uut ( .clk(clk), .stream(stream), .rst(rst), .enable(enable), .detected(detected) ); initial begin // Initialize Inputs clk = 0; stream = 0; // since the enable variable is 0, then the device is in the off state. rst = 1; enable = 0; // Wait 4 ns for global rst to finish #4; // turn on the device. enable = 1; rst = 0; #1; // at 2 units time interval, input these stream values. // OUT #2 stream = 8'hAA; #2 stream = 8'hBB; #2 stream = 8'hCC; #2 stream = 8'hDD; // 0

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#2 #2 #2 #2

stream stream stream stream

= = = =

8'h56; 8'hAE; 8'hAA; 8'h56;

#2 #2 #2 #2

stream stream stream stream

= = = =

8'hAB; 8'h11; 8'hBB; 8'hAB;

#2 #2 #2 #2

stream stream stream stream

= = = =

8'h89; 8'h22; 8'hCC; 8'h89;

#2 #2 #2 #2

stream stream stream stream

= = = =

8'h7F; 8'hD3; 8'hDD; 8'h7F;

// // // //

1 0 0 1

#2 stream = 8'hAE; #2 stream = 8'hAE; enable = 0; rst = 1; #2 stream = 8'hAE; #2 stream = 8'h11; #2 stream = 8'h22; #2 stream = 8'hD3; // 0 #2 stream = 8'h56; #2 stream = 8'hAB; #2 stream = 8'h89; #2 stream = 8'h7F; // 1 enable = 1; rst = 0; #2 stream = 8'h56; #2 stream = 8'hAB; #2 stream = 8'h89; #2 stream = 8'h7F; // 1 #2 stream = 8'hAE; #2 stream = 8'h11; #2 stream = 8'h22; #2 stream = 8'hD3; // 0 #2 stream = 8'hAA; #2 stream = 8'hBB; #2 stream = 8'hCC; #2 stream = 8'hDD; // 0 $finish; end // this block of code provides clock frequency for the device. always begin #1 clk = !clk; end endmodule

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Source Code BytePattern_detector.V

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MSU-IIT // Student: Johannah Mae D. Abestano // // Create Date: 07:37:37 02/01/2013 // Design Name: // Module Name: BytePattern_detector // Project Name: BytePattern_detector // Target Devices: Any // Tool versions: Any // Description: Detects binary pattern in the input stream which is: // 8'h56 // 8'hAB // 8'h89 // 8'h7F // Dependencies: N/A // // Revision: 0001 // Revision 0.01 - File Created // Additional Comments: N/A // ////////////////////////////////////////////////////////////////////////////////// module BytePattern_detector( clk, stream, rst, enable, detected ); input clk; input stream; input rst; input enable; output detected; // parameter settings for the current states. parameter SS_IDLE = 5'b00001; parameter STATE_0 = 5'b00010; parameter STATE_1 = 5'b00100; parameter STATE_2 = 5'b01000; parameter STATE_3 = 5'b10000; // paramter settings for the pattern of the input byte stream that must // be detected. parameter PATTERN_0 = 8'h56; parameter PATTERN_1 = 8'hAB; parameter PATTERN_2 = 8'h89; parameter PATTERN_3 = 8'h7F; // this is the input stream. declared as an 8bit wire. wire[7:0] stream; // this is the current state INTERNAL variable. This stores the current state // of the finite state machine. reg[4:0] state;

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reg[4:0] nxt_state; assign detected = ((state==STATE_3 && nxt_state==SS_IDLE) || (state==STATE_3 && nxt_state==STATE_0)); // the code that follows is heavily based on the finite state machine diagram // in the documentation of this project. please refer to the diagram and its // following discussion on its operation. always@(posedge clk or negedge rst)begin if (rst) begin state <= SS_IDLE; end else begin state <= nxt_state; end end always @(stream) begin if (enable) begin case (state) SS_IDLE: if (stream == PATTERN_0) begin nxt_state = STATE_0; end else begin nxt_state = SS_IDLE; end STATE_0: if (stream == PATTERN_1) begin nxt_state = STATE_1; end else if (stream != PATTERN_0) begin nxt_state = SS_IDLE; end else begin nxt_state = STATE_0; end STATE_1: if (stream == PATTERN_2) begin nxt_state = STATE_2; end else if (stream != PATTERN_0) begin nxt_state = SS_IDLE; end else begin nxt_state = STATE_0; end STATE_2: if (stream == PATTERN_3) begin nxt_state = STATE_3; end else if (stream != PATTERN_0) begin nxt_state = SS_IDLE; end else begin nxt_state = STATE_0; end STATE_3: if (stream == PATTERN_0) begin nxt_state <= STATE_0; end else begin nxt_state <= SS_IDLE; end

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default: nxt_state <= SS_IDLE; endcase end else begin state = SS_IDLE; nxt_state <= SS_IDLE; end end endmodule

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Wave View using Memory File

In this simulation the test bench receives data from an external memory file containing testbench data.

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Source Code BytePatternDetector_tb_mem.V

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 15:16:16 02/08/2013 // Design Name: BytePattern_detector // Module Name: C:/Users/Bangonkali/Downloads/BytePattern_detector/BytePattern_detector/BytePattern_detec tor_tb_mem.v // Project Name: BytePattern_detector // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: BytePattern_detector // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module BytePattern_detector_tb_mem; // Inputs reg clk; reg [7:0] stream; reg rst; reg enable; // Memory Blocks. Instantiate a memory space 8 bits wide and 92 // entries tall. reg [7:0] memory [92:0]; // the variable holding the number of memory entries to read from // an external file. integer mem_max; // a variable holding the current address of the memory being // pushed to the stream input. integer counter; // Outputs wire detected; // Instantiate the Unit Under Test (UUT) BytePattern_detector uut ( .clk(clk), .stream(stream), .rst(rst), .enable(enable), .detected(detected) ); initial begin

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// Initialize number of memory locations to read from memory.mem mem_max = 50; // make sure the initial memory iterator is set to 0. this is the // beginning address. counter = 0; // instantiate the reading of the memory and store data to memory // variable. $readmemh("memory.mem", memory, 0, mem_max); // Initialize Inputs clk = 0; stream = 0; rst = 1; enable = 0; // Wait 3 ns for global rst to finish #3; // turn on the device by setting enable to high and reset to low. enable = 1; rst = 0; // loop at each memory location. then at each address push value to stream at 2 time // units interval. for (counter = 0; counter < mem_max; counter = counter + 1) begin #2 stream = memory[counter]; end $finish; end // block of code provides clock source for the device under test. always begin #1 clk = !clk; end endmodule

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Source Code memory.mem AA 56 AB 89 7F AA 56 AB 89 7F 56 AB 89 7F 11 22 33 44 55 66 77 77 88 99 01 02 03 AA 56 AB 89 7F AA 56 AB 89 7F 56 AB 89 7F 11 22 33 44 55 66 77

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