Reg. No.

MANIPAL INSTITUTE OF TECHNOLOGY

Manipal University, Manipal 576 104
FOURTH SEMESTER B.E (E&C) DEGREE END SEMESTER EXAMINATION MAY 2010 SUBJECT: DIGITAL SYSTEM DESIGN AND HDL (ECE-206) (REVISED CREDIT SYSTEM) TIME : 3 HOURS MAX. MARKS: 50

Instructions to candidates Answer ANY FIVE full questions. Missing data may be suitably assumed.

1A. Draw the output waveform Z, for the circuit given in Fig Q1A. Write the necessary VHDL code also. 1B. Write the short notes on following i. PIP ii. LVT iii. BIDI 1C. Find the essential test vector and selection test vector for the given circuit in Fig Q1C, using fault table technique. (3+3+4) 2B. Write a VHDL sequential modelling program for 3 to 8 decoder with active low enable. 2B. In Fig Q1A implement the following function using respective blocks F1= (A XOR B XOR C) F2= (ACD+BCD+AB+BC) F3= F1+F2 i. Find the no. of CLBs and LUTs required to implement F3 ii. Show the SRAM contents of Xilinx XC 3000. iii. Draw the entire layout for ACT-1, PAL (three wide OR gate) and XilinxXC3000 with proper routing between different blocks. (4+6) 3A. Write a sequential VHDL code for a simple heater thermostat. The device can be modelled as an entity with 2 integer inputs. One that specifies the desired temperature and the another that is connected to a thermometer and one Boolean output that turns the heater on and off. The thermostat turns the heater on if the measured temperature falls below 2 degrees less than the desired temperature and turns the heater off if the measured temperature rises above 2 degrees greater than the desired temperature. 3B. Find the test vector for circuit given in Fig 3B using Path Sensitization technique. 3C. Explain different types of MGA or Gate Array Based ASICs. (4+2+4) 4A. Design a 1011 sequence detector using PROM and D-FF. Overlapping is allowed. 4B. Implement F= a + b + c + d using ACT-2 Logic Module and also write the structural VHDL code for it. (5+5) 5A. Find out the test vector for the circuit given in Fig 5A using Boolean difference technique.
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5B. Write the VHDL code for 8: 1 MUX using with-select statement. 5C. Explain ASIC design flow with necessary diagram.

(3+4+3)

6A. Find out the signature of the faulty (a S-A-0) and fault free circuit given in Fig 6A. 6B. Write the verilog code for 3 input NAND gate. 6C. Find the test vector using PODEM technique for S-A-1 fault at the input of gate U3 in Fig Q6C. (4+3+3)

Fig-Q1A

Fig-Q1C

Fig-Q2B

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Fig-Q3B

Fig-Q5A

Fig-Q6A

Fig-Q6C
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