SEE3223MicroprocessorSystems

2:68000Architecture
MuhammadMunimAhmadZabidi(munim@utm.my)

68000Architecture
Aims
Toreviewthethearchitectureofthe68000microprocessor.

IntendedLearningOutcomes
Attheendofthismodule,studentsshouldbeableto:
Brieyexplainthehistoryofmicroprocessorandthe68000family Describethetermprogrammingmodel Describetheprogrammervisibleregistersinthe68000 Describehowthememoryisaccessedinthe68000 Describeandusethethreesimplestaddressingmodesofthe68000:direct, absoluteandimmediate BeabletoaccessandunderstandtheinformaQonpresentedinthe68000 Programmer sReferenceManual

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68000/ColdFireBackground
MC68000introducedbyMotorolain1979. NotablesighQngs:
UsedintheSun,thersteverworkstaQon UsedintheMacintosh,rsteverGUIpersonalcomputer UsedinearlyversionsofPalmPilotPDA

Why68000forlearningmicroprocessors?
Powerful&simpleinstrucQonset SophisQcatedinterfacingcapabiliQes AbletosupporthighlevellanguageandoperaQngsystems Flatmemorymap(versussegmentedmemoryusedinIntel80x86) ThemostpopularPinacademia

Internally,MC68000has32bitdatapathsand32bitinstrucQons
interfaceswithexternalcomponentsusinga16bitdatabus.Soaprogrammer considersit32bitchipwhileasystemdesignerconsidersita16bitchip. Hencethe 16/32bitchip designaQon.

Theoriginal68000wasavailablein64bitDIPor68pinPLCC.

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68000/ColdFireVersions
68000familyhasmanyversions.
680x0means68000,68008,68010,68020,68030,68040and68060. Newerversionsare upwardcompaQble witholderversions. ThefamilyisalsoaecQonatelycalled68korMC68k. Mostcommonlyfoundmembersare68000,68020,CPU32andColdFire.

Thefamilyincludes16bitperipheralschips.
The68000canuse68000typeperipheralschipsforhigherperformanceorolder 6800typeperipheralsforlowercost.

ColdFireisthecurrentversion
RISC ied68000processorcore. Smaller,lesspowerusedthannormal68020. AColdFirechipisanembeddedprocessorwithintegratedperipherals YoucannditinsomeHPlaserjetprinters

Today,the68kfamilyismadebyFreescaleSemiconductors.
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68kProcessorFamily
48-pin 68008 * Data bus (bits) Address Bus (bits) Data cache (bytes) Instruction cache (bytes) Memory Management Unit Floating-Point Unit Max Speed (MHz) Performance (MIPS) 8 20 52-pin 68008 * 8 22 68000 8/16 ** 24 20 2 68010 * 16 24 68020 32 32 256 Off-chip 33 10 68030 32 32 256 256 On-chip Off-chip 50 18 68040 32 32 4096 4096 On-chip On-chip 40 44 68060 32 32 8192 8192 On-chip On-chip 75 110

* 68008 and 68010 are end-of-lifed (EOL) meaning no longer in production. ** Original 68000 has 16-bit bus. Current 68000 has selectable 8- or 16-bit bus.

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68000Hardware
SpecicaQons
32bitdataandaddressregisters 16bitdatabus 24bitaddressbus 14addressingmodes Memorymappedinputoutput Programcounter 56instrucQons 5maindatatypes 7interruptlevels Clockspeeds:4MHzto12.5MHz Synchronousandasynchronousdatatransfers

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Whatis Microprocessor Architecture

Forourpurposesthearchitectureisthesokwareorprogrammer s modelofthemicroprocessor
TheCPUregistersavailabletotheprogrammer ThebasicinstrucQonstheCPUcanperform ThewaystheseinstrucQonscanspecifyamemorylocaQon Thewaydataisorganizedinmemory HowtheCPUaccesses&controlsperipheraldevices

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68000ProgrammingModel

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68000Registers
Name Data registers Address registers Stack pointer Program counter Status Register Label D0-D7 A0-A6 Number 8 7 Size 32 bit 32 bit 32 bit 32 bit 16 bit Function Stores 8-/16-/32-bit data Stores 16-/32-bit pointers (addresses of data) Store a pointer to a group of data known as the stack. Also known as A7. Theres two stack pointers: USP and SSP. Contains the address of the NEXT instruction to fetch and execute Contains information on the results of the last instruction. Consists of the system byte and the condition codes register (CCR)
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SP

PC

SR

StatusRegisterGeneralIdea
Register Register

ALU

X N Z V C

F L A G S

Register

Status register stores an analysis of the last operation involving the ALU
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 SystemByte

Control/StatusRegister
Bit C V Z N X Meaning Set if a carry or borrow is generated. Cleared otherwise. Set if a signed overflow occurs. Cleared otherwise. Set if the result is zero. Cleared otherwise. Set if the result is negative. Cleared otherwise. Retains the carry bit for multi-precision arithmetic Systems responds to interrupts with a level higher than I 1 means CPU in supervisor mode, 0 means user mode 0 for normal operation, 1 to stop the CPU after EVERY instruction for runtime debugging

Onlymodiableissupervisormode Detailsinlatermodules

UserByte:CCR
Foruserlevelprograms BehaviordependsoninstrucQon
Byte Sistem
15 14 13 12 11 10 9 8 7

Byte Pengguna
6 5 4 3 2 1 0

I2 I1 I0

X N Z V C

CCR Carry oVerflow Zero Negative eXtend Interrupt Mask Supervisor Trace
S T

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68000DataSizes
Bit( binarydigit )
Smallestamountofdata 1bitstoreseitherbinary0orbinary1.

BCD( binarycodeddecimal )
4bitsthatrepresentsdecimal0to9 Usedbyonly3instrucQons

Byte
8bitsthatisprocessedasoneunit

Word
16bitsthatisprocessedasoneuni
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Longword
32bitsthatisprocessedasoneunit
Bait atas (MSB) 9 8 7 6 Bait bawah (LSB) 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Kata atas

Kata bawah

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ByteAddressing
BytescanbestoredinanyevenoroddlocaQon
Alamat 0 2 4 6 Alamat 1 3 5 7

000000 000002 000004

10101010 00011001

11000101 11110010

000001 000003 000005

bait 0 bait 2 bait 4 bait 6

bait 1 bait 3 bait 5 bait 7

FFFFFC FFFFFE Alamat genap

11001000 00011010

11111111 01010111

FFFFFD FFFFFF Alamat ganjil

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WordAddressing
Wordmuststoredateven addresses Alempttostorewordat oddaddressresultina trap Trap:recoverablecrash
Alamat 15 0 2 4 kata 0 kata 1 kata 2 0 Alamat 1 3 5

Contoh: ABCD16 disimpan di alamat 0.

00000016 1010 1011 1100 1101 0000001 16

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LongwordAddressing
Longwordcanbestoredat evenaddress Longwordrequirestwo memoryaccesses(tworowsin memorymap)
Alamat 15 0 2 4 6 8 kata panjang 0 kata panjang 1 0 Alamat 1 3 5 7 9

Contoh: ABCD123416 disimpan di alamat 0.

00000016 1010 1011 1100 1101 0000001 16 00000216 0001 0010 0011 0100 0000003 16

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RegisterTransferLanguage(RTL)
AsimplenotaQontodescribetheoperaQonscarriedoutbyCPU clearlyandunambiguously
WewilluseittodescribethefuncQonofinstrucQon

100 [M(4)] [M(4)] = 100 [M(4)] 25 [PC] 4 [M(4) 100+[M(4)]

means #100 or the number 100 means contents stored in memory location 4 means memory location 4 contains #100 means load number 25 into memory location 4 means load number 4 into PC means add #100 to contents of location 4 and save (This slide falls in the good to know category.)
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InstrucQonSet
ThecompletelistofinstrucQonsisknownastheinstrucQonset InstrucQonsarecategorizedaccordingtobasicoperaQon performed:
Datatransfer ArithmeQc Logic Shiks&rotates BitmanipulaQon BCD ProgramControl SystemControl

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BasicInstrucQonSet
Mnemonic ABCD ADD AND ASL ASR Bcc BCHG BCLR BRA BSET BSR BTST CHK CLR CMP DBcc DIVS DIVU EOR EXG EXT JMP JSR LEA LINK LSL LSR Meaning Add decimal with extend Add binary Logical AND Arithmetic shift left Arithmetic shift right Branch conditionally Bit test and change Bit test and clear Branch always Bit test and set Branch to subroutine Bit test Check register with bounds Clear operand Compare Decrement and branch conditionally Exclusive OR Unsigned divide Jump to subroutine Exchange registers Sign extend Jump to effective address Logical shift left Load effective address Link stack Signed divide Logical shift right Mnemonic MOVE MULS MULU NBCD NEG NOP NOT OR PEA RESET ROL ROR ROXL ROXR RTE RTR RTS SBCD Scc STOP SUB SWAP TAS TRAP TRAPV TST UNLK Meaning Move source to destination Sign multiply Unsigned multiply Negate decimal with extend Negate No operation One's complement Logical OR Push effective address Reset external devices Rotate left Rotate right Rotate left through extend Rotate right through extend Return from exception Return and restore Return from subroutine Subtract decimal with extend Set conditionally Stop processor Subtract binary Swap data register halves Test and set operand Trap Trap on overflow Test Unlink stack

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 GenericinstrucQonformat

InstrucQonFormat
pointer to the instructions memory location operation code (MOVE, ADD, etc) size/width of operand (B,W,L) data used in the operation for program documentation
RTL [D0] 100 [D0] [M($100)] [D0] [D0] + [D1] [M(100)] D0 [DATA] 20 [PC] label
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<label> opcode<.size> <operands> <;comments>

<label> opcode <.size> <operands> <;comments>

Instruction MOVE.W MOVE.W ADD.W MOVE.W DATA DC.B BRA #100,D0 $100,D0 D1,D0 D1,100 20 LABEL

Operands
Operandscanbe
Registers Constants Memoryaddresses

Operandsspecifyaddressingmodessuchas
Dn:dataregisterdirect An:addressregisterindirect #n:immediate N:absolute Decimal:default Hexadecimal:prexedby$ Octal:prexedby@ Binary:prexedby% ASCII:withinsinglequotes ABC
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MOVE.W MOVE.W MOVE.W MOVE.W

D0, D1 (A0),D1 #10,D1 $1000,D1

Operandscanbespeciedinseveralformats

AddressingModes
Addressingmode:themechanismusedtocomputetheoperandaddress 68000hassophisQcatedaddressingmodes
Simpliesassemblerprogrammingbecauseitreducesthenumberstepsrequiredto specifyanaddress

68000has14addressingmodesbutreallyfallsinto6majorcategories.
Registerdirect Immediate Absolute ProgramcounterrelaQve Registerindirect Inherent
We ll cover the first three in this module. The rest will be covered later.

Eec2veaddress:theactualaddressusedbytheinstrucQon
Examples:
DataregisterD1intheprocessor Address$10000inmemory
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AsimpleinstrucQon
Format: CLR.s Example: CLR.W Eect:
D1 FE ED BE EF D1 FE ED 00 00

<ea>

D1

;Clears lower word of D1

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AnothersimpleinstrucQon
Format: MOVE.s Example: MOVE.W Eect:
D0 D1
12 78 34 56 56 34 78 12

<ea>,<ea>

D0,D1 ;Copy lower word of D0 to D1

D0 D1

12 78

34 56

56 56

78 berubah 78

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RegisterDirectAddressing
EecQveaddress:oneofthe8dataregister(D0D7) Thesimplestaddressingmode SourceordesQnaQonofanoperandisadataregisteroranaddress register.
Thecontentsofthespeciedsourceregisterprovidethesourceoperand. Similarly,ifaregisterisadesQnaQonoperand,itisloadedwiththevalue speciedbytheinstrucQon.

Examples:
MOVE.B SUB.L CMP.W ADD D0,D3 A0,D3 D2,D0 D3,D4 Copy the source operand in register D0 to register D3 Subtract the source operand in register A0 from register D3 Compare the source operand in register D2 with register D0 Add the source operand in register D3 to register D4

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RegisterDirectAddressing
The instruction indicates the data register MOVE.B D0,D1

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D0 D1

The source operand is data register D0

The MOVE.B D0,D1 instruction uses data registers for both source and destination operands
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RegisterDirectAddressing
MOVE.B D0,D1

The effect of this instruction is to copy the contents of data register D0 in to data register D1
25 25 D0 D1

ShortinstrucQons(needonly3bitstospecifyoneof8dataregisters) Fastbecausetheexternalmemorydoesnothavetobeaccessed.

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ImmediateAddressingMode
EecQveaddress:thememoryaddressimmediatelyfollowingtheinstrucQon word Indicatedbya#symbolinfrontofthesourceoperand. Canbeusedonlytospecifyasourceoperand. TheactualoperandformspartoftheinstrucQon. Animmediateoperandisalsocalledaliteraloperand. Canonlybeusedasasourceaddressingmode.ThedesQnaQonofthedatamust alsobespeciedbythedesQnaQonaddressingmode. TIP: Veryusefultoloadconstants(valuesthatneverchange).

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ImmediateAddressingMode
TheinstrucQonMOVE.B#4,D0usesaliteralsourceoperandandaregister directdesQnaQonoperand The literal source operand, 4, is part of the instruction

MOVE.B #4,D0

4
The

D0

The destination operand is a data register

effect of this instruction is to copy the literal value 4 to data register

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D0

AbsoluteAddressingMode
EecQveaddress:thememorylocaQonspeciedbytheinstrucQon Indirectorabsoluteaddressing,theinstrucQonprovidestheaddressoftheoperandin memory. Directaddressingrequirestwomemoryaccesses.TherstistoaccesstheinstrucQonand thesecondistoaccesstheactualoperand.

TIP: Mostaddressesarespeciedinhexsothe $ hexsymboliscommonlyfoundwhen memoryaccessesareinvolved Example: CLR.W $2000

clearswordlocatedataddress2000hex.

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AbsoluteAddressingMode
M em ory

MOVE.B 20,D0

20

42

42

D0

The effect of MOVE.B 20,D0 is to read the contents of memory location 20 and copy them to D0
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Bytes,Words,andLongwords
D3

1234 1235 1236 1237

1234 1235 1236 1237

1234 1235 1236 1237

MOVE.B $1234,D3
[D3(0:7)] [M($1234)]

MOVE.W $1234,D3
[D3(0:15)] [M($1234)]

MOVE.L $1234,D3
[D3] [M($1234)]

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AddressRegisterIndirectAddressing
EecQveaddress:thememoryaddressspeciedbytheaddress registercontainedintheinstrucQon TheinstrucQonspeciesoneofthe68000 saddressregisters;for example,MOVE.B(A0),D0. Thespeciedaddressregistercontainstheaddressoftheoperand. Theprocessorthenaccessestheoperandpointedatbytheaddress register. Example:

CLR.W

(A0) clears located in memory, specified by A0.

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RegisterIndirectAddressing(ARI) Mode
ThisinstrucQonmeansloadD0withthecontentsofthelocaQon pointedatbyaddressregisterA0
Memo r y

A0 10 00 1000

MOVE.B (A0),D0

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D0

The instruction specifies the source operand as (A0).

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RelaQveAddressingMode
EecQveaddress:calculatedbyaddingadisplacementtothePC Format:XXXXorXXXX(PC) Contoh:

BRA

*+2

The branchalways instrucQontransferscontroltoaninstrucQon2bytes ahead.The * charactermeans currentposiQon .

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InherentAddressingMode
EecQveaddress:inprocessorregister(CCR,SR,SP,USP,SSPor PC)ormemorybutnotindicatedintheinstrucQon Format:usuallynooperand Example:

RTS

Takes4bytesfromthe topofstack andloadsitintothePC.InvolvesPC,SP andmemory.

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MachineinstrucQon
EachinstrucQonisatleast1word,atmost5words. Therstwordisknownastheopera6onword,whichdetermines:
OperaQonrequired Datasize:byte,wordorlongword LengthofthecompleteinstrucQon Wheretonddata(eecQveaddress)

ThemethodofinstrucQonencoding(howainstrucQoniswrilenin binary)iscomplex!

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VariableLengthInstrucQons
Notonlyisthe68000instrucQonformatcomplex,thenumberof bytesinaninstrucQonalsovaries.
Address $4000 $4002 $4004 $4006 $4008 $400A $400C $400E $4010 $4012 $4014 $4016
Op-word operands

OP-word MOVE.W #1234,$543210

33FC

Operand1
1234

Operand2
0054 3210

$33FC $1234 $0054 $3210 $D082 $0003 $0005 $4EF9 $0030 $0008 $4E70

ADD.L ORI.B JMP

D2, D0 #5,D3 ($300008)

D082 0003 4EF9 0005 0030 0008

RESET

4E70

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AddressingModeEncoding
Addressingmodeisencodedusing6bitswithinaninstrucQon. ForasingleeecQveaddressinstrucQon,theaddressingmodeislocatedinbits 05.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Kata operasi

Mod

Daftar

Mod ! 000 ! 001 ! 010 ! 011 ! 100 ! 101 ! 110 ! 111 ! 111 ! 111 ! 111 ! 111 !

!Daftar !rrr ! !rrr ! !rrr ! !rrr ! !rrr ! !rrr ! !rrr ! !000 ! !001 ! !010 ! !011 ! !100 !

!Mod alamat ! ! ! ! ! !Daftar data langsung ! ! ! !Daftar alamat langsung ! ! !Daftar alamat tak langsung (ARI) !ARI dgn pascatokok ! ! ! !ARI dgn prasusut ! ! ! !ARI dgn ofset ! ! ! ! !ARI dgn ofset dan indeks ! ! !Mutlak pendek ! ! ! ! !Mutlak panjang ! ! ! ! !PC relatif dgn ofset ! ! ! !PC relatif dgn ofset dan indeks ! !Terdekat ! ! ! ! !

!Sintaksis !Dn !An !(An) !(An)+ !-(An) !N(An) !N(An,Xm) !$XXXX !$XXXXXXXX !N(PC) !N(PC,Xm) !#$XXXX
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MachineFormatforMOVEInstrucQon
TheMOVEinstrucQonismostheavilyused.
Generally,themostcommonlyused68000instrucQonsareencodedinfewerbits. MOVEisencodedbyonlytwobits(bit15:14=00)

TheeecQveaddressencodingisslightlydierentforthedesQnaQonoperand The68000isaprimeexampleoftheCISC(ComplexInstrucQonSetComputer) Example:MachinecodeforMOVE.WD7,D0

Machine language

0011 0000 0000 0011

MOVE.W D7,D0

0011 opkod

000000 kendalian2

000111
[D0(0:15)] [D7]

kendalian1

RTL 239

15

14

13

12

11

10

Opcodes
9 8 7 6 5

Bit 15, 14, 13, 12 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Operation MOVE Byte MOVE Long MOVE Word Miscellaneous ADDQ / SUBQ / Scc / DBcc Bcc MOVEQ OR / DIV / SBCD SUB / SUBX (Unassigned) CMP / EOR AND / MUL / ABCD / EXG ADD / ADDX Shift / Rotate (Unassiggned) 240

Summary
Registerdirectaddressingisusedforvariablesthatcanbeheldinregisters Literal(immediate)addressingisusedforconstantsthatdonotchange Direct(absolute)addressingisusedforvariablesthatresideinmemory Theonlydierencebetweenregisterdirectaddressinganddirectaddressingis thattheformerusesregisterstostoreoperandsandthelalerusesmemory ForFurtherInfo:
Motorola68000FromWikipedia,thefreeencyclopedia:
hlp://en.wikipedia.org/wiki/68000

CPUWorldMotorola68000microprocessorfamily:
hlp://www.cpuworld.com/CPUs/68000

68000Programmer sReferenceManual
hlp://www.freescale.com/les/archives/doc/ref_manual/M68000PRM.pdf

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