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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO.

2, FEBRUARY 2001

285

A Model of the Stress Induced Leakage Current in Gate Oxides


Luca Larcher, Student Member, IEEE, Alessandro Paccagnella, Member, IEEE, and Gabriella Ghidini
AbstractA new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress. Index TermsModeling, MOS capacitors, simulation, stress-induced leakage current, ultrathin SiO2 .
Fig. 1. Schematic band diagram of a MOS structure. The actual band structure (thin line) is compared with our new double box model (thick line).  and  are the equivalent barrier heights seen by electrons tunneling from the cathode into the trap and from the trap to the anode, respectively; E is the ground electron energy level at the cathode; E is the energy lost by electrons during trap-assisted tunneling; x is the trap distance from the cathodic interface.

I. INTRODUCTION HE STRESS INDUCED leakage current (SILC), namely the excess low field current across a thin gate oxide after a high electric field stress, is a major concern for the long-term reliability and the scaling of the tunnel oxide in nonvolatile memories [1]. Various quantitative models of SILC have been proposed in literature, differing by some features of the underlying physical mechanisms. Early models described SILC in a pragmatic way, by using a FowlerNordheim expression with a reduced barrier height acting as a fitting parameter, hence no insight on the physics of the process was available. One of the first SILC models based on a detailed physical description has been proposed in [2], [3], assuming a phonon assisted tunneling process as the conduction mechanism. inelastic trap assisted tunneling (TAT) appears now as the conduction mechanism of choice to describe SILC [4][8]. The low-field excess current can be found also in thin oxides after exposure to ionizing radiation. This radiation induced leakage current (RILC) displays electrical characteristics that are quite similar to those of SILC [9], [10]. In this work, we propose a new quantitative model of SILC, based on the double-box approximation of the oxide band structure proposed in [11], which noticeably simplifies the mathematics, required to solve the TAT problem. In this way it has

been possible to evaluate the density and the electrical characteristics of the traps involved in the tunneling process for various oxide thickness, stress and measurement polarities, and stress levels. II. THE MODEL Our model aims to describe the SILC as a TAT mechanism, which we considered as an inelastic tunneling of electrons coming from the conduction band at the cathode [4][6], [12]. The contribution of electrons coming from the Si valence band resulted negligible, in accordance with the experimental evidence proposed in [6]. The starting point is the double-box approximation of the oxide band structure (see Fig. 1) [11]. In the following, we will refer for simplicity to the positive V), where the bulk Si is the cathode and the injection ( poly-Si gate is the anode. The TAT can be described as a two step process: first, the electron tunnels from the cathode to a trap, which is aligned in energy with the electron in Si; then, the electron tunnels out from the trap toward the anode after having lost the energy [4][6], [13]. The oxide layer is divided into two constant energy regions, corresponding to the two rectangular boxes separated by the stressinduced trap, which is represented by the deep rectangular well in Fig. 1. No net charge is present inside the oxide layer. Each rectangular box replaces the corresponding trapezoidal barrier seen by the tunneling electron. The equivaand of the rectangular boxes are lent barrier heights (1) (2)

Manuscript received January 26, 2000; revised July 7, 2000. This work was supported in part by CNR-Italy, Progetto Microelettronica 5%. The review of this paper was arranged by Editor G. Baccarani. L. Larcher is with the Dipartimento di Scienze dellIngegneria, Universit di Modena e Reggio Emilia, 41100 Modena, Italy. A. Paccagnella is with the Dipartimento di Elettronica e Informatica, Universit di Padova, 35131 Padova, Italy (e-mail: paccag@dei.unipd.it). G. Ghidini is with the Central R&D/ST Microelectronics, 20041 Agrate Brianza, Italy. Publisher Item Identifier S 0018-9383(01)00768-7.

00189383/01$10.00 2001 IEEE

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 2, FEBRUARY 2001

is the silicon/oxide interface barrier ( eV), is the electron ground energy in Si, is the trap distance from the is the electric field within the oxide. Si/SiO interface, and Each of the tunneling steps has its tunneling time constant, and , which are inversely and proportional to the correspondent tunneling probability, , respectively [13]:

(3)

(4) , and are the electron effective masses in the oxide, in the substrate, and in the poly-Si gate, respectively. , , and are the electron wave-vectors in Si, in the gate, in the first and second oxide box, and in the trap, respectively. The electron tunneling probability via an oxide trap , in is proportional to since both events must occur in sequence [13]. By integrating , over the oxide thickness, we obthe TAT current, : tain the SILC analytical expression
Fig. 2. Negative (V < 0) and positive (V > 0) currentvoltage characteristics of a MOS capacitor (t = 4:4 nm, area = 10 cm ) after a positive CCS (J = 10 mA/cm , N = 5:8 1 10 electrons/cm ). Thick lines: measurements; thin lines: simulations. The curves before stress are shown for comparison.

(5) is the electron flux incident on the Si/oxide interface, and are the density and the cross section of the oxide traps, respectively. III. RESULTS AND DISCUSSION To achieve the best agreement between simulated and experimental results, different trap distributions have been explored. Traps have been considered neutral when empty [3][6], [14]. The best matching between experiments and simulations has been found for a trap distribution Gaussian in energy and space, described by (6), as follows:

(6) is the distance of the center of the trap distribution from the is its width. is the center of the Si/SiO interface, and energetic trap distribution measured from the bottom of the SiO conduction band, with a finite width [5], [13]. is the peak trap density in oxide. Since a defect in the middle of the oxide layer features an associated TAT probability several orders of magnitude higher

than one close to the interfaces, the model is much more sensitive to traps close to the oxide center [5], [10]. For this reason, the Gaussian space distribution may just be an artifact of the model. In fact, by considering a trap distribution Gaussian in energy and uniform in space, the fit of experimental data is still pretty good, being the model blind to traps close to interfaces. and 5.2 SILC was measured on MOS capacitors ( cm and 10 cm ) after positive and neganm, area tive constant current stress (CCS), with stress currents density ranging between 0.1 mA/cm and 30 mA/cm , and cumulabetween 10 electrons/cm and 10 tive injected charge electrons/cm . A sample of the results is shown in Fig. 2. The total simulated gate current includes the SILC contribution, and the FowlerNordheim and the direct tunneling currents calculated as explained in [11]. The values of the trap distribution param, and ) are eters assumed in simulations ( listed in Table I for the different oxides and stress conditions. It is worth noting that the same trap distribution was used to obtain the simulated positive and negative curves. Agreement between experimental and simulation results is always a parasitic low-field leakage excellent. Only at very low contribution (independent on electric stress) appears, which has not been considered in our simulations. Further, we studied the CCS trap generation kinetics, and is shown as a function of for different stressing currents in Fig. 3. From our simulations it is not possible to exand separately but only the product term can tract be evaluated. By assuming as a constant the curves in Fig. 3 , which follow the saturating bedepict the kinetics of havior characteristic of SILC. The peak trap density increases due to the enhanced energy of the CCS injected elecwith trons. Instead, as reported in [10], the accumulation kinetics of the defects generated by irradiation are almost linear for var-

LARCHER et al.: STRESS INDUCED LEAKAGE CURRENT

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TABLE I TRAP PARAMETERS IN ELECTRICALLY STRESSED OXIDES, AS DEDUCED FROM FITTING THE EXPERIMENTAL CURVES FOR ALL STRESS CURRENT DENSITIES, J , AND CUMULATIVE CHARGE INJECTED DURING THE STRESS, N

IV. CONCLUSIONS In this work, we have proposed a model of SILC in thin oxides based on a simplified oxide band structure, from which we deduced an analytical expression of SILC. The model can successfully fit a variety of experimental curves, with a defect distribution Gaussian in space and energy. However, the model is poorly sensitive to traps close to interfaces, and the Gaussian spatial distribution may just be due to this limit. The trap distribution parameters are not affected by the stress level, indicating that the same defect types account for low and high intensity SILC. Hence, the SILC kinetics is related only to the increase of the oxide defect density with the injected charge during electrical stresses. While a saturating behavior is observed for CCS trap density, which can be described by a power law, the RILC one is linear, indicating no decrease of the defect generation rate even for RILC values exceeding the maximum SILC intensity measured before breakdown. ACKNOWLEDGMENT The authors would like to acknowledge comments and suggestions by Prof. P. Pavan of the Universit di Modena e Reggio Emilia. REFERENCES
[1] J. de Blauwe et al., SILC-related effects in flash-E PROMs-Part I: A quantitative model for steady- state SILC, IEEE Trans. Electron Devices, vol. 45, pp. 17511760, Aug. 1998. [2] K. Sakakibara, N. Ajika, M. Hatanaka, and H. Miyoshi, A quantitative analysis of stress induced excess current in SiO films, in IRPS Tech. Dig., 1996, p. 100. [3] K. Sakakibara et al., A quantitative analysis of time-decay reproducible stress-induced leakage current in SiO films, IEEE Trans. Electron Devices, vol. 44, pp. 10021007, June 1997. [4] S. Takagi, N. Yasuda, and A. Toriumi, Experimental evidence of inelastic tunneling and new I V model for stress-induced leakage current, in IEDM Tech. Dig., 1996, pp. 323326. [5] , A new IV model for stress-induced leakage current including inelastic tunneling, IEEE Trans. Electron Devices, vol. 46, pp. 348354, Feb. 1999. [6] J. Wu, L. F. Register, and E. Rosenbaum, Trap-assisted tunneling current through ultra-thin oxide, in IRPS Tech. Dig., 1999, pp. 396399. [7] P. E. Nicollian et al., Low voltage stress-induced leakage current in ultrathin gate oxides, in IRPS Tech. Dig., 1999, pp. 400404. [8] C. T. Liu et al., Intrinsic and stress-induced traps in the direct tunneling current of 2.33.8 nm oxides and unified characterization methodologies of sub-3 nm oxides, in IEDM Tech. Dig., 1997, pp. 8588. [9] A. Scarpa et al., Ionizing radiation induced leakage current on ultra-thin gate oxide, IEEE Trans. Nucl. Sci., vol. 44, pp. 18181825, 1997. [10] L. Larcher, A. Paccagnella, M. Ceschia, and G. Ghidini, A new model of radiation induced leakage current (RILC) in ultra-thin gate oxides, IEEE Trans. Nucl. Sci., vol. 46, pp. 15531561, 1999. [11] L. Larcher, A. Paccagnella, and G. Ghidini, Gate current in ultrathin MOS capacitors: a new model of tunnel current, IEEE Trans. Electron Devices, vol. 48, pp. 271278, Feb. 2001. [12] E. Rosenbaum and L. F. Register, Mechanism of stress-induced leakage current in MOS capacitors, IEEE Trans. Electron Devices, vol. 44, pp. 317322, Feb. 1997. [13] A. I. Chou et al., Modeling of stress-induced leakage current in ultrathin oxides with the trap-assisted tunneling mechanism, Appl. Phys. Lett., vol. 70, no. 25, pp. 34073409, 1997. [14] B. Ricc, G. Gozzi, and M. Lanzoni, Modeling and simulation of stressinduced leakage current in ultrathin SiO films, IEEE Trans. Electron Devices, vol. 45, pp. 15541560, July 1998. [15] A. Cester, A. Paccagnella, and G. Ghidini, Time decay of stress induced leakage current in thin gate oxides by low-field electron injection, Microelectron. Reliab., vol. 40, pp. 715718, 2000.

Fig. 3. N 1 MOS capacitors (t 10, and 30 mA/cm .

0 N characteristics extrapolated from simulations for = 4:4 nm, area = 10 cm ) after CCS with J = 3,

ious radiation sources, and no saturation appears even for very high radiation doses. Further, for the same oxide thickness RILC can be much higher than the maximum value of the CCS SILC reached before oxide breakdown. These results clearly demonstrate the different accumulation kinetics of oxide traps under electrical or radiation stresses, while trap distribution parameters after different stress types are quite similar. The different kinetics could be related to different generation mechanisms of the defects, due to the different energy of the electrons: few eV for electrical stresses, MeV for radiation stresses. During radiation stresses, positive and negative charges are injected in the oxide in equal amount, owing to the electron-hole pair generation mechanism. Instead, during electrical stresses many more electrons are injected in the oxide layer than holes (or hydrogen ions). Since electrons can anneal the SILC during post-stress electron injection [15], similar effects could occur even during the CCS, when the density of injected electrons is much higher than that of the positive back-injected charge, thus producing the saturating behavior of the trap generation kinetics. On the contrary, in case of radiation stresses, the balance between positive and negative charge injected in the oxide would limit the electron annealing effect, producing a quasilinear kinetics.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 2, FEBRUARY 2001

Luca Larcher (S98) was born in Cles (Trento), Italy, in 1972. He received the Laurea degree in electronic engineering from the University of Padova, Padova, Italy, in 1998. Since 1998, he has been pursuing the Ph.D. degree at the Department of Engineering Science, University of Modena and Reggio Emilia, Italy. His research activities are in the field of nonvolatile memory cells. Particularly, his interest are on the oxide reliability, the simulation of oxide leakage current, the modeling of E PROM and flash.

Alessandro Paccagnella (M97) was born in Padova, Italy, in 1958. He received the Laurea degree in physics from the University of Padova in 1983. After joining different Italian universities, he is now Full Professor of Electronics at the University of Padova. In the past, his research activity has been directed to the study of different aspects of physics, technology, and reliability of semiconductor devices, mainly on compound semiconductors. In relation to this activity, he spent some research periods at the University of California, San Diego, and at the IBM T. J. Watson Research Center, Yorktown Heights, NY. At present, he is working on the study of ultrathin MOS gate dielectrics, on the effects of plasma-based deposition and etching processes in CMOS components, and on the damage induced by ionizing radiation on MOS technologies and integrated circuits. He is co-spokeperson of the RD49 collaboration of CERN, Geneva, CH (Study of the Radiation Tolerance of ICs for LHC). He has co-authored more than 180 scientific publications, about 110 in international journals.

Gabriella Ghidini graduated in physics from the University of Parma, Italy, in 1979, and received the Ph.D. degree in physics in 1983 from the City College of New York. In 1983, she joined STMicroelectronics, Agrate Brianza, Italy, working in the Physics Group, Central R&D Department. In 1987, she moved to the Non-Volatile Memory Process Development Group, Central R&D, becoming the leader of the Dielectric Reliability Group. Her research activities include failure and wear-out mechanisms of all active dielectric of Eprom, flash EEPROM and E2PROM devices and the evaluation of new technologies for the future generations. She has published more than 35 technical papers in international journals and conferences.

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