High Bandwidth Low Noise Amplifier with improved stability over Radio Frequency range

Prashanth G UID: 3913834 gxxxx003@umn.edu Dec 18, 2008

Introduction:
The measuring appliance amplifier is a double-end input differentiator amplifier, besides the high accuracy, the high stable characteristic, its output zero reference voltage may establish willfully through the REF base pins voltage, this adjusted zero for us to float has provided the possibility. The AD620 input end has reaches as high as 109 the input impedance; Input offset voltage 30uV, output offset voltage 400uV. The input bias current is very low, usually is highest in 0.5nA does not surpass 2nA; When the gain is 100, gain error 0.15%; Increases 100:00 syntype rejection ratios to reach as high as 130dB; Input noise 9nV/, output noise 72nV/. , The AD620 temperature stability also is very except for this outstanding: The gain is bigger than 1:00, gain temperature coefficient for - 50ppm, input offset voltage and output offset voltage average temperature coefficient respectively be 0.3uV/ and 5.0uV/.

Fig: The AD620 finds its major usage in ECG systems

Here, we shall explore the internal working of the AD620 and try to emulate the characteristics of AD620.

We can start by analyzing the two stage Op amp in the circuit used above:

Identifying functional blocks in the two-stage op-amp circuit

1) We first note that the resistor R is the only passive element in this two-stage opamp circuit: the function of R is biasing, i.e. setting up a constant dc bias current Ib. This current is then is replicated at various other locations for biasing other amplifier stages through current mirrors. In the op-amp circuit of Fig.6.3, the bias current Ib is the input current for the current mirror with two outputs: N0 and N1.

2) N2 and P2 combined together form current mirrors, distributing Ib to the rest circuit. Here, the input side of the mirror is N0 are the two outputs of the mirror. Since N3 and P3 are sharing the same gate-source voltage, the driver source N0

can replicate the bias current Ib as needed for biasing throughout the rest of the circuit. Different aspect ratios W/L of the mirror output transistors with respect to the input transistor can be used to scale the bias currents as needed (more about this in the quantitative analysis later)

3) N1 and N0 form the input differential pair, which is also the input of the first gain stage. P0 and P1 form the current mirrors for the differential pair N0 and N1. This bias current is provided by the voltage source Vdd, which acts as a DC current source.

4) M6 is the common source gain stage and it is also the second gain stage, note that the input of this gain stage is at node 1 which is the gate of P3, the output of this stage is at node 2 which is the drain of M6 and M6 is biased from node 1. The source of M6 is directly connected to the DC supply voltage VDD and hence no signal component.

To approach analysis of complex circuits at the transistor level, we consider the general idea of visualizing the circuit as a combination of known, simpler functional blocks, and perform the analysis on these simpler functional blocks one by one, if possible.

Upon solving the circuit for DC bias, we get I DP 3 = ( n C ox / 2) * (W / L) P 3 (VGSP 3 Vth ) 2 Vdd I B R B VGSP 3 = VSS

Solving for the above equations gives us the bias voltage for the second stage of the circuit. The cascade two-port model of the differential amplifier with current mirror supply is given by the following small signal model analysis.

In the First stage: Polarity of Gm1 is inverted to reect reversal of input terminals ... which is done to make the overall gain positive for vd > 0
G m1 = g m1 Rout1 = ro 2 || ro 4

In Second stage:

Gm2 = gm5 Rout = ro5 || ro6 a vdo = (Gm1 Rout1 )(Gm2 Rout ) a vdo = gm1 (ro 2 || ro 4 ) gm5 (ro5 || ro 6 )

Transistor Sizing:

We shall size the transistor in order to maximize the Gm1 and maximize common mode input voltage. For the DC current, we shall assume that the reference current at the first stage to be 50 A. IREF=50A. We shall choose (W/L)P = 75 m and (W/L)N = 37.5 m. This transistor sizing would be uniform for all the P and N transistors.

The AD620:
Schematic:

The AD620 was created from the above discussed two stage Op amp and the schematic is shown above.

Characterization of AD620:
Transient Response of the circuit:

Slew Rate Calculation: The slew Rate of the amplifier used in the circuit is calculated to be 4.5V for a 5V rail to rail voltage. Below is the diagram for Slew Rate:

CMRR Measurement: The CMRR is measured by setting up the amplifier as shown in the diagram. The input voltage is slowly varied from 0V in steps of 0.1V. The corresponding Vout is recorded for the given Vin. Vout is then plotted versus Vin. The above result is plotted versus various frequencies.

The CMRR obtained from the circuit is as shown below.

The CMRR obtained was 113.5. Layout of the AD620 circuit:

Shown in the above figure is the layout for the AD620 with all the stages.

Bibliography:
David Johns and Ken Martin (1997). Analog Integrated Circuit Design. John Wiley & Sons. Kenington, Peter. B. (2000). High-Linearity RF Amplifier Design. Artech House. Razavi, B. (2000). Design of Analog CMOS Integrated Circuits. McGraw Hill. http://www.analog.com/en/other/militaryaerospace/ad620/products/product.html Wikipedia