Professional Documents
Culture Documents
Agenda
9:30 LPC2000 Technical Training Part I - Introduzione - LPC2000 devices and roadmaps dev tools. I nuovi dispositivi della famiglia LPC2300 e LPC2400. Novit per il 2007 Break - Presentazione dell'Architettura ARM7 (mappa di memoria, system control, peripherals) 12:30 Pranzo 13:30 LPC2000 Technical Training Part II - Inizializzazione delle periferiche di sistema PLL, Vector Interrupt Controller e USB - presentazioni di esempi con tool Keil e scheda di valutazione Keil Break - Implementazone dellarchitettura ARM7 nella famiglia LPC23/24 - Q&A 17:30 Chiusura
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LPC3000 LPC2000
ARM926EJ ARM7TDMI-S
10
16-bit XA
16-bit
6-Clock MX
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ARM926EJ CMOS90
Crolles2
ARM1156EJ CMOS65
Crolles2
0.5
0.4
0.35
90n
65n
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Standard Microcontroller
Strategy Summary
Develop Innovative and Cost Effective Products Focus on 16/32-bit market with wide range of ARM7 & ARM9 based products Expand the successful LPC Family approach: - New peripherals like USB, Ethernet, ....... Use highly competitive flash based processes: - 0.35 m and 0.18 m Flash in production - Shrink path down to 0.14 m - First products in 90nm in 2005 Introduction of innovative packages: - Chip scale packages like HVSON10, TFBGA256
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ARM Microcontrollers
NXP has developed a family of ARM-based Microcontrollers For - Low-Cost High Volume Applications With - Embedded Flash and SRAM - On-board AMBA-bus Peripherals (Adv. C Bus Architecture) - Real-Time Deterministic behavior (no Cache required) -High performance NXP specific Flash Memory matrix -and access design - Full Debug, Real-time Monitoring and Trace facilities To - Continue on from our successful 8-bit 80C51 Family - Enable new low-cost 16/32-bit Microcontroller-based applications
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R M 68 K
SH MI -7 PS Po XX X w er P SP C A R 80 C X 86 ST 20 +
0
0 20 20 20 20 06 7 20 05 20 04
20 01
03
0 20
02
99 19
ARM : Leading solution for Industrial / Automotive, CONFIDENTIAL Communications and General Purpose
98 19
D- Core has debug extensions M- Core has enhanced multiplier I- Core has Embedded ICE Macrocell S- Fully synthesis able
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2007 Released (28) UART(4) 2x AHB + Ethernet +Single p supply 3.3V Minibus 100 - 144 pins
UART(4), I2C(3) SPI(1), SSP(2), LV RTC, ADC, DAC, PWM(2), USB full I2C10/100 Ethernet, CAN(2), IRC
H2 06
/01
H1 2007
UART(2), I2C, USB SPI/SSP, LV RTC LPC21xx ADC(1-2), DAC 3V p.supply UART(2), I2C CAN(2)
Flash Security SPI(2), RTC
I2C
LPC2148 LPC2194 /01 LPC2138 /01 512K/32K+8K 256K/16K 512K/32K USB ADC(2), DAC CAN (4) ADC(2), DAC LPC2146 LPC2129 /01 LPC2136 /01 256K/32K+8K 256K/16K 256K/32K USB ADC(2), DAC CAN (2) ADC(2), DAC LPC2144 LPC2124 /01 LPC2134 /01 128K/16K+8K 128K/16K 256K/16K USB ADC(2), DAC ADC ADC(2), DAC LPC2119 /01 128K/16K CAN (2) LPC2114 /01 128K/16K ADC 64pins
UART(2), I2C SPI(2), RTC ADC, CAN
10b-ADC
Flash Security 1.8V and 3.3 V UART(2), + external bus
LPC2214 /01 Flash Security 256K/16K 1.8V and 3.3 V ADC +external bus LPC2212 /01
128K/16K ADC
LPC2378 512K/58K
Ethernet, USB, CAN, MiniBus, MMC
LPC2105 /01
128K/32K
LPC2294 /01
256K/16K CAN (4)
LPC2368 512K/58K
Ethernet, USB, CAN, MMC
LPC2104 /01
128K/16K
LPC2132 /01
64K/16K ADC, DAC
LPC2142
64K/16K+8K USB ADC, DAC
LPC2220
0K/64K ADC
LPC2292 /01
256K/16K CAN (2)
LPC2366 256K/58K Ethernet, USB, CAN LPC2364 128K/34K Ethernet, USB, CAN
LPC2468 512K/98K Ethernet, USB, CAN LPC2458 512K/98K Ethernet, USB, CAN
LPC2888
1M/64K USB HS
LPC2101/2/3
8/16/32K/Flsh 2/4/8KRam ADC,LV,RTC
LPC2131 /01
32K/8K ADC
LPC2141
32K/8K+8K USB ADC
LPC2210 /01
0K/16K ADC
LPC2290 /01
0K/16K CAN (2)
LPC2880
0M/64K USB HS
LPC3180
64K RAM, 32+32K Cache
48pins
UART(2), I2C(2), SPI, SPI/SSP, RTC, ADC
64pins
UART(2), I2C SPI, SPI/SSP, LV RTC ADC(1-2), DAC
64pins
UART(2), I2C SPI(2), USB, LV RTC ADC, DAC
144pins
UART(2), I2C SPI(2), RTC ADC
144pins
UART(2), I2C SPI(2), RTC ADC, CAN(2/4)
180 pins
Flex. Suppl. HS USB, Flex. Ext. Mem. LCDcontr.Interf .
320 pins
ADC, 2xI2C, 2xSPI, 7xUART,USBOTG.
Timing/features/packages of non released parts may CONFIDENTIAL change without prior notification Subject/Department, Author, MMMM dd, yyyy
SPI LPC3190 IIS interface Ethernet MAC controller LCD interface LPC24xx: ARM7 Ethernet (MII+RMII) USB FS Device USB Host/OTG LPC2458 2 x CAN Ext. Memory (SDRAM, SRAM) 96K SRAM
LPC3000 LPC3000 LPC3000 LPC3000 LPC2000 LPC2000 LPC2000 LCD LCD LCD
2007
Time
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Reset.1 bug fixed LPC2104/00 and LPC2105/00 are Indus. Temp. range qualified
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Parts Samples LPC2104FBD48/01 No LPC2105FBD48/01 No LPC2106FBD48/01 No LPC2106FHN48/01 No LPC2114FBD64/01 No LPC2124FBD64/01 No LPC2119FBD64/01 No LPC2129FBD64/01 No LPC2131FBD64/01 Yes LPC2132FBD64/01 Yes LPC2132FHN64/01 Yes LPC2134FBD64/01 Yes LPC2136FBD64/01 Yes LPC2138FBD64/01 Yes LPC2138FHN64/01 No LPC2194HBD64/01 No LPC2210FBD144/01 Yes LPC2290FBD144/01 Yes LPC2212FBD144/01 No LPC2214FBD144/01 No LPC2292FET144/01 No LPC2294HBD144/01 No
Status Dev Dev Dev Dev Dev Dev Dev Dev RFS RFS RFS RFS RFS RFS RFS Dev RFS RFS Dev Dev Dev Dev
RFS date H1/07 H1/07 H1/07 H1/07 H1/07 H1/07 H1/07 H1/07 Now Now Now Now Now Now Now H1/07 Now Now H1/07 H1/07 H1/07 H1/07
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Vdd
TMS
TDO
TCK
TDI
Trace Trace
System Clock
PLL PLL
Local Bus
22 II C C
GPIO GPIO
GPIO SCK
UART0 UART0
2 pins
UART1 UART1
8 pins
Timer0 Timer0
MAT0.0-2 CAP0.0-2
Timer1 Timer1
MAT1.0-3 CAP1.0-3
PWM PWM
PWM1 - 6
SCL
SDA
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Vss
X1
X2
LPC2101/2/3 Blocks
2/4/8Kb 8/16/32Kb
Bootloader, RealMonitor
Fast GPIO
TRST
SRAM SRAM
FLASH FLASH
TMS
TCK
TDI
TDO
EICE
ETM ETM
AHB Bus
AHB Bus
RTC Osc
GPIO GPIO
2C 2 2x xII2 C
SPI SPI
SPI/SSP SPI/SSP
UART0 UART0
UART1 UART1
Timer0 Timer0 Timer1 Timer1 Timer2 Timer2 Timer3 Timer3 32-bit 32-bit 32-bit 32-bit 16-bit 16-bit 16-bit 16-bit
3 x MAT0 4 x MAT1 3 x CAP0 4 x CAP1 3 x CAP2 3 x MAT2 4 x MAT3
GPIO
2 pins
MOSI SSEL
SCK MISO
SSEL
SCL
SDA
8 pins
AVDD
AVSS
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*Flash size:
LPC2119 LPC2129,94
128KB 256KB
LPC2119, LPC2129,LPC2194
RST X1
Package: LQFP64
Vdd AIN0 - 3
JTAG
10
E-ICE SRAM SRAM Controller Controller Flash Flash Controller Controller // MAM MAM
ETM ETM
AHB Bus
22 II C C
UART1 UART1
8 pins
UART0 UART0
8 pins
GPIO GPIO
GPIO
Timer0 Timer0
MAT0.0-3 CAP0.0-3
Timer1 Timer1
CAP1.0-3 MAT1.0-3
PWM PWM
PWM1 - 6
CAN1 CAN1
TD1 RD1
CAN2 CAN2
RD2 TD2
SCL
SDA
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Vss
X2
n: LPC2292 = 2 LPC2294 = 4
LPC2292, LPC2294
BLS3:0 CS3:0
144-Pin Packages
A23:0
E-ICE SRAM SRAM Controller Controller Flash Flash Controller Controller // MAM MAM
ETM ETM
AHB
Vectored VectoredInterrupt Interrupt Controller Controller AHB AHBto toVPB VPB Bridge Bridge
VPB
22 II C C
SPI0 SPI0
SPI1 SPI1
UART1 UART1
UART0 UART0
GPIO GPIO
Timer0 Timer0
MAT0.0-3 CAP0.0-3
Timer1 Timer1
MAT1.0-3 CAP1.0-3
PWM PWM
PWM1 - 6
CAN1 CAN1
...
CANn CANn
WE
OE
4 pins
4 pins
8 pins
8 pins
GPIO
SCL
SDA
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RDn
RD1
TDn
TD1
D31:0
RST
Vdd
JTAG
10
RT-Trace
Vss
X1
X2
TRST
Vdd
TMS
TDO
TCK
X1
TDI
Trace Trace
System Clock
PLL PLL
Local Bus
AHB
CS 3:0 A 23:0 BLS 3:0 OE,WE D 31:0
22 II C C
2xSPI/SSP 2xSPI/SSP
SSEL MOSI MISO SCK
UART0 UART0
2 pins
UART1 UART1
8 pins
ADC ADC
8 pins
GPIO GPIO
GPIO
Timer0 Timer0
MAT0.0-2 CAP0.0-2
Timer1 Timer1
CAP1.0-3 MAT1.0-3
X2
PWM PWM
PWM1 - 6
SCL
SDA
Package: LQFP144
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Vss
RTCK
TRST
Vdd
TMS
TDO
TCK
X1
TDI
Trace Trace
System Clock
PLL PLL
Local Bus
and AHB
32 kHz Vbat
2 2x C 2xII2 C
UART0 UART0
2 pins
UART1 UART1
8 pins
ADC0/1 ADC0/1
2x8 pins
DAC DAC
1-10-bit
GPIO GPIO
GPIO
Timer0 Timer0
MAT0.0-2 CAP0.0-2
Timer1 Timer1
CAP1.0-3 MAT1.0-3
X2
Package: LQFP64/HVQFN64
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PWM1 - 6
SCL
SDA
Vss
PWM PWM
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TRST
Vdd
TMS
TDO
TCK
X1
TDI
ETM ETM
VIC VIC
Local Bus
32 kHz Vbat
22 II C C0/1 0/1
DAC DAC
1-10-bit
UART0/1 UART0/1
Tx/RX 0,1 Modem pins (6)
Timer0/1 Timer0/1
CAP x 8 MAT x 8
X2
PWM PWM
SCL
SDA
SCK
64-pin LQFP
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LPC2142 64 KB 16 KB 1 x 6-chan
3.3V Single-Voltage Supply 32KHz RTC with Vbat input Brown Out Detect, Power On Reset User-code security Real-time Debugging & Trace ISP, IAP, Parallel Programmer Support Tiny Packages: LQFP64 (10 x 10 x 1.4 mm), HVQFN64 (9 x 9 x 0.85 mm)
2 x 16C550 2 x 16C550
(one with auto CTS/RTS plus fractional baud rate divisor)
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2kB of endpoint RAM for communication only (not general purpose) 8kB block of general purpose SRAM usable by USB DMA (LPC2148 only) USB controller has dedicated PLL (functionally same as other PLL) USB registers are accessed via the VPB bus, but the 8kB block is accessible via the AHB bus Customer can choose between the UP_LED (Good LinkTM) OR the CONNECT (Soft ConnectTM) functionality
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Each Channel has its own Result Register thus reducing CPU Interrupt Overhead by a factor of 8 ADCs can Operate in Burst Mode with autonomous signal acquisition ADCs can be synchronized (e.g. for simultaneous current & voltage measurement) and triggered by an input pin or Timer match
ADC Inputs
ADC Clock
(CLKS Bits)
1-8
Input Scan
(SEL Bits)
n-bit ADC
(n Clocks/Conv)
ADDR0
ADDR1
ADDR7
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Max. Control Buffer size. Max. Interrupt Buffer Size Max. Bulk Buffer Size Max. Isoch. Buffer Size DMA Capability
* Separate input/output
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LPC2880/88 Blocks
SRAM SRAM
64k TRST TMS TCK TDO TDI SEL
180 pins
AHB Bus
HS HSUSB USB With With DMA DMA
RTCX1 RTCX2
RTC Osc
IS IS In/Out In/Out
DATO, BCKO, DCLKO,WSO BCKI, WSI
LCD LCD
LCD Bus
I22 C
IC
SPI SPI
2x
(1)
Stereo audio in
Timer0 Timer0
MAT0.0-3 CAP0.0-3
Timer1 Timer1
CAP1.0-3 MAT1.0-3
SDA
MOSI
MISO
SCL
SSEL
SCK
DATI
LPC2800 Family
Advanced and Flexible Memory Capability: On-chip: 1Mbyte of Flash, 64KB of RAM, and 32KB of ROM External Memory Controller for SDRAM, NOR and NAND Flash, and SRAM 8KBytes of Cache for enhanced performance from external memory LPC2800 Peripherals: 480 Mbits/sec High-Speed USB device with on-chip PHY Multi-Media Card, I2S, and LCD controller interfaces General Purpose DMA ATA interface LPC2800 Power Supply sub-systems: On-chip High-efficiency Switching regulator and Linear Regulators allow: Operation from single AA(A) Battery cell (0.9 to 1.6V) Operation from 5V USB input
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64 KB SRAM
512 KB Flash
Test/Debug Interface
ARM7TDMI-S
Internal SRAM Controller Internal Flash Controller ARM7 Local Bus AHB Bridge AHB to Master Port AHB Bridge APB Divider
MII or RMII
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*I2S Interface
RXCLK, TXCLK RXWS,TXWS RXSDA,TXSDA SCK0 MOSI0 MISO0 FS/SSEL0 SCK1 MOSI1 MISO1 FS/SSEL1 MCICLK, MCIPWR MCICMD, MCIDAT3:0 TxD0,2,3 RxD0,2,3 TxD1 RxD1 DTR, RTS DSR, CTS, DCD, RI RX2, 1 TX2, 1 SCL0, 1, 2 SDA0, 1, 2
Ain7:0
2 KB Battery RAM Real Time Clock Watchdog Timer System Control UART1
RTC Oscillator
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Features: Core
72 MHz ARM7TDMI Advanced Vectored Interrupt Controller (32 vectors, 16 priorities) Single 3.3V power supply (3.0V to 3.6V).
On-chip DC/DC converter for internal 1.8V Processor wakeup from Power Down mode via any interrupt able to operate during Power Down mode (includes external & GPIO interrupts, RTC, Ethernet wakeup).
4 reduced power modes, Idle, Sleep, Power Down, and Deep Power Down. On-chip Power On Reset, and Brownout detect with separate thresholds for interrupt and forced reset. On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. 4 MHz internal RC oscillator that is the default system clock.
On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator.
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Advanced Vectored Interrupt Controller (VIC) 32 IRQ sources Emulation Trace Module supports real-time trace Low power - 4 reduced power modes including Deep Power Down
Ethernet USB Ext, DRAM SSP I2C(2) CAN (2) UARTS(2) ADC
More than 60% usage of bus bandwidth causes collisions Loaded system bandwidth at 72Mhz is 96% for application Conclusion: 1 AHB Bus is not sufficient Multiple Busses and concurrent DMA processing is required
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High-bandwidth peripherals on different AHBs will not overwhelm the CPU or other peripherals
Trace Signals Emulation Trace Module TRST TDO TMS TCK TDI
64 KB SRAM
512 KB Flash
Test/Debug Interface
ARM7TDMI-S
Internal SRAM Controller Internal Flash Controller ARM7 Local Bus AHB Bridge
AHB2 16 KB SRAM
AHB1
32 KB SRAM
512 KB Flash
Test/Debug Interface
PLL
ARM7TDMI-S
Internal SRAM Controller Internal Flash Controller ARM7 Local Bus AHB Bridge AHB to Master Port AHB Bridge APB Divider
System Clock
AHB2
Ethernet
RMII
16 KB SRAM
USB
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Power Options
Power options:
On-chip DC-DC converter supplies 1.8V power to all internal logic, except in the RTC power domain. 1.8V power can be supplied from off-chip for some pinouts.
Power reduction modes are entered via an encoding of the IDL and PD bits in PCON, plus an additional new power control bit.
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Idle Mode
CPU is halted, reducing power used by:
The CPU itself. Memories and their controllers used by the CPU. Internal buses used by the CPU.
Peripheral clocks and functions continue to run. All registers and memories retain their state. Wakeup from any enabled interrupt, or Reset.
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Sleep Mode
All clocks are stopped to the CPU and peripherals. If enabled, the main oscillator and PLL are shut down.
All dynamic operation of the device is suspended. The DC-DC converter remains operational. The Flash memory remains on, allowing for fast wakeup.
All registers and memories retain their state. Wakeup from any enabled interrupt that can occur without clocks, or Reset.
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All registers and memories retain their state. Wakeup from any enabled wakeup source that can occur without clocks, or Reset.
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Wakeup can only be accomplished by a chip reset or an Alarm interrupt from the RTC. During Deep PD mode, power may be removed from the entire device, except for the RTC.
Restoring power causes a POR.
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Ethernet wakeup
(portions of the Ethernet block receive clocks from the external PHY)
USB or CAN activity (pin state change) Brown Out Detect RTC Alarm
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Ethernet wakeup
(portions of the Ethernet block receive clocks from the external PHY)
USB or CAN activity (pin state change) Brown Out Detect RTC Alarm
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RTC Oscillator
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Includes NicheTask a cooperative multi-tasking scheduler. Supports InterNiche's Light Weight API and a Zero-Copy option. Single Ethernet interface with device drivers optimized for the LPC2300 and LPC2400 Example applications (TFTP Client, TFTP Server, HTTP Listener)
Source code is free to NXP customers License - Unlimited use with NXP LPC2000 and LPC3000 microcontrollers only
Support from Interniche at sales@interniche.com
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LPC24xx
LPC24xx features beyond those offered in the LPC23xx. More RAM Ethernet MII interface (in addition to RMII) USB Host and OTG functionality External Memory Interface with additional External Memory Controller circuitry Additional GPIO Additional PWM
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LPC24xx
Announcement on the web Datasheets by email (LogicPG@NXP.com) 2 Devices:
LPC2458: 512KB flash, 98KB SRAM, Ext bus (16-bit), TFBGA180 LPC2468: 512KB flash, 98KB SRAM, Ext bus (32-bit), LQFP208 & TFBGA208
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CPU subsystem
I-Cache 32kB D-Cache 32kB VFP9
ARM926EJ
Instr Data
Up to 1MB SRAM
(On-Chip Memory)
DMA Controller
A/D RTC
System Functions
Other Peripherals
Communication Peripherals
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Technology Announcement
First ARM9 family-based microcontrollers in 90nm technology Press release done on Feb 23th during the Embedded World Show Nuremberg: LPC3000 Family based on 90nm technology industrys first 90nm ARM9* familybased 32-bit microcontroller family. Based on NXP Nexperia platform using the ARM926EJ-S* core Features: Several power management benefits Peripherals such as integrated USB On-the-Go (OTG) and full USB Open Host Controller Interface (OHCI) host Multi-level NAND Flash interface Operating speed at 200MHz Standard communication peripherals like up to 7 UARTs, SPI, I2C, USB, real-time clock, Ethernet - to follow. Floating point Vector Coprocessor 100mW power consumption @200Mhz with all peripherals switched on
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10
ETM: Embedded Trace Macrocell
E-ICE (JTAG)
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Keil/NXP board for devices with ADC and optional CAN (LPC2129)
2x 9-pin D-type Serial for serial co. ports 2x 9-pin D-type Serial for CAN 8 status LEDs Switches for interrupt and Reset Potentiometer for ADC demos Price projection $149 with 16k compiler
(no time limit)
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PHYTEC phyCOREARM7/LPC229x
phyCORE-ARM7/LPC229x PCM-023-SK-2294 10/60 MHz, 1 MB SRAM, 2 MB Flash, 2 KB EEPROM, SMSC LAN91C111 10/100 Mbit/s Ethernet, JTAG interface $199.00 http://www.phytec.com/sbc/32bit/p clpc229x.htm
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Price: 199$
Two serial interfaces, a speaker, analog input (via potentiometer), two CAN interfaces, LCD, SD card interface USB, Ethernet, and eight LEDs make this board a great starting point for your next ARM project.
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for LPC2378
IAR Embedded Workbench with a 32KB version of the IAR C/C++ Compiler IAR PowerPac: 3 tasks (RTOS) and 1 file (Flash File System) evaluation version 20-state version of visualSTATE
lab i a Av
en e t th a le
Fe f do
ry a u br
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SD card Connector USB connector LCD Module 16MB SDRAM, 8MB Flash Headphone jack Price on Nohaus web site: 995$
http://www.nohau.com/emularm/lpc2800.html
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ARM Emulators
JTAG emulators
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http://www.ashling.com/datasheets/armtools.html
Jlink + Trace
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Debuggers
Pathfinder debugger for the LP2100
http://www.ashling.com/datasheets/armtools.html
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Debuggers
Chameleon Debugger
http://signum.com/Signum.htm?p=ARM.htm
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RealView
AsIDE
EWARM
Multi 2000
Vision3
CrossWorks
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Compilers
ARM Compiler
http://www.arm.com/devtools/soft_dev_tools? OpenDocument.
GHS Compiler
http://www.ghs.com/products/arm_development.html
IAR Compiler
http://www.iar.com/Products/?name=EWARM
GNU GCC
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ARM RTOS
http://www.freertos.org/
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RTOS Listing
eCos NicheTask ThreadX Pumpkin Salvo Clinux IAR,ARM Keil See www.uclinux.org Ashling
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RTOS Support
Nucleus from Accelerated Technology a Mentor company
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NXP
IAR:
Rowley :
Free lib: EFSL http://efsl.de (FAT12/16/32 file system with short file names)
Keil and IAR examples dont require any Windows USB class driver. Windows XP supports all mentioned class drivers. NXP supplies the Virtual COM driver for Windows XP, IAR supplies the .inf file for the CDC windows driver
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Keil
Supports Fat 16 8.3 file naming Part of RTL
IAR
Power PACK
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Customer Application
Init_USB() Defines device, interfaces, endpoints Open_File() Read_File() Write_File()
Windows FAT16/32 Filesystem APIs USB Mass storage class driver Window low-level HOST driver USB HOST
USB Mass storage class driver USB device low-level messages driver USB Device SD/MMC cards
Low Level Memory card driver Ex.: EFSL, HCC, IAR power Pack Keil RTX FS
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USB books
USB Design By Example
A pratical Guide to Building I/O devices John Hyde, Intel University Press
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LPC2000 forum
Started by Leon Heller, an engineering consultant from England: The NXP LPC2100 family of ARM MCUs is sufficiently different from other ARM variants that I decided that a forum dedicated to it would be useful. Direct URL http://groups.yahoo.com/group/lpc2000/ Founded Nov 17, 2003 Already about 4000 members!
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Application examples
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http://www.jandspromotions.com/philips2005/
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TAM-TAM
NoPC
Flash card
Charlie
Magnetometer
LAURIN
Ethernet Acquisition
TV-Oscilloscope
Distinctive Excellence
Buckymeter
Duux Babycall
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Why ARM?
Why NXP?
First ARM7TDMI supplier with on-board flash in 0.18 m process, with the largest ARM7 product portfolio Memory sizes from 8k up to 1M on-chip flash Highest flash performance with nearly zero wait states due to internal MAM (Memory
Accelerator Module)
Widest selection of devices and of the integrated peripherals: 4*CAN, 2*ADC, SPI, I2C) Lowest pin count and smallest packages available Price level allows to address mid/high end 16-bit applications, and high end 8 bit application
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Hands-On
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Hands-On Index
1. 2. 3. 4. 5.
Hands-On
Tools Setup Oscillator / PLL / MAM / GP I/O / Flash ADC Interrupts / Timer UART / CAN
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Hands-On
Compile Current File Make Project Rebuild Project (all) Open Options Dialog Start/Stop Debugging
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Hands-On
Reset Run Step into Halt Step over
Hands-On
Add New signal
Here: 10
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Hands-On
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Hands-On
Using JTAG/ULINK
Select Debug Tab Use ULINK ARM Debugger
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1. 2. 3. 4. 5. 6. 7. 8.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation Q&A
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Introduction of ARM6 family in 1991, VLSI initial licensee In April 1998 listed on the London Stock Exchange and Nasdaq
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1. 2. 3. 4. 5. 6. 7. 8.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation Q&A
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Bus Width
ARM7 is a 32-bit architecture
Data pathes and (ARM) instructions are 32 bits wide Von Neumann architecture
instructions and data use the same 32-bit data bus
Registers Address Bus Address Register Incr.
Mult.
Shifter
Thumb Decompression
Data Bus
*: from C code
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Thumb State
Set of instructions re-coded into 16 bits
Improved code density by ~ 30% saving program memory space
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= = =
3
Halfword Word
Halfword Word
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Processor Modes
ARM has seven operating modes
1. User 2. FIQ 3. IRQ unprivileged mode under which most applications run entered, when a high priority (fast) interrupt is raised general purpose interrupt handling
entered on reset or software interrupt instruction
4. Supervisor protected mode for the operating system 5. System 6. Abort 7. Undefined privileged mode using the same registers as user mode
(not in ARM architectures 1, 2 and 3)
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Registers (1)
An ARM core has 37 registers (32-bits wide) General purpose registers
1 program counter 30 general purpose registers
Status registers
1 current program status register 5 saved program status registers These registers are not all accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.
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Registers (II)
Depending on processor mode one of several banks is accessible. Each mode can access
the program counter r15 (PC) a particular r13 (stack pointer SP) a particular r14 (subroutine link register, LR) a set of r0-r7 registers, and a particular set of r8-r12 the current program status register (CPSR)
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Register Overview
User and System
r0 r1
FIQ
r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq (SP) r14_fiq (LR) r15 (PC) CPSR SPSR_fiq
IRQ
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_irq (SP) r14_irq (LR) r15 (PC) CPSR SPSR_irq
Supervisor
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_svc (SP) r14_svc (LR) r15 (PC) CPSR SPSR_svc
Abort
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_abt (SP) r14_abt (LR) r15 (PC) CPSR SPSR_abt
Undefined
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13_und (SP) r14_und (LR) r15 (PC) CPSR SPSR_und
r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (SP) r14 (LR) r15 (PC) CPSR
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In Thumb state, the high registers (r8 - r15) are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage
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Thumb state
r3 r4 r5 r6 r7
Low registers
Thumb
Thumb state
ARM State
State
High registers
r13 (SP) r14 (LR) r15 (PC) CPSR SPSR
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Reserved
Control bits
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Reserved
Control bits
Mode Bits
10000 10001 10010 10011 10111 11011 11111 User FIQ IRQ Supervisor Abort Undefined System
T Bit
Thumb mode (when set) ARM mode (when cleared)
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Exception
Exceptions result whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before attempting to handle an exception, the ARM7TDMI-S preserves the current processor state so that the original program can resume when the handler routine has finished.
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Exception Handling
Entering an exception the ARM core
saves the address of the next instruction in the appropriate LR
r15 (PC) PC + 4 or PC + 8 r14_<mode> (LR)
Control bits
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Exception Vectors
Vector Table
. . . FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset
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Multiple Exceptions
Exception priorities
When multiple exceptions arise at the same time, a fixed priority sytem determines the order in which they are handled
1. 2. 3. 4. 5. 6. 7.
Reset Data Abort (data memory access cannot be completed) FIQ IRQ Prefetch Abort (instruction memory access cannot be completed) Undefined Instruction SWI - Software Interrupt
(to enter supervisor mode)
highest priority
lowest priority
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Leaving Exception
To leave an exception, the exception handler must
copy SPSR back into CPSR
SPSR_<mode> CPSR
CPSR:
Control bits
1. 2. 3. 4. 5. 6. 7. 8.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation Q&A
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Instruction Set
All instructions are 32-bits long Many instructions execute in a single cycle Instructions are conditionally executed ARM is a load / store architecture
via registers => RISC
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Conditional Execution
Mnemonic EQ NE CS / HS CC / LO MI PL VS VC HI LS GE LT GT LE AL Equal Not equal Carry Set / Unsigned higher or same Carry Clear / Unsigned lower Negative Positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Signed greater than or equal Signed less than Signed greater than Signed less than or equal Always (normally omitted) Description
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Instruction Examples
Data processing instructions
SUB ADD ADDS r0, r1, #5 r2, r3, r3, LSL #2 r4, r4, #0x20
r0 := R1 - 5 r2 := r3 + (r3, LSL #2) r4 := r4 + 32 and set flags r5 := r5 + r6 if equal
ARM code can be combined with Thumb code for maximum flexibility
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Thumb Instructions
ARM instruction set 31 ARM instruction ARM instruction ARM instruction ARM instruction ARM instruction ARM instruction ARM instruction 0 Recoding Thumb instruction set 15 Thumb instruction Thumb instruction Thumb instruction Thumb instruction Thumb instruction Thumb instruction Thumb instruction 0
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Data Processing
Subset of ARM data processing instructions Not conditionally executed (but some update flags)
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Thumb code
0
001
10
Rd
8-bit immediate
Immediate value
31
1110
00
0100
0 Rd 0 Rd ARM code
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Rn
n: 0-15
31
BX
31 1 0
Destination address
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1. 2. 3. 4. 5. 6. 7. 8.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation Q&A
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ARM7TDMI-S
The ARM7TDMI-S is based on ARM7 core
3 stage pipeline Von Neumann architecture CPI ~1.9 T: D: M: I: S: Thumb instruction set includes debug extensions enhanced multiplier (32x8) with instructions for 64-bit results core has EmbeddedICE logic extensions fully synthesisable (soft IP)
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ARM7TDMI-S Core
Address Bus
Address Register
Incr.
Registers
Mult. Shifter
Data Bus
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Thumb only: Thumb instruction decompressed to ARM instruction Instruction decoded Registers read from Register Bank, Shift and ALU operations performed, Registers written back to Register Bank
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1. 2. 3. 4. 5. 6. 7. 8.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation Q&A
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RAM
16 bit wide
ARM core
Peripherals
I/O
RAM
32 bit wide
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AMBA
Advanced Microcontroller Bus Architecture
on-chip interconnect established, open specification framework for SoC designs enabler for IP reuse digital glue that binds IP cores together
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AHB
APB Bridge
APB
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1. 2. 3. 4. 5. 6. 7. 8.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation Q&A
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Decode
ThumbARM decompress ARM decode Reg. select Reg. read
Execute
Shift ALU Reg. write CPI: 1.9
ARM9TDMI
Fetch Decode
ARM or Thumb instruction decode Reg. decode Reg. read
Execute
Instruction Fetch
Shift + ALU
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4
SA-110 SA-1110
Improved ARM/Thumb Interworking CLZ Instruction Saturated maths DSP multiplyaccumulate instructions ARM1020E X-Scale
Jazelle
5T
5TEJ
5TE
ARM9EJ-S ARM7EJ-S
3
Early ARM architectures
4T
ARM9TDMI ARM940T
ARM9E-S ARM966ES
ARM926EJ -S
E: DSP-extensions
S: synthesizable
J: Java
: Core Architecture
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400
0.35 4.8mm2
(ARM 10)
0.18mm
ARM 11
100
0.35 2.1mm2
ARM 9...
0.25 1.0mm2
ARM 9E
0.18 < 0.5mm2
0.6 4.8mm2
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1. 2. 3. 4. 5. 6. 7.
ARM - The Company Architecture Instruction Set ARM7TDMI-S Systems Other ARM cores NXP Implementation
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NXP Implementation
1. 2. 3. 4. 5. 6.
Memory Addressing System Control Block Memory Accelerator Module (MAM) General Purpose I/O / Pin Connect Block Vectored Interrupt Controller Integrated Peripherals
Timer 0 / Timer 1, UART 0 / UART 1, IC, SPI, PWM, RTC, Watchdog, ADC, USB, CAN, Ethernet, SD, IIS, GPDMA
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RAM on AHB
1.0 GB
Reserved for On-Chip Memory 8KM ... 1MB On-Chip Non-Volatile Memory
0.0 GB
LPC213X
12K Boot Block 0x07 FFFF 0x07 CFFF
Active Exception Vectors Active interrupt vectors could 0x3F be from Flash, SRAM or boot 0x00 block. On reset the boot block vectors are always mapped to 0x0 LPC2100, 256k
Sector 26 Sector 22
4K 4k
Sector 21 32K Sector 15 32k Sector 14 32K Sector 11 32k Sector 10 32K Sector 9 32K Sector 8 32K Sector 7 4K ... Sector 1 4K Sector 0 4K
0x00 FFFF 0x00 7FFF 0x03 FFFF
LPC2100, 128k
8K Boot Block Sector 14 8K Sector 13 8K Sector 12 8K Sector 2 8k Sector 1 8K Sector 0 8K
0x0 0x01 FFFF
8K Boot Block Sector 16 8K Sector 10 8k Sector 9 64K Sector 8 64K Sector 7 8K Sector 2 8k Sector 1 8K Sector 0 8K
256k
0x03 FFFF
0x01 FFFF
0x0
0x0
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SRAM: 8, 16, 32 or 64 KB
0x4000FFFF
64KB SRAM
0x40007FFF
0x40003FFF
8KB SRAM
RAM Int Vect
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1. 2. 3. 4. 5. 6.
Memory Addressing System Control Block Memory Accelerator Module (MAM) General Purpose I/O / Pin Connect Block Vectored Interrupt Controller Integrated Peripherals
Timer 0 / Timer 1, UART 0 / UART 1, IC, SPI, PWM, RTC, Watchdog, Ethernet, SD, IIS, GPDMA
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System Control
Includes a number of important system features
Power Control Memory mapping configuration Oscillator PLL VPB (VLSI Pheriperal Bus) divider Reset (active low) Wakeup Timer External Interrupts
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Power Control 1
[PCON 0xE01FC0C0]
R/W
Idle mode - processor clock stopped, on-chip peripherals remain active, interrupts cause wakeup Power Down mode - oscillator and on-chip clocks stopped, wakeup by external interrupt
For example 5 mA with most peripherals powered down
PCON[1]
PD
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Power Control 2
When disabled, peripherals are switched off to conserve power Power Control for Peripherals Register PCONP 1 PCONP 2 PCONP 3 PCONP 4 PCONP 5 PCONP 7 PCONP 8 PCONP 9 ......
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[PCONP 0xE01FC0C4] Enable Timer0 Enable Timer1 Enable UART0 Enable UART1 Enable I2C Enable SPI Enable RTC
Each peripheral typically below 1mA
R/W
Boot Block
The uppermost Flash sector contains the Boot Loader
controls physical interface for programming and erasing the Flash supports ISP (In System Programming) mode for initial programming of customer code supports In-Application Programming in a running system under the control of customer software buffers an entire Flash line (512 bytes) at once to keep programming time to a minimum
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Exception Vectors
Vector Table . . . FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset
Valid user program key: Must contain a value that ensures that the checksum of all vectors is zero
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Boot Loader On-chip User Flash Memory 0x0000 003F 0x0000 0000
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Boot Loader On-chip User Flash Memory 0x0000 003F 0x0000 0000
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0xFFFF FFFF
4.0 GB
Boot Block (re-mapped from On-Chip Flash) Reserved for On-Chip Memory 16/32/64 KB On-Chip Static RAM
0x7FFF FFFF
2.0 GB
0x0000 0000
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R/W
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Programmable frequency multiplication PLL bypassed on reset PLL lock indicator can be used as an interrupt to connect the PLL once it is locked PLL programming requires a special feed sequence (like the watchdog) for safety
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XTAL1 Oscillator
FOSC
FCCO
2P
Divider Value VPB pclk Divider 1/2/4
M
Multiplier Value Default: 4
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[PLLCON 0xE01FC080]
PLL Enable PLL Connect
R/W
R/W
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[PLLFEED 0xE01FC08C]
Consecutive writes 0xAA then 0x55
WO
[PLLSTAT 0xE01FC088]
Readback for Multplier value "M" (M-1) Readback for Divider value "P" (1,2,4,8) Readback for PLL Enable bit Readback for PLL Connect bit * Reflects PLL Lock status
RO
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[VPBDIV 0xE01FC100]
cclk / pclk ratio 00: 4 01: 1 10: 2
R/W
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1. 2. 3. 4.
Memory Addressing System Control Block Memory Accelerator Module (MAM) General Purpose I/O / Pin Connect Block
Pin Connect Block / External Memory Controller
5. 6.
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32 bits needed with every clock Memory access time < 17ns @ 60MHz
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Flash Architecture
Flash is split into two blocks of 128 bits each
128 bits are accessed at once
Separate Branch Trail Buffer holds 128 bits of history of each block => 4-times speed improvement for linear code; branches will cause a variable delay, depending on target address Additional Data Buffer for data accesses to Flash
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128 bit Prefetch Buffer 2 Branch Trail Buffer 2 128 bit (2x) Data Buffer Selection Data Bus (32 / 16 bit)
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MAM Registers
MAM Control Register
MAMCR 1:0 MAM mode control
[MAMCR 0xE01FC000]
00: MAM functions disabled
R/W
01: MAM functions partially enabled * 10: MAM functions fully enabled 11: reserved
* Only sequencial code via MAM
[MAMTIM 0xE01FC004]
000: reserved 001: MAM fetch is 1 clock cycle ... 111: MAM fetch is 7 clock cycles
R/W
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Hands-On Index
1. 2. 3. 4. 5.
Hands-On
Tools Setup PLL / MAM / GP I/O / Flash ADC Interrupts / Timer UART / CAN
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Hands-On
The PLL and MAM settings are part of the startup code Settings can be made using a convenient input mask Exercise: Setup the PLL to 60Mhz
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MAM Setup
Enabling the MAM for 60Mhz clock and 50ns Flash Setup MAM Fully Enable MAM Timing 3
3 * 17ns = 51ns
Hands-On
Explanation of MAM Register values
Partially Enable: Code fetches only Fully enable: Code and data fetches MAM Timing Number of clock cycles used for one flash memory access
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Hands-On
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Flash IAP
Project FlashSWInt Load and single step
Hands-On
Exercise: Change program to use address 0x10200 for storing the string
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1. 2. 3. 4. 5. 6.
Memory Addressing System Control Block Memory Accelerator Module (MAM) General Purpose I/O / Pin Connect Block Vectored Interrupt Controller Integrated Peripherals
Timer 0 / Timer 1, UART 0 / UART 1, IC, SPI, PWM, RTC, Watchdog, ADC, CAN
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LPC23/24 Up to 160 GPIO pins, all implemented as fast GPIOs, with 64 GPIO interrupts (plus 4 other external interrupts).
Shared with
Alternate functions of all peripherals Data/address bus and strobe signals for external memories
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The current state of the port pins is read from this register Writing "1" sets pins high, writing "0" has no effect Writing "1" sets pins low and clears corresponding bits in IOSET Port pin direction: 0 = INPUT 1 = OUTPUT
IOSET
IOCLR
IODIR
PINSEL0/1
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Conventional ARM GPIO is implemented on the APB peripheral bus Toggling speed of the GPIO is limited due to the 3-stage pipeline, AHB bridge and the APB bus
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10
Improving Speed
GPIO registers are now interfaced directly to the ARM7 Local bus Ports can now toggle every 2 clocks giving a clock period of cclk/4= 15Mhz This is a 3.5x speed increase Enables faster soft peripherals
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Fast GPIO
Special features GPIO registers accessed via ARM local bus in addition to conventional peripheral bus access Mask registers allow treating sets of port pins as a group, leaving other bits unchanged Local bus GPIO registers are now byte addressable Entire port value can be written in one instruction using the IOPIN register
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PINSEL2
Configuration of P1 (64/144-pin devices) and P2, P3 (144-pin devices) Select availability of debug and trace ports on Port1 pins Controls use of address/data bus and strobe pins
devices) (144-pin
(144-pin devices)
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PINSEL0 21:20
P0.10
00: GPIO Port 0.10 01: RTS (UART1) 10: Capture 1.0 (Timer 1) 11: reserved
...
...
...
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External memory data lines External memory address lines Output Enable (active low) Byte Lane Select (active low) Write Enable (active low) Chip Select (active low)
Boot from 8-bit memory on CS0 16-bit memory on CS0 32-bit memory on CS0 Internal Flash memory
PINSEL2 27:25
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GPIO Exercise
Exercise: Modify the example to use a macro or function for LEDs Hint:
SET_LEDS(byte) LEDs are on Port 1, bits 16-23
Hands-On
Optional Exercise: Invent a display pattern indicating seconds and 125ms Examples:
Walking LED, or Bar indicator
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1. 2. 3. 4.
Memory Addressing System Control Block Memory Accelerator Module (MAM) General Purpose I/O / Pin Connect Block / Memory Controller Vectored Interrupt Controller Integrated Peripherals
Timer 0 / Timer 1, UART 0 / UART 1, IC, SPI, PWM, RTC, Watchdog
5. 6.
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O R
IntEnable
IntEnableClear
FIQ
FIQ
FIQ
FIQ
RawInterrupt
High Prio
VICVectorAddr 0 C P U
En Channel
...
IRQ 32 IntSelect
16/32 (LPC23/24)
VICVectorAddr 15/31
En Channel 5 0:4
VICVectorAddr VICVectorAdd 0
D[0..31]
IRQ D[ ]
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IRQ Interrupts
Vectored Vectored Interrupt Interrupt Controller Controller Timer Timer (Overflow) (Overflow)
Interrupt Channel Channel#4 #4 VIC Vector Address Channel Channel#16 #16 Exception Vector Table FIQ IRQ
ARM-Core
Main
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VICVectAddr4
VICVectAddr
ISR
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ISR
VICDefVectAddr
ISR
CODE
VICVectAddr
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Interrupt
VectorAddress = 0x1C
ISR
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Hands-On Index
1. 2. 3. 4. 5.
Hands-On
Tools Setup Oscillator / PLL / MAM / GP I/O ADC Interrupts / Timer UART / CAN
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Project: BlinkyIRQ
Load Project BlinkyIRQ Build and Debug Simulation
Use Logic Analyzer
gTimCnt loop
Hands-On
Peripheral window
Vectored Int. Contr.
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Hands-On
Test and debug in simulator using:
Performance Analyzer Signal Analyzer Peripheral GPIO window Peripheral Timer window Peripheral VIC window
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Interrupts
1.
Hands-On
Emul-ARM Evaluation System Embedded Workbench Flash ISP Utility LPC2106 Target Board (Nohau) (IAR) (NXP) (Nohau)
Tools Installation
Emulator/Debugger: Compiler: Flash Tool: Hardware:
2. 3. 4.
5. 6.
UART RTC
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Hands-On
(User Manual !)
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Hands-On
(Tools -> Seehau) (RUN -> Go or Button)
Start Seehau
Run project
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Hands-On
(Assembler!)
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Hands-On
Function
LEDs are changed whenever variable TimerIsUp=1 This variable is
set by Timer 0 interrupt routine after Timer 0 match cleared by main routine before LEDs are changed
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Hands-On
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Hands-On
(Tools -> Seehau) (RUN -> Go or Button)
Start Seehau
Run project Press SW4 Release SW4
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Hands-On
blinks LEDs
External IR 2 (SW4): stay in ISR until SW4 released Priorities External Interrupt > Timer SW4 blocks Timer 0 (LEDs control)
Main() Timer0_ISR() VICVectAddr1
ExtInt_ISR() VICVectAddr0
Hands-On
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Hands-On
!
Nested IR-Handler now save status and reenable further interrupts before entering ISR nested interrupts possible!
Main()
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Hands-On
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Hands-On
External Interrupt < Timer
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Hands-On
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Hands-On
Hands-On
ExtInt_ISR() VICVectAddr1
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Block
WDT -
Flag(s)
Watchdog Interrupt (WDINT) Reserved for software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match 0 -2 (MR0, MR1, MR2, MR3) Capture 0 - 2 (CR0, CR1, CR2) Match 0 -3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI)
VIC IR Source #
0 1 2 3 4 5 6
VIC IR Sources
LPC2104 LPC2105 LPC2106
UART 1
Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI)
PWM 0 I2C SPI PLL RTC System Control System Control System Control
Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) SI (state change) SPIF, MODF reserved PLL Lock (PLOCK) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2)
8 9 10 11 12 13 14 15 16
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Block
Flag(s)
... External Interrupt 3 (EINT3) A/D Converter ORed CAN Acceptance Filters CAN 1 Transmitter CAN 1 Receiver CAN 2 Transmitter CAN 2 Receiver CAN 3 Transmitter CAN 3 Receiver CAN 4 Transmitter CAN 4 Receiver
add'l
VIC IR Source #
... 17 18 19 20 21 22 23 24 25 26 27
VIC IR Sources
LPC2114/24 LPC2119*/29* LPC2194** LPC2210/12/14LPC2 290**/92** LPC2294***
... System Control A/D * CAN * CAN * CAN ** CAN ** CAN *** CAN *** CAN *** CAN *** CAN
plus more flags for UART0, Timer1, Capture 0 - 3 (CR0, CR1, CR2, CR3)
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FIQ: 12 (25) cycles, 200ns (416ns) @ 60MHz First Vectored IRQ (assuming no FIQ pending): 26 (39) cycles, 433ns (650ns) @ 60MHz Default IRQ Vector (assuming no other IRQ pending): 42 (55) cycles, 700ns (916ns) @ 60MHz
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1. 2. 3. 4. 5. 6.
Memory Addressing System Control Block Memory Accelerator Module (MAM) General Purpose I/O / Pin Connect Block Vectored Interrupt Controller Integrated Peripherals
Timer 0 / Timer 1, UART 0 / UART 1, IC, SPI, PWM, RTC, Watchdog
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RTC
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PCLK
RTC oscillator
MUX
Clock generator
Time Counters
Comparators
Alarm Registers
Interrupt Generator
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Running
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IAP programming
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In-Application Programming (IAP) In-System Programming (ISP via NXP Boot Loader, UART0) In-System Programming (through LPC HW macro cells/ and custom software protocol) Parallel programmer
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ADC
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A/D Converter
Features
10 bit successive approximation analog to digital converter Multiplexed inputs
4 pins 8 pins (64-pin devices) (144-pin devices)
Power down mode Measurement range 0V ... 3V Minimum 10 bit conversion time: 2.44 S Burst conversion mode for single or multiple inputs Optional conversion on transition on input pin or Timer Match signal Programmable divider to generate required 4.5MHz from VPB clock
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Measurement range of 0 V to 3 V
Separate voltage pins for analogue 3V supply (V3A) and analogue ground (VSSA)
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ADC Inputs
7 6 5 4 3 2 1 0 ADDR0
10-bit ADC
(11 Clocks/Conv)
ADDR7
V3A
VSSA
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ADC Inputs
ADC Clock
(CLKS Bits)
1-8
Input Scan
(SEL Bits)
n-bit ADC
(n Clocks/Conv)
ADDR0
ADDR1
ADDR7
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DAC
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LPC213x DAC
Digital-to-Analog Converter (DAC)
10-bit resolution DAC with a buffered output Output from Zero Volt to Reference Voltage Selectable Conversion speed vs. power
Settling time 1us, up to 350uA In 1024 steps Last output value is held as long as DAC is on
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Hands-On Index
1. 2. 3. 4. 5.
Hands-On
Tools Setup Oscillator / PLL / MAM / GP I/O ADC Interrupts / Timer UART / CAN
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Project: BlinkyADC
Load Project BlinkyADC Build and Debug Simulation
Use Logic Analyzer Peripheral windows
GPIO P1 ADC -> modify voltage
Hands-On
Run on hardware
Verify change of AD values with potentiometer
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UART
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1010010110110110
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UART0 / UART1
UART 0 Interface
TxD0 RxD0
TxD1 CTS DTR RxD1 DCD RI RTS DTR
UART 1 Interface
UART0 / UART1
Register locations conform to 550 industry standard UART Built-in Baud Rate Generator
16-bit baud rate generator clock divisor made from 2 8-bit divisor registers: DLM (MSB), DLL (LSB) Required baud rate: pclk / (16 x Divisor*) (* if the Divisor is 0x0000, it is treated as 0x0001.) Fractional baud rate generator (LPC214x, LPC2101-2-3)
Error Detection
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Word Length Select: 5, 6, 7 or 8-bit characters Stop Bit Select: 1 or 2 stop bits Parity Select: Odd or Even parity Supports 6 modem control signals
CTS, RTS, DCD, DSR, DTR and RI functions are selectable Note: On 48-pin devices UART 0 has Tx and Rx pins only
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IIC
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I2C Interface1
SDA SCL
interface on LPC213x
2nd I2C
I2C Interface2
SDA SCL
400Kbits/sec
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I2C Bus
Fast-I2C compliant bus interface
configurable as Master, Slave, or both multi-master bus bi-directional data transfer between masters and slaves up to 400kb/s arbitration between simultaneously transmitting masters without corruption of serial data on the bus serial clock synchronization allows devices with different bit rates to communicate via one serial bus programmable clock rate
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SPI Interface
MISO MOSI
SPI Interface
SPICLK SS
SPI Bus
Compliant with Serial Peripheral Interface (SPI) specification Combined SPI master and slave function Maximum data bit rate of 1/8 of the peripheral clock rate Programmable clock polarity and phase for data transmit/receive operations No. of SPI channels:
1 2 (48-pin devices) (64/144-pin devices)
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SSP
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MISO1 MOSI1
SSP Interface
SCK1 SSEL1
SSP Interface
Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire bus Supports multiple slaves and master on the bus but at any point of time only one master and slave can communicate 8-Frame FIFOs for both Transmit and Receive Frame sizes can be from 4 bits to 16 bits
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USB
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USB 2.0
Since USB is a standard doesnt that make all microcontrollers with USB the same? NO!! Architectural choices and implementation details make a big difference in performance and ease of use. The LPC2148 is a high performance USB device.
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Introduction to USB
An Auto-configuring Plug-and-play Serial Bus
PC
HOST/HUB
HUB Monitor
Phone
Kbd
All data communication is initiated and regulated by the Master; peerto-peer not allowed USB 2.0 is the latest version of USB (downward compatible)
Mic
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Approved on 11/23/99 by the USB Core team 12 Mbps bus Full-speed (12 Mbps) Low-speed (1.5 Mbps) Standard A connector and standard B connector
Original USB 2.0 specification released on April 27, 2000 480 Mbps bus High-speed (480 Mbps) Full-speed (12 Mbps) Low-speed (1.5 Mbps) Backward compatible with USB 1.1 New mini-B connector
Supplements the 2.0 specification Connects peripherals directly to each other New mini-A connector and mini-AB receptacle
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R1
Hub Port 0
or
D+ R1 DR1
D+
Untwisted, Unshielded
3 Meters Max. R1 = 15K ohms5% R2 = 1.5K ohms5%
R2
sb.org
www.usb.org
www.usb.org
www.usb.org
www.usb.org
www.us
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Device Layers
Function
Represents capability delivered by the device, The primary usage function, like mouse, audio output, printer, hub, etc.
Function
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Device Abstractions
End Point
Ultimate data source or sink at the device end Unique address, unidirectional, transfer characteristics Each endpoint is unidirectional and has a transfer type associated with its peripheral
Pipe
Association of endpoint with host SW owner
Interface
Collection of pipes Map to a capability Owned by exactly 1 software client More that 1 interface can be defined in a device
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Endpoints
Up to 32 (16 pairs) endpoints can reside within a device
All USB transfers are targeted to/from a device endpoint An endpoint is a buffer used to transmit or receive data
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Interfaces
Made of 0 or more pipes Has a client owner
Accesses individual pipes Shares default pipe
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Pipes
Connect host memory buffer to endpoint FIFO Stream Type
No USB imposed data format Unidirectional
Message Type
USB imposed data format Bidirectional
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Function
a collection of Interfaces
Device
Buffers
No USB Format
Interface Specific
No USB Format
USB System
manages devices
USB Device
Endpoint Zero
a collection of endpoints
Data
Unspecified
USB Bus
SIE
SIE
USB Wire
Pipe, represents connection abstraction between two horizontal layers Data transport mechanism USB-relevant format of transported data
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Pipes Pipes
Endpoints Endpoints
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Communications Layers
Physical Packets Transactions
3 phases (token, data, handshake) Token phase has token packet sent by host
Always present Packet ID (PID) identifies transaction type
Transfers
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Transfers to Transactions
Interface Interface Pipe Pipe Pipe Interface Interface Pipe Interface Interface Pipe Pipe
Client Client SW SW
Transfer Transfer Manager Manager Transaction Transaction List List Transaction Schedule Transaction Schedule Executor Executor
Token Token Token Token
USB USB System System SW SW and and Host Host Controller Controller
Requirements, Limitations
Token Token
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Transaction
Transaction
Token Packet
Data Packet
Handshake Packet
PID Packet IDentifier (16 types) Body Depended on Packet type CRC Cyclical Redundancy Check used for error checking
PID
Body
CRC
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Frames
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Control
24 bytes (three 8-byte transactions) 832 (thirteen 64-byte transactions/frame) yes no no Configuration
Interrupt
0.8 bytes (8-bytes per 10 msec) 64 (one 64-byte transaction/frame) yes no yes Mouse, keyboard
Bulk
no support 1216 (nineteen 64-byte transactions/frame) yes no no Printer, scanner
Isochronous
no support 1023 (one 1023-byte transaction/frame) no yes yes Audio, video
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Slot
BULK BULK
SOF
Tx Line
Rx Line
(not to scale)
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Transactions
Transactions are always initiated by the Host and therefore thought of from the Hosts perspective A Transaction consist of multiple packets and begin when the host sends one of four Token Packets
OUT notifies the DC that data is being send out from the Host IN requests that DC send data in to the Host SOF signals the Start of Frame SOF signals the Start of Frame
A Data Packet follows the token packet The Transaction ends with Handshake Packet to report the Status of the Transaction.
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Packet Formats
8 bits 11 bits 5 bits
SOF Packet
PID
8 bits
FRAME NUMBER
7 bits 4 bits
CRC5
5 bits
Token Packet
PID
8 bits
ADDR
ENDP
CRC5
16 bits
0 1023 bytes
PID
8 bits
PAYLOAD
CRC16
PID
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Endpoints in LPC2148
Maximum of 32 (16 logical) endpoints Selectable Double Buffering for Bulk and Isochronous Data Transfer Any combinations of Endpoints allowed Maximum buffer size supported for all endpoints types
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Using the DMA, the USB Logic has direct access to memory
VPB Bus
Register Interface
RX D
2K FIFO
Receivers
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Transfer Modes
Slave Transfer Mode DMA Transfer Mode
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LPC2148 connections
3.3 volt system power Vusb bus sense Good Link LPC2148 Logic level p channel FET Philips BSH203 1.5k ATX Pad DD+ 33 33 D+ Vusb supply
Soft connect_n
D-
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LPC2148 clocks
XTAL
cclk pclk
VPB clock must be 16 MHz minimum for the USB vpb interface
USB clk
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CAN
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Bus Interface
Transmit Transmit Buffer 1 Transmit Buffer 2 Buffer 3 Global Acceptance Filter Table with up to 1024 filters; buffered in Full CAN mode Transmit Transmit Buffer 1 Transmit Buffer 2 Buffer 3 Host Interface
Host CPU
Bus Interface
CAN Bus
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1000
10,000
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Timer 0 and 1
32-bit Timer 32-bit Capture Registers and Capture Pins
Four on each timer
(48-pin devices three on Timer 0 and four on Timer 1)
Interrupt, timer reset or timer halt on match Match output can toggle, go high, go low or do nothing
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Timer Capture
Control
Capture Input 0 Interrupt Register Capture Input 1 Capture Input 2 Capture Register 0 Capture Input 3* Load Capture Register 1 Capture Register 2 Capture Register 3* Timer Control Register
ENABLE RESET
32-bit Timer/Counter
Interrupt
*: not available in 48-pin devices
32-bit Pre-Scaler
PCLK
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Timer Compare
Control
Match Output 0 Match Output 1 Match Output 2 Match Output 3* Match Control Register External Match Register Interrupt Register Match Register 0 Match Register 1 Match Register 2 Match Register 3 Timer Control Register
ENABLE RESET
Interrupt
Timer=MR3 Timer=MR2 Timer=MR1 Timer=MR0
= = = =
32-bit Timer/Counter
32-bit Pre-Scaler
PCLK
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= =
PWM1
Enable
R EN S Q
Interrupt
PWM2
Enable
=
Control 32-bit Timer Counter 32-bit Pre-Scaler
R EN
PWM6
Enable
PCLK
R EN
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er m i T ue l Va
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r Time e Valu
(single-edge)
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Hands-On Index
1. 2. 3. 4. 5.
Hands-On
Tools Setup Oscillator / PLL / MAM / GP I/O ADC Interrupts / Timer UART / CAN
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Project: SerialRTC
Load Project SerialRTC Build and Debug Simulation
Use Serial Window #2
Hands-On
Target Hardware
Use terminal program set to 9600bps
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Watchdog Timer
Once activated, the Watchdog will reset the entire chip if it is not fed regularly Feed is accomplished by a specific sequence of data writes Watchdog flag allows software to tell that a watchdog reset has occurred Selectable overflow time (s ... minutes) Debug Mode generates an interrupt instead of a reset Secure: watchdog cannot be turned off once it is enabled Watchdog Timer value can be read in one cycle
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Watchdog Timer
WDFEED
Watchdog Timer Constant
PCLK
/4
WDRESET
Sticky bits!
(cleared by WDT underflow or ext. reset)
RESET INTERRUPT
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USB Block
cclk
ARM7TDMI-S
4MHz
Bypass Synchronizer
25 or 50 MHz
wdclk
Watchdog Timer
Perpipheral Clock Generator pclk
APB Peripherals
RTC Prescaler
32.768kHz
RTC Oscillator
rtcclk
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1..128
M = 132768 N = 1..256
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LPC23/24 clocking
The LPC2300 has three clock sources
External oscillator 1Mhz 24 Mhz External watch crystal 32.756 Khz Internal RC oscillator approx 4 Mhz
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APB Bus
APB Interface
Adapter Registers
Command Path
MCICMD
MCIDATA [3:0]
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SD/MMC/SDIO
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OR
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SDIO small devices that use the SD physical format for other functions beyond storage
GPS, WiFi, BlueTooth, Modems, FM Radio, RFID, Barcode, etc., etc. Additional interconnect functionality required May require interrupt line (SD interface does not provide)
http://en.wikipedia.org/wiki/Secure_Digital_card
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I2S Features
The I2S input and output can each operate independently in both master and slave mode. Capable of handling 8, 16, and 32 bit word sizes. Mono and stereo audio data supported. The sampling frequency can range (in practice) from 16-48 kHz. Word Select period in master mode is configurable (separately for I2S input and I2S output). Transmit and receive functions each have an 8 byte data FIFO. Programmable FIFO level interrupts. Two DMA requests, controlled by programmable FIFO levels. Controls include reset, stop and mute options separately for I2S input and I2S output.
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I2S Diagrams
SCK: serial clock SCK: serial clock
Transmitter (master)
Receiver (slave)
Transmitter (slave)
Receiver (master)
Controller (master)
SCK
Transmitter (slave)
WS SD
Receiver (slave)
SCK
WS
LSB
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Four chip selects each for SDRAM and static devices. Power-saving modes dynamically control CKE and CLKOUT. Support for dynamic memory self-refresh mode. Supports 2K, 4K, and 8K row address synchronous memory parts. Separate reset domains allow for auto-refresh through chip reset.
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Typically 512, 256, and 128 MB parts with 4, 8, 16, or 32 bits per device.
AHB Bus
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IntEnable [31:0]
FIQ
RawIntr [31:0]
IntSelect [31:0]
VectIRQ0
VectPriority0 [4:0]
Priority Logic
IRQ
Vectored Interrupt 1
IRQStatus [1]
Vect AddrOut
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DMA (1)
Two DMA channels, each with a four-word FIFO. 16 peripheral DMA request lines. Some of these are connected to peripheral functions that support DMA: the SD/MMC, two SSP, and I2S interfaces. One 32-bit AHB bus master interface. Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported.
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DMA (2)
Scatter or gather DMA is supported through the use of linked lists. Hardware DMA channel priority: channel 0 is higher priority than channel 1. Incrementing or non-incrementing addressing for source and destination. Programmable DMA burst size. 8, 16, and 32-bit wide transactions. Big-endian and little-endian support. Little-endian is the default. An interrupt can be generated on a DMA completion or error.
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GPIO Interrupts
APB Bus
GPIOIntStatus Register
Port Int VIC Interrupt Other Port Ints plus one existing interrupt
GPIO Pin
Write 1 to GPIOIntClr
1
Pin Int
Wakeup GPIOIntStatF Register (Read Only) GPIOWake (from IntWake Register) Other Port Wakeups
APB Bus
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Xtal1
Xtal2
TDO
TMS
64 KB SRAM
512 KB Flash
Test/Debug Interface
ARM7TDMI-S
Internal SRAM Controller Internal Flash Controller ARM7 Local Bus AHB Bridge AHB to Master Port AHB Bridge APB Divider
MII or RMII
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RST
TCK
TDI
Bus Interface
AHB Bus
Bus Interface
Receive DMA
Receive Buffer
MII
MIIM
Receive Filter
Ethernet Block
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Ethernet PHY
Transmit DMA
Transmit Retry
Ethernet MAC
RMII adapter
Host Registers
RMII
MII or RMII
Internal scatter/gather DMA controller Semi-dedicated 16K byte on-chip RAM Can access other memory areas (including off-chip) except the Flash and main SRAM
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MIIM Pin
MDC MDIO Total:
# of Pins
1 1 2
Function
Clock Combined data input, data output, and data output enable. The protocol defines how and when the direction changes.
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MII Pin
TX_EN TXD[3:0] TX_ER TX_CLK COL CRS RX_DV RXD[3:0] RX_ER RX_CLK Total:
# of Pins
1 4 1 1 1 1 1 4 1 1 16
Function
Transmit data enable Transmit data output Transmit error Transmitter clock Collision Carrier sense Receive data valid Receive data input Receive error Receiver clock
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RMII Pin
TX_EN TXD[1:0] RXD[1:0] CRS_DV RX_ER REF_CLK Total:
# of Pins
1 2 2 1 1 1 8
Function
Transmit data enable Transmit data output Receive data input Carrier sense / Data valid Receive error (optional, depending on application) Reference clock input
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When using the filter tables, the numbering of CAN interfaces might vary
In some implementations CAN interfaces are numbered 1 and 2 In some implementations CAN interfaces are numbered 0 and 1
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Other Peripherals
USB with Device, Host, and OTG. UARTs (4), one with modem control, one with IrDA. CAN (2 channels). SD / MMC Card Interface. SPI (1) & SSP (2). SPI shares pins with SSP0. Timers (4), each with capture/compare. Watchdog Timer. DAC output.
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Thank You!