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De-Emphasis
Over-sampling
Modulators
SD2 80
D/A 40KHz VOR2
96 Times
Filters
Audio I/F
Serial
SD3 77
D/A 40KHz VOL2
SDOUT 80
D/A 40KHz VOR1
15
XCK RST
Audio DAC
1 Audio Output Level 1 Vrms
Audio ADC
1 Full Scale Audio Input Level 3.5 Vp-p
3 SNR 98 dB
4 Dynamic Range 98 dB
DESCRIPTION
The AV2188 is a mixed signal CMOS monolithic audio CODEC. It consists six channels sigma delta DACs and two
channels sigma delta ADCs. The DACs support 20-bit and 24-bit input data, while the ADCs provides 24-bit MSB
justified data output.
XCK REQUIREMENT
The AV2188 support 384 and 256 times sampling clock for 32, 44.1 and 48 K audio; 192 and 128 times for the 96
K audio.; and 96 and 64 times for the 192K audio.
XCK Requirement
PIN ASSIGNMENT
SD1 1 28 AR3
SD2 2 27 AL3
SD3 3 26 AR2
SDOUT 4 25 AL2
SC 5 24 AR1
A V 2 1 8 8
SF 6 23 AL1
DGND 7 22 AGND
DVDD 8 21 CM2
DGND 9 20 AVDD
XCK 10 19 CM1
SCL 11 18 AGND
SDA 12 17 RIN
TST 13 16 LIN
RST 14 15 N/C
PIN DESCRIPTION
Pin Name Pin # Type Description
DIGITAL
SD1 1 I Audio Serial Data Input 1, data can be 20bit/24bit, Right justified, or 24bit Left
justified, or 24bit I2S, all in 2’s complement format.
SD2 2 I Audio Serial Data Input 2, data can be 20bit/24bit, Right justified, or 24bit Left
justified, or 24bit I2S, all in 2’s complement format.
SD3 3 I Audio Serial Data Input 3, data can be 20bit/24bit, Right justified, or 24bit Left
justified, or 24bit I2S, all in 2’s complement format.
SDOUT 4 O Serial Audio Output pin, data can be in 24/20bit left justified or 24/20 bit I2S
format.
SF 6 I Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in
SF indicates Left Channel Data, a low in SF indicates Right Channel Data. For
I2S mode, a low in SF indicates Left Channel Data, a high in SF indicates Right
Channel Data.
SDA 12 I/O I2C DATA bus. Open drain output. Externally this pin should tie to a 680 ohm
pull up resistor.
TEST 11 O Test fs reference pin. For test vector verification. For normal operation this pin
must be tied to ‘0’.
RST 12 I Active low power down reset. When low, the chip is reset and all programmable
registers are reset to default values.
Analog
0 0 0 24-bit
1 0 1 20-bit 24-bit
2 1 0 18-bit
3 1 1 16-bit
The SD3, SD2 and SD1 can be either 24-bit or 32-bit per frame as well as left justified, right justified or I2S. The
SDOUT only support left justified and I2S format. The AV1488 counts the number of BCK per frame to determine
whether the input is 24 or 32 bits format.
1 0 1 I2S I2S
3 1 1 Invalid
1/fs
LEFT CHANNEL RIGHT CHANNEL
SF
SC
1/fs
LEFT CHANNEL RIGHT CHANNEL
SF
SC
1/fs
LEFT CHANNEL RIGHT CHANNEL
SF
SC
MSB LSB MSB LSB
SD1,2,3 1 0 1 0
IIS, CREG0[7,6]=[0 1]
Figure 2.
1/fs
LEFT CHANNEL RIGHT CHANNEL
SF
SC
1/fs
LEFT CHANNEL RIGHT CHANNEL
SF
SC
MSB LSB MSB LSB
SD1,2,3
23 22 21 2 1 0 23 22 21 2 1 0
IIS, CREG0[7,6]=[0 1]
Upon power up, all programmable registers are set to default values. Figure 4 describes the serial command port
timing relationship.
SDA 1 1 1
SCL
Address Default
Register Register Function
(decimal) Value
CREG0[7:0]
ADDR[4:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Default Value 1 0 0 0 0 0 0 0
FMT[1:0]: - These two bits define the serial audio input resolution
00: - 24-bit resolution. (default)
01: - 20-bit resolution.
10: - 18-bit resolution.
11: - 16-bit resolution.
CREG1[7:0]
ADDR[4:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Default Value 1 0 0 0 0 0 0
Volume Registers
ADDR[4:0]
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Hex 02 VLREG[7:0]
Default Value 1 0 0 0 0 0 0 0
22 uF 8 20 22 uF
DVCC AVCC
22 uF
1 28
SD1 AR3
2
SD2 27 22 uF
3
SD3
AV2188 AL3
Digital Audio 4 26 22 uF
Interface SDOUT AR2
5 25 22 uF
SC AL2
6
SF 24 22 uF
AR1
384 or 256 Times 10
XCK 23 22 uF
SF C lock
AL1
21
+5 Volt CM2
47uF
680 ohm
11
2 19
I C Serial SCL
CM1
Interface 12 47uF
SDA
220 ohm 22 uF
13 17
TST RIN
200K
14
Reset 220 ohm 22 uF
RST 16
LIN
200K
DVSS AVSS
All Unmarked 18 22
7 9 15
Capacitors are
0.1 uF
TIMING DIAGRAM
Figure 5. Audio Serial Interface Timing Requirement
tsc
tscH tscL
SC
tsd su
SD1-3
tsdout mx tsd hd
SDOUT
tsdout mn
tsf su
SF
tsf hd
tBUF tSU;STA
SDA
tHD;STA tSU;DAT
tSU;STO
tHIGH
SCL P S P
Sr
tLOW
tR
tF tHD;DAT
trst
PWD
TDsc Digital Short Circuit Duration (single output high state to Vss) 1 Sec
TASC Analog Short Circuit Duration (single output to VSS1) infinite Sec
Notes:
1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified
operating conditions.
2. Applied voltage must be current limited to specified range, and measured with respect to VSS.
ELECTRICAL CHRACTERISTICS
Supply
Reset Signal
Channel Separation 84 97 dB
Channel Separation 96 dB
PACKAGING INFORMATION
Dimensions
Mils Mils
28-Pin (SOP)
A1
E2 A
E1