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UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting nonbuffered functions.
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MC14001UB
Quad 2Input NOR Gate
MC14011UB
Quad 2Input NAND Gate
MARKING
DIAGRAMS
14
PDIP14
P SUFFIX
CASE 646
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
0.5 to +18.0
1
14
10
mA
PD
Power Dissipation,
per Package (Note 2.)
500
mW
TA
55 to +125
Tstg
65 to +150
TL
Lead Temperature
(8Second Soldering)
260
Iin, Iout
MC140xxUBCP
AWLYYWW
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/C From 65C To 125C
SOIC14
D SUFFIX
CASE 751A
140xxU
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
ORDERING INFORMATION
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
Device
Package
Shipping
MC14001UBCP
PDIP14
2000/Box
MC14001UBD
SOIC14
55/Rail
MC14001UBDR2
SOIC14
MC14011UBCP
PDIP14
2000/Box
MC14011UBD
SOIC14
55/Rail
MC14011UBDR2
SOIC14
MC14001UB, MC14011UB
LOGIC DIAGRAMS
MC14001UB
Quad 2Input
NOR Gate
1
2
5
6
8
9
12
13
MC14011UB
Quad 2Input
NAND Gate
1
2
5
6
8
10
10
9
12
11
11
13
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001UB
Quad 2Input NOR Gate
MC14011UB
Quad 2Input NAND Gate
IN 1A
14
VDD
IN 1A
14
VDD
IN 2A
13
IN 2D
IN 2A
13
IN 2D
OUTA
12
IN 1D
OUTA
12
IN 1D
OUTB
11
OUTD
OUTB
11
OUTD
IN 1B
10
OUTC
IN 1B
10
OUTC
IN 2B
IN 2C
IN 2B
IN 2C
VSS
IN 1C
VSS
IN 1C
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2
MC14001UB, MC14011UB
Symbol
55C
25C
125C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
0 Level
VOL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
1 Level
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
0 Level
VIL
5.0
10
15
1.0
2.0
2.5
2.25
4.50
6.75
1.0
2.0
2.5
1.0
2.0
2.5
5.0
10
15
4.0
8.0
12.5
4.0
8.0
12.5
2.75
5.50
8.25
4.0
8.0
12.5
5.0
5.0
10
15
1.2
0.25
0.62
1.8
1.0
0.2
0.5
1.5
1.7
0.36
0.9
3.5
0.7
0.14
0.35
1.1
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
0.1
0.00001
0.1
1.0
Adc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
Adc
IT
5.0
10
15
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
1 Level
IIH
Vdc
IOH
Source
Sink
Vdc
mAdc
Adc
3. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
4. The formulas given are for the typical characteristics only at 25C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in H (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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3
MC14001UB, MC14011UB
Symbol
tTLH
tTHL
VDD
Vdc
Min
Typ (7.)
Max
5.0
10
15
180
90
65
360
180
130
5.0
10
15
100
50
40
200
100
80
5.0
10
15
90
50
40
180
100
80
Unit
ns
ns
tPLH, tPHL
ns
6. The formulas given are for the typical characteristics only at 25C.
7. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
20 ns
14
VDD
INPUT
PULSE
GENERATOR
INPUT
OUTPUT
VDD
90%
50%
10%
tPLH
tPHL
CL
90%
50%
10%
OUTPUT
INVERTING
VSS
20 ns
tTLH
VDD
14
10
14 VDD
3, 4, 10, 11
1, 6, 8, 13
2, 5, 9, 12
13
12
7
VSS
7 VSS
11
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4
VOH
VOL
tTHL
0V
MC14001UB, MC14011UB
12
10
8.0
6.0
5.0 Vdc
4.0
b
2.0
0
8.0
6.0
15 Vdc
b a
a
10 Vdc
4.0
14
16
16
2.0
-10 Vdc
-10
-10
-15 Vdc
b
a
-8.0
6.0
-6.0
-4.0
VDS, DRAIN VOLTAGE (Vdc)
a b
8.0
15 Vdc
b
VGS = 10 Vdc
b
c
6.0
a TA = -55C
b TA = +25C
c TA = +125C
4.0
a
2.0
a
-2.0
5.0 Vdc
4.0
10
c
b
-8.0
a TA = +125C
b TA = -55C
a TA = -55C
b TA = +25C
c TA = +125C
-6.0
8.0
-4.0
10 Vdc
10
2.0
-2.0
12
0
2.0 4.0 6.0 8.0 10 12 14 16
Vin, INPUT VOLTAGE (Vdc)
14
2.0
5.0 Vdc
4.0
6.0
VDS, DRAIN VOLTAGE (Vdc)
8.0
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5
10
MC14001UB, MC14011UB
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
14
A
F
T
SEATING
PLANE
K
H
D 14 PL
0.13 (0.005)
M
M
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6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
--10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
--10
0.38
1.01
MC14001UB, MC14011UB
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
14
B
1
P 7 PL
0.25 (0.010)
R X 45
T
SEATING
PLANE
0.25 (0.010)
D 14 PL
M
T B
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019
MC14001UB, MC14011UB
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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8
MC14001UB/D