Climbing to the Top: OVM to UVM Migration

Larry Ching DAC 2011 June 7, 2011

Copyright 2011 Boeing. All rights reserved.

OVM Adoption Roadmap

Boeing Space and Intelligence Systems

2006 & Earlier - Traditional Verilog/VHDL Testbench

Need randomization and functional coverage

2007 Adopted SystemVerilog

Need simulator independent testbench Which methodology gy ? ( (URM, , AVM or VMM ?) ) Developed Boeing internal SV Methodology

2008 - Adopted OVM

OVM doesn doesnt t have a register package

2009 - Adopted Cadence OVM Register Package

Compatible with both Cadence & Mentor simulators

2010 - Stayed with OVM 2.11

Did not use UVM-1.0EA

2011 Adopted UVM 1.0 1.0-p1 p1

Converted OVM testbench to UVM

Copyright 2011 Boeing. All rights reserved.

Existing OVM Verification Architecture

Boeing Space and Intelligence Systems

my_top (module) test_xyz (class) my_tb (class)

virtual sequencer my OVC
tx agent mon seqr drvr

my module OVC module OVC monitor scoreboard

hbus OVC
master agent mon seqr drvr

my_if

hbus_if

TX DUT

HSS hss error OVC

master t mon agent seqr drvr

my OVC
rx agent mon seqr drvr

my_if

HSS ERR MUX

err_mux_if

hbus OVC
master agent mon seqr drvr

hbus_if

RX DUT

HSS

Copyright 2011 Boeing. All rights reserved.

OVM to UVM Conversion Procedure

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

1. Rename all filename with ovc to uvc

At unix p prompt, p , type: yp rename ovc uvc *

2. Convert all OVM text to UVM text (using Boeing modified script)
Boeing modified ovm2uvm.pl script, to convert uvc text to ovc At unix prompt, type:
perl $UVM_HOME/bin/boeing_ovm2uvm.pl top_dir your_dir all write

3. Manual Steps to convert your OVM testbench and testcases

A. Use new UVM Phase and Objection feature in testcase OVM testcase
virtual task run(); . . . . . . . . global_stop_request(); endtask : run

UVM testcase
virtual task run_phase(uvm_phase phase); phase.raise_objection(this,,"Start run phase"); . . . . . . . . phase.drop_objection(this,,"Start run phase"); endtask : run_phase

Copyright 2011 Boeing. All rights reserved.

OVM to UVM Conversion Procedure (continue)

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

3. Manual steps to convert your OVM testbench and test cases

B. Update your virtual sequence with objection statements UVM virtual sequence
// Sequence PRE-BODY Used to raise end-of-test objection virtual task pre_body(); uvm_info(get_type_name(), info(get type name() "Raising Raising Objection Objection",UVM_LOW); UVM LOW); `uvm uvm_test_done.raise_objection(this); endtask : pre_body // Sequence PRE-BODY Used to drop end-of-test objection virtual task post_body(); _ _ _ "Dropping Objection", UVM_LOW); _ `uvm_info(get_type_name(), uvm_test_done.drop_objection(this); endtask : post_body

Note : Use objection statements, or your virtual sequence will complete at time 0.

C New C. N way t to specify if default d f lt sequence for f the th sequencer (within ( ithi each h test) t t) OVM code
set_config_string(tb.tx_uvc.tx_agent.sequencer", q , "default_sequence", "bss_uvc_demo_seq");

UVM testcase
uvm_config_db#(uvm_object_wrapper)::set(this, g q _p phase", , tb.tx_uvc.tx_agent.sequencer.run default_sequence, bss_uvc_demo_seq::type_id::get());

Note : Original OVM code still works in UVM1.0, but you will have a deprecation message.
Copyright 2011 Boeing. All rights reserved.

New UVM features adopted

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

1. 2. 3. 4. 5. 6. 7. 8.

Use Callback to disable printing of unwanted UVM message Register virtual sequence to the factory replace `uvm_sequence_utils with `uvm_object_utils `uvm_info/error/fatal can now be used within Sequencer and virtual sequences (Replacing p_sequencer.uvm_report_info) Command line to override verbosity setting of individual UVC component Use new UVM phase syntax build_phase(uvm_phase phase) Replace set_config_int & set_config_string, with uvm_config_db Removed uvm_printer format options in test case, because UVM can now autosize table columns Use uvm_config_db for virtual interface connection
initial begin uvm_config_db#(virtual demo_if)::set(null, "uvm_test_top.demo_top.demo_uvc*", "vif", demo_if); 6 run_test(); end

9.

UVM Register Package: Using driver and adapter, but need to investigate the scoreboard usage model
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Copyright 2011 Boeing. All rights reserved.

New UVM Wish List

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

1. Deprecated Features:
Need a better way to find out what (and when) are being deprecated Need to document replacement coding method and usage model Do not generate deprecation messages if new feature is not mature, or in beta stage

2. New UVM Phasing concept is too confusing

Why do we need two parallel run phases ? The solution doesnt seem complete

3. Command line option UVM_REPORT_DISABLE_FILE_LINE should be a default option 4. Need more examples, and usage model for
new sequence library concept UVM register scoreboard
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Copyright 2011 Boeing. All rights reserved.

Summary and Next Steps

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

1. Basic migration g to UVM was straightforward g 2. UVM is a users dream come true
A. Finally, a true simulator independent SV Methodology B. Finally, a unified UVM Register Package

3. While a dream came true, we cant rest easy yet

A. So many new features in UVM, but lack standardized usage model B. New UVM users are confused Where and how do I begin with UVM ? C. Existing users are concerned about UVM backward compatibilities

Copyright 2011 Boeing. All rights reserved.

UVM Rookie Experience Using Cadences flow

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

Voices from UVM rookies :

UVM provides many small example codes but how do I put them together ? There are many ways of coding UVM How and where do I start building my UVM testbench ?

Learn from the Expert, use Cadences reference flow and SV tools
Incisive Verification Builder (IVB) Incisive Enterprise Simulator Incisive Enterprise Planner (Metric Driven Verification) Learn from the latest SOCkit

Copyright 2011 Boeing. All rights reserved.

Incisive Verification Builder (IVB)

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

1.

For UVM rookies :

IVB generates two types of UVCs Simple Interface UVC Comprehensive Bus UVC Each IVB generated UVC comes with : Full UVC structure : Agent, Driver, Monitor, Sequencer, Sequences, Sequence Library, example DUT, example testbench, run scripts A good way to standardize your UVC structure, coding style, t l and d usage model d l Good for internal training

2 2.

More importantly, IVB is free with Incisive Simulator For experienced OVM users :
Compare your existing OVC with IVB generated UVC A good way to find out the Cadences recommended usage model for new UVM features Very useful for OVM users to convert their OVCs to UVCs

Copyright 2011 Boeing. All rights reserved.

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Cadence Incisive Debug for UVM/OVM (Transaction Recording and Linking)

Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

// Inside driver or monitor code void '(begin_tr(packet)); end_tr(packet)); d ( k )) // start recording // body including timing // end d recording di

SimVision: Transaction viewing

Copyright 2011 Boeing. All rights reserved.

// In test before testbench creation set_config_int( *, recording_detail, 1);

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Summary
Integrated Defense Systems | Network and Space Systems | Space and Intelligence Systems | El Segundo

1. OVM users should feel comfortable migrating g g to UVM 2. UVM is a users dream come true
A. Finally, a true simulator independent SV Methodology B. Finally, a unified UVM Register Package

3. Core of UVM is solid, some new features need more ti time to t mature t 4. Cadence has a great solution for both OVM/UVM and new users

Copyright 2011 Boeing. All rights reserved.

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