PROJECT REPORT ON

Arithmetic Logic Unit

DESIGN AND IMPLEMENTATION OF 32-BIT ALU ON XILINX FPGA USING VHDL

PROJECT MENTOR:

RAJ MOHAN DEY SARKAR

Submitted by

ARITRA RANJAN PAL SHREYASI KOLEY ANINDITA PAUL INDRANI DEY TANAYA DAS
in partial fulfillment for the award of the degree

B.TECH IN ELECTRONICS & COMMUNICATION from SEACOM ENGINEERING COLLEGE Year of Submission: 2010

Acknowledgement:
It gives me great pleasure to find an opportunity to express my deep gratitude and sincerest thanks to my project mentor, Mr. Raj Mohan De Sarkar at Ardent Collaboration Salt lake of Kolkata for giving most valuable suggestion, helpful guidance and encouragement in the execution of this project. His guidance and encouragement has led to the successful completion of my project titled:- DESIGN AND IMPLEMENTATION

OF 32-BIT ALU ON XILINX FPGA USING VHDL. We are highly indebted to him for the way he modeled
and structured our work with his valuable tips and suggestions that he accorded to us in every respect of our work. Last but not the least I humbly extend my sense of gratitude to other faculty member and staffs of the institute for providing me their valuable help and time with a congenial working environment.

Abstract:
The aim of the project was to make a 32-bit Arithmetic and Logical Unit, using VHDL module in Xilinx I.S.E. 8.2i. here we have tried to design and implement the 32-bit A.L.U. by behavioral programming method in VHDL module. We have used various techniques as per our knowledge, we have used various logic gates, arithmetic circuits using logic gates and usi ng them we have prepared the arithmetic unit and the logical unit of the A.L.U... Then using multiplexers we have combined them and organized the A.L.U. structure. In this report we have shown various diagrams to show the structures of the A.L.U. and also the basic structures which constitutes the A.L.U. as a proof that the output is as per expected one can check the output waveforms of the different blocks with their respective theoretical values and truth tables.

Project Category:
V.L.S.I. chip design us ing A.S.I.C. and F.P.G.A. procedure . A.S.I.C. (Application Specific Integrated Circuit) is an integrated circuit designing method for integrated chip and circuit boards. But in this method designing can be done for one purpose only, it cant be modified. Circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare. F.P.G.A. (Field-Programmable Gate Array) is an integrated circuit designed to be configured by the customer or designer after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an applicationspecific integrated circuit (ASIC). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of the portion of the design and the low non-recurring engineering costs relative to an ASIC design offer advantages for many applications.

Objectives:
The objective of the project was to make a 32-bit Arithmetic and Logic Unit using V.H.D.L. module in Xilinx I.S.E. 8.2i. this report shows explicit details of Xilinx, Spartan 3E starter kit board, F.P.G.A., V.H.D.L., the program coding of the A.L.U. blocks and its basic blocks are also given in this report. Diagrammatic representation of the block diagrams and the gates and the circuits as well as the waveforms of each and every design is also supplied so that one can easily understand and check whether the output is correct or not.

Introduction:
INTRODUCTION TO XILINX (THE LEADER IN FGPA TECHNOLOGY)
Xilinx is the worlds largest supplier (Electronics Company) of programmable logic devices and the inventor of the field programmable gate array (FPGA). Today Xilinx is the number one FPGA vendor in the world. Xilinx is the worldwide leader of complete programmable logic solutions. Xilinx has two main FPGA families: - the high-performance Virtex series and the high-volume Spartan series. Each model series has been released in multiple generations since its launch. The latest Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, cost 20 percent less, and have up to twice the logic capacity of previous generations of FPGAs. The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume; e.g. displays, set-top boxes, wireless routers and other applications.

XILINX ISE 8.2I (THE INTEGRATED SOFTWARE ENVIRONMENT)

Xilinx ISE 8.2i (Integrated Software Environment) tool is the latest release of the Xilinxs widely-used design solutions. Xilinx delivers ISE 8.2i A complete logic design solution for the next Virtex-5 FPGA family. The ISE 8.2i design environment enables 30 percent faster performance than previous generation FPGAs. The ISE 8.2i design suite is accompanied by the release of the Chip Scope Pro 8.2 debug and verification software. Available as an add-on option, the Chip Scope Pro 8.2 solution reduces verification cycles by up to 50 percent. ISE software delivers programmable logic design solutions to over 300,000 users worldwide with an intuitive, front-to-back design environment for all Xilinx product families, including Spartan-3 Generation FPGAs. All versions of ISE 8.2i software packages support Windows 2000 and Windows XP and Linux Red Hat Enterprise 3.0.

FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL). FPGAs can be used to implement any logical function. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnections that allow the blocks to be "wired together". Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory. At the highest level, FPGAs are reconfigurable silicon chips. Using prebuilt logic blocks and programmable routing resources, we can configure these chips to implement custom hardware functionality. There are two basic types of FPGAs: SRAM-based reprogrammable and OTP (One Time Programmable). These two types of FPGAs differ in the implementation of the logic cell and the mechanism used to make connections in the device.

VHDL
VHDL is an acronym for Very High Scale Integrated Circuits Hardware Description Language. This language can be used to model a digital system at the levels of abstraction, algorithmic level to the gate level. A hardware description language is inherently parallel, i.e., commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. It also allows incorporation of timing specification (gate delays) as well as to describe a system as an interconnection of different components. The complexity of ASIC and designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. Verilog HDL is another Hardware Description Language. VHDL offers several advantages to the designers.  Standard language and readily available tool.  Powerful and versatile description language.  Multiple mechanisms to support design hierarchy.  Versatile design reconfiguration support.  Support of multiple levels of abstraction.

XILINX SPARTAN FPGA STARTER KIT BOARD

The latest Spartan-6 FPGA families are said to consume 50 percent less power, cost 20 percent less, and have up to twice the logic capacity of previous generations of FPGAs. The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume; e.g. displays, set-top boxes, wireless routers and other applications. ISE software delivers programmable logic design solutions to over 300,000 users worldwide with an intuitive, frontto-back design environment for all Xilinx product families, including Spartan-3 Generation FPGAs. The Spartan series targets applications with a low-power footprint, extreme cost sensitivity and high-volume.

Tools/Environment used
HARDWARES:Computer Hard Disk PROCESSOR RAM VDU

: : : : :

IBM or compatible. 20 GB or higher. PENTIUM-IV 2 GHz and above 512 MB and above VGA

SOFTWARES:OPERATING SYSTEM DEVELOPMENT SOFTWARE

: :

Windows XP, Windows 7, Windows vista, Linux, Solaris Xilinx ISE 8.2i, ModelSim Simulator

SOFTWARE REGISTRATION:During installation, you must enter a 16-digit Registration ID, which allows you to finish the software installation. Registration of Xilinx software on a "per end-user" basis ensures that you receive the full complement of support and services to which you are entitled.

IDENTIFICATION OF THE NEED

The first step in the system development life cycle is the identification of the need. This is a users request to change, improve or enhance an existing system. Because there is likely to be a stream of such requests, standard procedures must be established to deal with them. The success of a system depends largely on how accurately a problem is defined, thoroughly investigated and properly carried out through the choice of solution. User need identification and analysis are concerned with what the user needs rather that what he/she wants. Not until the problem has been identified, defined and evaluated should the analyst think about solutions and whether the problem is worth solving. This step is intended to help the user and the analyst understand the real problem rather than its symptoms. The user or the analyst may identify the need for a candidate system or for enhancements in the existing system. If objectives are misunderstood, it is easy to solve the wrong problem. The successful design of a system requires a clear knowledge of what the system is intended to do. In the present scenario of Information Technology it is needed that most of the manual operational systems in an organization are needed to be converted into information management system. In a huge organization like correction house there is a need of co-relation between the different independent operations related to the organization. The primary need is to design a reconfigurable CPU that is extendible.

Project Planning
Once a project is found to be feasible, project planning is undertaken and completed before any development activity starts. Project planning consists of the following essential activities:Estimating some basic attributes of the project: Cost: How much will it cost to develop the project?  Duration: How long will it take to complete the development?  Effort: How much effort would be required? The effectiveness of the subsequent planning activities is based on the accuracy of these estimations. Scheduling manpower and other resources Staff organization and staffing plans Risk identification and analysis Miscellaneous plans such as quality assurance plan, configuration management plan, etc. Developing a system requires planning and coordinating resources with a given time. More important, effective project management is needed to organize the available resources, schedule the events, and establish standards.

GANTT CHART:A GANTT chart is a bar chart, which is perhaps the simplest form of formal project management. The bar chart is used almost exclusively for scheduling purposes and therefore controls only the time dimension of projects. GANTT Charts (developed by Henry L Gantt) are a project control technique that can be used for several purposes, including scheduling, budgeting and resource planning. A GANTT chart is bar chart with each bar representing an activity. The bars are drawn against a time line. The length of each bar is proportional to the length of time planned for the activity.

Project Activity Identification of Need Feasibility Study Requirement Specification Technology Familiarization Design Coding Testing Implementation and Evaluation

2010
Jan 1 7 Feb Mar Apr May

20

21

10

11 20

21

25 26 15 16 25 26 12

REQUIREMENTS SPECIFICATION
The requirement specification is the starting point for the next phase: design. Consequently, a very precise, even mathematical description is preferable. On the other hand, the specification must also be understandable to the user. This often means a readable document, using natural language and pictures. In practice, one has to look for a compromise. Alternatively, the requirements specification may be presented in different, but consistent, forms to the different audiences involved.

REQUIREMENT SPECIFICATION OF THE |DESIGN AND IMPLEMENTATION OF A 32BIT ARITHMETIC LOGIC UNIT ON XILINX FPGA USING VHDL} PROJECT IS AS FOLLOWS:(1) Introduction
1. Purpose: This document states the requirements of a 32-bit ALU design and implementation. T he requirements stated serve as a basis for the acceptance procedure of this system. The document is also intended as a starting point for the design phase. 2. Scope: The intended product creates 32-bit ALU. Its purpose is to fetch instruction from memory and execute them.

(2) Overall Description

The top-level design of 32-bit ALU consists of the 4-bit ALU blocks whose inputs are in the form of bus. The ALU fetches inputs from the input bus and executes its logic to run a program. These outputs are shown in the form of waveforms.

(3) User Characteristics

Anyone can be the user of this system and must have some familiarization with computer to operate this type system. The users should have access to the instruction manual of the ALU.

(4) Constraints
1. 2. 3. Design Constraints: This is only a 16-bit CPU. In future, I hope to extend it. Software Constraints: The system can run under the Windows XP professional operating systems. Hardware Constraints: The system will run with minimum 512 MB RAM and 4.3 GB HARD -DISK spaces.

CLASSIFICATIO :ALU 32 BIT

ALU 4 BIT

ALU 1 BIT

MULTIPLEXER

LOGICAL UNIT

ARITHMETIC UNIT

MULTIPLEXER

MULTIPLEXER

AND

ADDER

OR

SUBTRATOR

XOR

INCREMENT

NAND

DECREMENT

NOR

TRANS ER

XNOR

NOT

COMPONENTS DESIGN, CODING AND VERIFICATION:LOGICAL AND :The AND gate performs logical multiplication, more commonly known as AND function. In this gate two or more inputs are used. When all inputs are high then only output is high, otherwise the output is low.

CODING:
entity ANDBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end ANDBIT; architecture Behavioral of ANDBIT is begin C <= A AND B; end Behavioral; 1 1 0 1 0 1 TRUTH TABLE: INPUT S A 0 0 B 0 1 OUTPUT C 0 0

DESIGN:

WAVEFORM:

LOGICAL OR :The OR gate performs logical addition, more commonly known as OR function. In this gate two or more inputs are used. When all inputs are low then only output is low, otherwise the output is high.

CODING:
entity ORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end ORBIT; architecture Behavioral of ORBIT is begin C <= A OR B; end Behavioral; A 0 0 1 1

TRUTH TABLE: INPUT S B 0 1 0 1 OUTPUT C 0 1 1 1

DESIGN:

WAVEFORM:

LOGICAL EXCLUSIVE OR (XOR) :This circuit is also called inequality comparator or detector because it produces output only when the two inputs are different. In this gate two or more inputs are used. When number of high inputs is even then the output is low, otherwise the output is high.

CODING:
entity XORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end XORBIT; architecture Behavioral of XORBIT is begin 0 C <= A XOR B; end Behavioral; 1 1 1 0 1 1 1 0 A 0

TRUTH TABLE: INPUT S B 0 OUTPUT C 0

DESIGN:

WAVEFORM:

COMPLEMENT AND (NAND) :This is a universal gate. In this gate two or more inputs are used. When all inputs are high then only output is low, otherwise the output is high.

CODING:
entity NANDBIT is Port (

A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); A

TRUTH TABLE: INPUT S B 0 1 0 1 OUTPUT C 1 1 1 0

end NANDBIT; architecture Behavioral of NANDBIT is begin C <= A NAND B; end Behavioral;

0 0 1 1

DESIGN:

WAVEFORM:

COMPLEMENT OR (NOR) :This is also a universal gate. In this gate two or more inputs are used. When all inputs are low then only output is high, otherwise the output is low.

CODING:
entity NORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end NORBIT; architecture Behavioral of NORBIT is begin C <= A NOR B; end Behavioral;

TRUTH TABLE: INPUT S A 0 0 1 1 B 0 1 0 1 OUTPUT C 1 0 0 0

DESIGN:

WAVEFORM:

LOGICAL EXCLUSIVE (XNOR) :The EX-NOR gate is also called a coincidence gate, because its output is a 1 only when its inputs coincide (either 0, 0 or 1, 1). It can be used as an equality detector because its output is a 1 only when its inputs are equal. In this gate two or more inputs are used. When number of high inputs is even then the output is high, otherwise the output is low.

CODING:
entity XNORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end XNORBIT; architecture Behavioral of XNORBIT is begin 0 C <= A XNOR B; end Behavioral; 1 1 1 0 1 0 0 1 A 0

TRUTH TABLE: INPUT S B 0 OUTPUT C 1

DESIGN:

WAVEFORM:

LOGICAL COMPLEMENT (NOT) :The inverter performs a basic logic function called inversion or complementation. It inverts the input.

CODING:
entity NOTBIT is Port ( A : in STD_LOGIC; B : out STD_LOGIC); end NOTBIT; architecture Behavioral of NOTBIT is begin B <= NOT A; end Behavioral;

TRUTH TABLE: INPUT A 0 1 OUTPUT B 1 0

DESIGN:

WAVEFORM:

ADDER:A logic circuit that can add three bits, two bits to be added and a CARRY bit from the lower bit order which results in a SUM and a CARRY.
CODING:
entity ADDER is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C_IN : in STD_LOGIC; SUM : out STD_LOGIC; C_OUT : out STD_LOGIC); end ADDER; architecture Behavioral of ADDER is begin SUM <= (A XOR B) XOR C_IN; C_OUT <= (A AND B) OR ((A OR B) AND C_IN); end Behavioral; TRUTH TABLE: INPUT S A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C_IN 0 1 0 1 0 1 0 1 OUTPUT S SUM 0 1 1 0 1 0 0 1 C_OUT 0 0 0 1 0 1 1 1

DESIGN:

WAVEFORM:

SUBSTRACTOR:A logic circuit that can subtract three bits, one bit is to be subtracted from another and a BORROW bit from the previous bit order which results in a output D and a BORROW OUT.
CODING:
entity SUBTRACTOR is Port ( A : in STD_LOGIC; B : in STD_LOGIC; B_IN : in STD_LOGIC; DIFF : out STD_LOGIC; B_OUT : out STD_LOGIC); end SUBTRACTOR; architecture Behavioral of SUBTRACTOR is begin TRUTH TABLE: INPUT S A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C_IN 0 1 0 1 0 1 0 1 OUTPUT S SUM 0 1 1 0 1 0 0 1 C_OUT 0 1 1 1 0 0 0 1

DIFF <= (A XOR B ) XOR B_IN ; B_OUT <= (B_IN AND (A XNOR B)) OR ((NOT A) AND B); end Behavioral;

DESIGN:

WAVEFORM:

INCREMENT:Increments a number by one.

CODING:
entity INCREMENT is Port ( A 0 0 1 1 TRUTH TABLE: INPUT S B 1 1 1 1 C_IN 0 1 0 1 OUTPUT S SUM 1 0 0 1 C_OUT 0 1 1 1

A : in STD_LOGIC; C_IN : in STD_LOGIC; SUM : out STD_LOGIC; C_OUT : out STD_LOGIC);

end INCREMENT; architecture Behavioral of INCREMENT is begin SUM <= (A XOR '1') XOR C_IN; C_OUT <= (A AND '1') OR ((A OR '1') AND C_IN); end Behavioral;

DESIGN:

WAVEFORM:

DECREMENT:
Decrements a number by one.
CODING:
entity DECREMENT is Port ( TRUTH TABLE: INPUT S A : in STD_LOGIC; C_IN : in STD_LOGIC; D : out STD_LOGIC; C_OUT : out STD_LOGIC); A 0 0 1 1 B 1 1 1 1 C_IN 0 1 0 1 OUTPUT S SUM 1 0 0 1 C_OUT 1 1 0 1

end DECREMENT; architecture Behavioral of DECREMENT is begin

D <= (A XOR '1') XOR C_IN; C_OUT <= (C_IN AND (A XNOR '1')) OR ((NOT A) AND '1'); end Behavioral;

DESIGN:

WAVEFORM:

TRANSFER:The output is kept same as the input bit, no change or alteration is made to it.
CODING:
entity TRANSFER is Port ( TRUTH TABLE: A : in STD_LOGIC; B : out STD_LOGIC); INPUT A 0 1 begin B <= NOT (NOT A); end Behavioral; OUTPUT B 0 1

end TRANSFER; architecture Behavioral of TRANSFER is

DESIGN:

WAVEFORM:

MULTIPLEXERS:Mux or multiplexer or data selector is a logic circuit that accepts several data inputs and allows only one of them at a time to get through the output. In this circuit select lines are used and the output depends on it. If m is the number of select lines then inputs are 2^m.

CODING:
MUX 2 TO 1: entity MUX_TWO is Port ( A : in STD_LOGIC; B : in STD_LOGIC; SEL : in STD_LOGIC; MUX_TWO_OUT : out STD_LOGIC); end MUX_TWO; architecture Behavioral of MUX_TWO is begin WITH SEL SELECT MUX_TWO_OUT <= A WHEN '0', B WHEN OTHERS; MULT IPLEXER 8 TO 1 INPUT S A B C D E 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 TRUTH TABLE: SELECT F G H S2 S1 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 OUTPUT MUX_OUT 0 1 0 1 0 1 0 1 MULT IPLEXER 2 TO 1 TRUTH TABLE: INPUT S B SEL 1 0 1 1 OUTPUT MUX 0 1

A 0 0

end Behavioral;

MUX 8 TO 1:
entity MUX_EIGHT is Port (

A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; E : in STD_LOGIC; F : in STD_LOGIC; G : in STD_LOGIC; H : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); MUX_OUT : out STD_LOGIC);

S0 0 1 0 1 0 1 0 1

end MUX_EIGHT; architecture Behavioral of MUX_EIGHT is begin WITH SEL SELECT MUX_OUT <= A WHEN "000", B WHEN "001", C WHEN "010", D WHEN "011", E WHEN "100", F WHEN "101", G WHEN "110", H WHEN OTHERS;

end Behavioral;

DESIGN: MUX 2 TO 1:

MUX 8 TO 1:

WAVEFORM: MUX 2 TO 1:

MUX 8 TO 1:

ARITHMETIC UNIT:One essential function of most computer or other devices is the performance of arithmetic operations. Logic gates are used to perform arithmetic operations like addition, subtraction, incrementing, decrementing. The basic arithmetic units are adder, subtracter.

CODING:
entity AU_NEW is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; C_IN : in STD_LOGIC; SEL : in STD_LOGIC_VECT OR (2 downto 0); AU : out STD_LOGIC; C_OUT : out STD_LOGIC); end AU_NEW; architecture Behavioral of AU_NEW is SIGNAL A, B, C, D, E, F, G, H : STD_LOGIC; SIGNAL I, J, K, L, M, N, O, P : STD_LOGIC; COMPONENT ADDER is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C_IN : in STD_LOGIC; SUM : out STD_LOGIC; C_OUT : out STD_LOGIC); end COMPONENT; COMPONENT SUB TRACTOR is Port ( A : in STD_LOGIC; B : in STD_LOGIC; B_IN : in STD_LOGIC; DIFF : out STD_LOGIC; B_OUT : out STD_LOGIC); end COMPONENT; COMPONENT INCREMENT is Port ( A : in STD_LOGIC; C_IN : in STD_LOGIC; SUM : out STD_LOGIC; C_OUT : out STD_LOGIC); end COMPONENT; COMPONENT DECREMENT is Port ( A : in STD_LOGIC; C_IN : in STD_LOGIC; D : out STD_LOGIC; C_OUT : out STD_LOGIC); end COMPONENT; COMPONENT TRANSFER is Port ( A : in STD_LOGIC; B : out STD_LOGIC); end COMPONENT; COMPONENT MUX_EIGHT is

Port (

A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC; E : in STD_LOGIC; F : in STD_LOGIC; G : in STD_LOGIC; H : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); MUX_OUT : out STD_LOGIC);

end COMPONENT; begin AUO : ADDER PORT MAP ( X, Y, C_IN, A, I); AU1 : SUBTRACTOR PORT MAP ( X, Y, C_IN, B, J); AU2 : INCREMENT PORT MAP ( X, C_IN, C, K); AU3 : INCREMENT PORT MAP ( Y, C_IN, D, L); AU4 : DECREMENT PORT MAP ( X, C_IN, E, M); AU5 : DECREMENT PORT MAP ( Y, C_IN, F, N); AU6 : TRANSFER PORT MAP ( X, G); AU7 : TRANSFER PORT MAP ( Y, H); AU8 : MUX_EIGHT PORT MAP ( A, B, C, D, E, F, G, H, SEL, AU); AU9 : MUX_EIGHT PORT MAP ( I, J, K, L, M, N, O, P, SEL, C_OUT); O <= '0'; P <= '0'; end Behavioral; X 0 0 0 0 1 1 1 1 INPUT S Y 0 0 1 1 0 0 1 1 C_IN 0 1 0 1 0 1 0 1 S2 0 0 0 0 1 1 1 1 TRUTH TABLE: SELECT S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 OUTPUT ARITHMETIC UNIT ADDER SUBTRACTER INCREMENT X INCREMENT Y DECREMENT X DECREMENT Y TRANSFER X TRANSFER Y

DESIGN:

WAVEFORM:

LOGICAL UNIT:The most basic elements of digital circuits are logic gates. The output depends upon the combination of high and low inputs and the type of gates used. There are seven types of logic gates named AND, OR, NOT, NAND, NOR, XOR, X NOR.

CODING:
entity LU_NEW is Port (

X : in STD_LOGIC; Y : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); LU : out STD_LOGIC);

end LU_NEW; architecture Behavioral of LU_NEW is SIGNAL A, B, C, D, E, F, G, H : STD_LOGIC; COMPONENT ANDBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end COMPONENT; COMPONENT ORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end COMPONENT; COMPONENT XORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end COMPONENT; COMPONENT NANDBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end COMPONENT; COMPONENT NORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end COMPONENT; COMPONENT XNORBIT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : out STD_LOGIC); end COMPONENT; COMPONENT NOTBIT is Port ( A : in STD_LOGIC; B : out STD_LOGIC); end COMPONENT; COMPONENT MUX_EIGHT is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; D : in STD_LOGIC;

E : in STD_LOGIC; F : in STD_LOGIC; G : in STD_LOGIC; H : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); MUX_OUT : out STD_LOGIC); end COMPONENT; begin LU0 : ANDBIT PORT MAP (X, Y, A); LU1 : ORBIT PORT MAP (X, Y, B); LU2 : XORBIT PORT MAP (X, Y, C); LU3 : NANDBIT PORT MAP (X, Y, D); LU4 : NORBIT PORT MAP (X, Y, E); LU5 : XNORBIT PORT MAP (X, Y, F); LU6 : NOTBIT PORT MAP (X, G); LU7 : NOTBIT PORT MAP (Y, H); LU8 : MUX_EIGHT PORT MAP (A, B, C, D, E, F, G, H, SEL, LU); end Behavioral;

TRUTH TABLE: INPUT X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 S2 0 0 0 0 1 1 1 1 SELECT S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 OUTPUT LOGICAL UNIT AND OR XOR NAND NOR XNOR NOT X NOT Y

DESIGN:

WAVEFORM:

ARITHMETIC & LOGIC UNIT:ALU is an acronym for Arithmetic and Logic Unit. This unit performs various mathematical(addition, subtraction etc.) operations and logical operations(AND,OR,XOR etc.). in addition to these operations it also takes complements of a number, it compares two numbers, rotates the bits of number from left to right, shifts the bits of a number left or right, increments or decrements a number.

ALU 1 BIT: CODING:

entity ALU1BIT is Port ( X 0 0 INPUT S Y 1 1

TRUTH TABLE: SEL 0 1 OUTPUT A.L.U. ARITHMETIC UNIT LOGIC UNIT

X : in STD_LOGIC; Y : in STD_LOGIC; C_IN : in STD_LOGIC; S : in STD_LOGIC; T : in STD_LOGIC_VECTOR (2 downto 0); C_OUT : out STD_LOGIC; ALU_1OUT : out STD_LOGIC);

end ALU1BIT; architecture Behavioral of ALU1BIT is SIGNAL A, B : STD_LOGIC; COMPONENT AU_NEW is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; C_IN : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); AU : out STD_LOGIC; C_OUT : out STD_LOGIC); end COMPONENT; COMPONENT LU_NEW is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; SEL : in STD_LOGIC_VECTOR (2 downto 0); LU : out STD_LOGIC); end COMPONENT; COMPONENT MUX_TWO is Port ( A : in STD_LOGIC; B : in STD_LOGIC; SEL : in STD_LOGIC; MUX_TWO_OUT : out STD_LOGIC); end COMPONENT; begin ALUO : AU_NEW PORT MAP (X, Y, C_IN, T, A, C_OUT); ALU1 : LU_NEW PORT MAP (X, Y, T, B); ALU2 : MUX_TWO PORT MAP (A, B, S, ALU_1OUT); end Behavioral;

DESIGN:

WAVEFORM:

ALU 4 BIT: CODING:

entity ALU4BIT is Port (

X : in STD_LOGIC_VECTOR (3 DOWNTO 0); Y : in STD_LOGIC_VECTOR (3 DOWNTO 0); C_IN : in STD_LOGIC; S : in STD_LOGIC; T : in STD_LOGIC_VECTOR (2 downto 0); C_OUT : out STD_LOGIC; ALU_4OUT : out STD_LOGIC_VECTOR (3 DOWNTO 0));

end ALU4BIT; architecture Behavioral of ALU4BIT is SIGNAL C : STD_LOGIC_VECTOR (3 DOWNTO 0); COMPONENT ALU1BIT is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; C_IN : in STD_LOGIC; S : in STD_LOGIC; T : in STD_LOGIC_VECTOR (2 downto 0); C_OUT : out STD_LOGIC; ALU_1OUT : out STD_LOGIC); end COMPONENT; begin ALUO : ALU1BIT PORT MAP ( X(0), Y(0), C_IN, S, T, C(0), ALU_4OUT(0)); ALU1 : ALU1BIT PORT MAP ( X(1), Y(1), C(0), S, T, C(1), ALU_4OUT(1)); ALU2 : ALU1BIT PORT MAP ( X(2), Y(2), C(1), S, T, C(2), ALU_4OUT(2)); ALU3 : ALU1BIT PORT MAP ( X(3), Y(3), C(2), S, T, C(3), ALU_4OUT(3)); C_OUT <= C(3); end Behavioral;

DESIGN:

WAVEFORM:

ALU 32 BIT: CODING:

entity ALU32BIT is Port (

X : in STD_LOGIC_VECTOR (31 DOWNTO 0); Y : in STD_LOGIC_VECTOR (31 DOWNTO 0); C_IN : in STD_LOGIC; S : in STD_LOGIC; T : in STD_LOGIC_VECTOR (2 downto 0); C_OUT : out STD_LOGIC; ALU_32OUT : out STD_LOGIC_VECTOR (31 DOWNTO 0));

end ALU32BIT; architecture Behavioral of ALU32BIT is SIGNAL C : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT ALU4BIT is Port ( X : in STD_LOGIC_VECTOR (3 DOWNTO 0); Y : in STD_LOGIC_VECTOR (3 DOWNTO 0); C_IN : in STD_LOGIC; S : in STD_LOGIC; T : in STD_LOGIC_VECTOR (2 downto 0); C_OUT : out STD_LOGIC; ALU_4OUT : out STD_LOGIC_VECTOR (3 DOWNTO 0)); end COMPONENT; begin ALUO : ALU4BIT PORT MAP ( X(31 DOWNTO 28), Y(31 DOWNTO 28), C_in, S, T, C(7), ALU_32OUT(31 DOWNTO 28)); ALU1 : FOR i IN 6 DOWNTO 1 GENERATE ALU2 : ALU4BIT PORT MAP ( X((4*i+3) DOWNTO (4*i)), Y((4*i+3) DOWNTO (4*i)), C(i+1), S, T,C(i), ALU_32OUT((4*i+3)DOWNTO (4*i))); END GENERATE; ALU3 : ALU4BIT PORT MAP ( X(3 DOWNTO 0), Y(3 DOWNTO 0), C(1), S, T, C(0), ALU_32OUT(3DOWNTO 0)); C_OUT <= C(0); end Behavioral;

DESIGN:

WAVEFORM:

Conclusion:The project is being done on the Xilinx I.S.E. 8.2i software. The 32-bit Arithmetic Logic Unit is being created by programming in VHDL module as per Spartan 3E kit board. The diagrammatic representation of the 32 -bits A.L.U. block and the other blocks constituting this block has been observed carefully along with their output waveforms, the output waveforms matches with the theoretical values, they are also being supplied in this report and the presentation coming with this. Do check them for better understanding. This presentation and the report has been made carefully with help from every member of the group.

Future Work:This 32 bit ALU (Arithmetic and Logic Unit) design and waveform implementation can be used to make microprocessor designs and can be used for its calculations and various other purpose.

Reference:   Google.com Wikiepedia.com Electronics devices and Circuits by J. B. Gupta