VL9251

TESTING OF VLSI CIRCUITS

UNIT I
Introduction to testing Faults in Digital Circuits

Modeling of faults
Logical Fault Models Fault detection Fault Location Fault dominance Logic simulation Types of simulation

Delay models
Gate Level Event -Driven simulation

Introduction to testing
Motivation: Moores Law Complexity Growth of VLSI circuits Source (Copp, Int. AOC EW Conf., 2002)

Present and Future

Technology Directions: SIA Roadmap
Year Feature size (nm) Mtrans/cm2 Chip size (mm2) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W) 1999 180 7 170 768 600 6-7 1.8 90 1.4 2002 130 14-26 170-214 1024 800 7-8 1.5 130 2.0 2005 90 47 235 1024 1100 8-9 1.2 160 2.4 2008 45 115 269 1280 1400 9 0.9 170 2.0 2011 32 284 308 1408 1800 9-10 0.6 174 2.2 2014 22 701 354 1472 2200 10 0.6 183 2.4

http://www.itrs.net/ntrs/publntrs.nsf

Verification v/s Testing

Definitions Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

Verification v/s Testing

Verifies correctness of design. Performed by simulation, hardware emulation, or formal methods. Performed once prior to manufacturing. Responsible for quality of design.
Verifies correctness of manufactured hardware. Two-part process:
1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware

Test application performed on every manufactured device. Responsible for quality of devices.

Need for testing

Functionality issue
Does the circuit (large or small) work?

Density issue

Higher density higher failure probability Life critical applications

Application issue Maintenance issue

Need to identify failed components

Cost of doing business What does testing achieve?

Discard only the bad product?

Levels of testing (1)

Levels
Chip Board System
Boards put together System-on-Chip (SoC)

System in field

Cost Rule of 10
It costs 10 times more to test a device as we move to higher level in the product manufacturing process

Levels of testing (2)

Other ways to define levels these are important to develop correct fault models and simulation models
Transistor Gate RTL Functional Behavioral Architecture

Focus: Chip level testing gate level design