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Modeling, Analysis and Simulation of a Buck Converter Under Cascade Control

Chen Zengshi
(Lufkin Industries, Inc., Houston, Texas, USA 77031) Abstract: In this paper, a cascade controller is designed and analyzed for a buck converter. The fast inner current loop uses sliding mode control (SMC). The slow outer voltage loop uses the proportional-integral (PI) control. Stability analysis and selection of PI gains are based on the closed-loop error dynamics. The closed-loop system is proven to have a minimum phase structure. The voltage transients due to step changes of input voltage and load resistance are predictable. The controller is validated by a simulation circuit with non-ideal circuit factors. The simulation results show that the reference output voltage is well tracked under system uncertainties or disturbances, confirming the validity of the proposed controller. Keywords:Buck Converter;Transient;Cascade;SMC;PI

0 Introduction
The buck converter is a typical power conditioning component due to its simple structure and practical functionality of scaling down an input voltage[1]. Since the conventional pulsewidth modulation (PWM) controllers are small signal based, the systems operate optimally only for a specific operating point and often fails to perform satisfactorily under large signal operating condition (system uncertainties and disturbances)[1-4]. Nonlinear feedback controls that are used in DC-DC converters include feedback state linearization, input output linearization, flatness, passivity based control, dynamic feedback control by input-output linearization, exact tracking and error passivity feedback[5]. These tools require PWM modulators, understanding of them needs professional control expertise and practical implementation of them takes uncertain risks. In[6], five recent techniques from hybrid and optimal controls are evaluated on buck and boost converters. The simulations and experiments show that these methods display high performances, while respecting circuit constraints. One-cycle control is applied to Cuk Converter[7]. Synergetic control is applied to buck and boost converters with an incomplete analysis of the closed-loop system stability[8, 9]. In the past three decades, SMC has gained popularity in DC-DC converters[10]. The earliest application of SMC to DC-DC converters was reported in 1983[11] and 1985[12]. The detailed SMC design theory is in[13]. Mainly, SMC makes a system insensitive to disturbances and parametric uncertainties, and reduces the order of the system by the number of switching manifolds or controls. In[14], the various aspects concerning the application of SMC are discussed. It shows that the SMC generates more consistent transient responses for a wide operating range as compared with the conventional linear controls. With phase portraits, extended linearization is proposed for the systematic solution of sliding mode controller design in boost and buck-boost converters[15]. In[5, 13], open loop SMC is applied to various DC-DC converters. The indirect control of the current on a switching manifold is used for output voltage regulation. Unfortunately, open loop SMC lacks robustness against system uncertainties and disturbances. In[16], a PWM-Based sliding mode voltage controller is designed
Brief author introduction:Zengshi Chen earned his Ph.D. degree in systems and controls at The Ohio State University in 2006. He is an automation research scientist in the automation division of Lufkin Industries, Inc. His research interests include variable structure systems, sliding mode control, nonlinear control and their applications to power converters, inverters and renewable energy machines. E-mail: chenzengshi@gmail.com

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for basic DC-DC converters in continuous conduction mode. It is limited to a lower bandwidth application. In[17, 18], sliding mode controllers with dynamic sliding manifolds allow direct control of the voltages of buck, boost and buck-boost converters. However, the output voltage tracking error has to converge to zero asymptotically in sliding mode. In[19], SMC is applied to a buck converter with an assumption of the zero value of the average capacitor current. It is difficult to extend this method to more complicated converters or converters with other modeling methods. In[20], a buck-boost converter uses SMC with the switching manifold as a function of linear combinations of the voltage error and its derivative. In[21], a SMC analog integrated circuit for switching DC-DC converters is developed. The experimental results validate the high-speed functionality of the proposed implementation. PID control is applied to DC-DC converters either in conventional manner or in combination with SMC. The semi-global asymptotic stabilizing properties of classic PI control in the indirect regulation of average models of DC-DC converters are established[22]. A PID auxiliary dynamics is designed for a buck converter under SMC[23]. In[24], generalized PI controllers are applied to buck, boost and buck-boost converters based on integral reconstructors of the unmeasured observable state variables. However, the system robustness with respect to input voltage variation or disturbances is not studied, and extremely large load variation renders loss of feedback for the controller. In[25], a cascade controller with PI control and SMC is applied to a boost converter with the PI gains based on trials and errors. Some simulations results are provided. In this paper, a PI and sliding mode cascade controller is designed and analyzed for a buck converter. This control structure was proposed fifteen years ago but its analytical solution has never been seen in the existing literature[13]. This paper shows a few merits of this controller: it embraces a solid theoretical foundation, it can easily be simulated and implemented, and the closed-loop system is stable and robust. The closed-loop error dynamics is developed. Stability, robustness, power transients, and minimum phase structure of the closed-loop system are analyzed. The algorithm is validated on a simulation circuit with consideration of various non-ideal factors of power devices. This paper is organized as follows. The buck converter model is developed in Section 1. The controller is designed and the closed-loop system is analyzed in Section 2. Simulation is reported in Section 3. Conclusion is in Section 4. References follow.

1 Buck Converter Model

The buck converter is shown in Fig. 1. It consists of an input voltage source E, a MOSFET switch S, an anti-parallel diode d, a freewheeling diode D, a capacitor C, an inductor L and a load resistor R. When S is on, the circuit is shown in Fig. 2. When S is off, the circuit is shown in Fig. 3. Let i be the inductor current and v be the output voltage. As shown in[13], if the control signal u is 1 when S is on and 0 when S is off, the state equations for the buck converter can be represented as (1) i ' = v / L + Eu / L ,
v' = i / C v /(CR )

(2)

where the prime ' refers to the first derivative. Eq. 1 and 2 have the typical variable structure format with the discontinuous right hand side. The control and the input voltage have a bilinear relation.

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i
L

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S
E
D

Fig. 1. Buck converter

i

Fig. 2. Buck converter when the switch S is on.

i

Fig. 3. Buck converter when the switch S is off.

2 Closed-loop Control and Analysis

In this section, the cascade controller is proposed, and the closed-loop system is analyzed.

2.1 Cascade Control

The closed-loop error dynamics involving the voltage and current controllers is developed and analyzed. The structure of the cascade control system is shown in Fig. 4 where i* is the reference current, vd is the reference voltage, and e is the error between vd and v. i is a positive feedback signal due to Eq. 8. v and i are measured.

e
vd

i*

i
Fig. 4. Cascade controller.

2.1.1

Outer Voltage Loop with PI Control

The equilibrium point of the buck converter corresponding to a constant value of the average control input is obtained by letting the right hand side of Eqs. 1 and 2 be zero while the control variable is set to be u=U where U is a constant[5, 13]. The equations for the equilibrium inductor current id and the equilibrium voltage that also equals vd are given by vd / L + Eu / L = 0 , (3)
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id / C vd /(CR ) = 0 .

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(4) (5)

Eliminating U in Eqs. 3 and 4 renders id in terms of vd as id = vd / R .

Eq. 5 provides a theoretical relation between the inductor current and the output voltage when the converter is in the steady state. id can be the feed-forward input current for the converter. With e=vd-v, the reference current for the current loop is generated by a PI controller as
i * = K p e + K i 0edt
t

(6)

where Kp and Ki are the proportional and integral gains, respectively. 2.1.2 Inner Current Loop with SMC
s = i i* .

The switching manifold for the sliding mode current control is designed as (7) (8) For the buck converter, the control scheme is u = 0.5(1 sign(s )) = 1 if s < 0 or 0 if s > 0.

This control structure will be verified when the current loop stability is analyzed. The existence condition of sliding mode can be derived with the candidate Lyapunov function[13]. Let such a function for the system represented by Eqs. 1 and 2 be
V = 0.5s 2 > 0 if s 0 .

(9) (10) (11)

The differentiation of Eq. 7 is

s ' = i 'i * ' = v / L + Eu / L i * ' .

With Eq. 10, the derivative of V is

V ' = ss ' = s[v / L + 0.5E (1 sign(s )) / L i * ' ] 0.5 | s | (| 2v + E 2 Li * ' | E ) / L.

Therefore, the sufficient condition for V'<0 is

| 2v + E 2Li * ' | E < 0 .

(12)

The inequality 12 leads to (13) After sliding mode is reached, s0 and s'0. Consequently, i id and i ' id'=0. Since L is very small, then 2Li*'0. Due to E > 0, v must be positive to guarantee the inequality 13. The inequality 13 defines an attraction domain of the sliding manifold. Because the control in Eq. 8 contains no control gains to be adjusted, the domain of attraction (the inequality 13) is predetermined by the system architecture. In the steady state, the inequality 13 is fulfilled by the definition of a buck converter. The derivation of Eq. 11 implicitly validates Eq. 8 since it results in a stable system.
* *

0 < v + Li* ' < E .

2.1.3

Closed-loop Analysis

In sliding mode, the equivalent control method can be explored[13]. Once the system is in sliding mode, s=0 and s'=0 hold. The discontinuous control u in s'=0 can be replaced by a continuous equivalent control ueq, and s'=0 is solved for ueq. After sliding mode occurs, one has
s = i i* = 0 ,
s ' = v / L + ueq E / L i ' = 0 .
*

(14) (15) (16) (17)

Solving Eq. 15 for ueq renders

ueq = (v + Li * ' ) / E .

With E>0, dividing the inequality 13 by E renders

0 < ueq = (v + Li * ' ) / E < 1 .

Eq. 15 contains the current dynamics represented by Eq. 1. In sliding mode, the current
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dynamics is controlled. It is natural to drop Eq. 1 from the original system, leaving only the voltage dynamics Eq. 2 for study. Plugging i in Eq. 14 and ueq in Eq. 16 into Eq. 2 yields
v ' = i * / C v /(CR) .

(18) (19) (20)

Differentiating Eqs. 6 and 18 renders

i * ' = K p e'+ K i e , v ' ' = i * ' / C v' /(CR) .

where the double prime '' refers to the second derivative. Substituting Eq. 19 into Eq. 20 renders v ' ' = ( K p e'+ K i e) / C v ' /(CR ) (21) With e=vdv, and vd as a constant, v=vde, v'=-e', and v''=-e'' are obtained. Then Eq. 21 becomes
e' '+( K p / C + 1 /(CR ))e'+( K i / C )e = 0 .

(22)

Eq. 22 shows that the closed-loop error dynamics of the buck converter is linear. The characteristic equation of Eq. 22 is K K 1 2 + ( p + ) + i = 0 . (23) If the C CR C desired poles are 1 and 2, the PI gains are 1 K p = C (1 + 2 ) , (24) R K i = C12 . (25) This design renders a globally stable closed-loop system.

2.2

Minimum Phase Output Voltage

Plugging e=vdv and e'=vd'-v' into Eq. 21 results in
v ' ' = ( K p v1 d K p v'+ K i vd K i v ) / C v' /(CR ) .

(26)

The transfer function of Eq. 26 is

F ( s) = RK p s + RK i v (s ) . = vd ( s ) CRs 2 + ( RK p + 1)s + RK i

(27)

With the nominal circuit and control parameters to be shown later on, the zero and poles of F(s) are in the left hand phase plane. The output voltage displays a minimum-phase behavior and is stable.

2.3

Transients with Step Changes of Input Voltage and Load Resistance

When the reference voltage is constant, the transient of the output voltage can still happen if there is a step change for a parameter such as input voltage, resistance, inductance or capacitance. It is useful to predict the transients resulting from step changes of input voltage or load resistance because such variation is common in practice. Since Eq. 22 contains no input voltage variable, the output voltage experiences no transient for input voltage variation. Next, the transient due to step changes of load resistance is studied. Let Rd be the operating point of R and let R be the perturbation of R from Rd. Let v=vd+v where vd is the operating point of v, and v is the perturbation of v from vd. R, i*, and v are the variables to be considered and C is assumed to be constant. Apparently, v=v-vd=-e and v'=-e'. Then, Eq. 19 becomes
i * ' = K p v ' K i v .

(28)

Differentiating Eq. 18 renders

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R 2i * ' = CR 2 v' '+v ' R vR' .

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(29) Plugging R=Rd+R, v=vd+v, and Eqs. 28 into Eq. 29, and dropping the high orders of v, v', v'', R, and R' and any product of some of them render g 3 v ' '+ g 2 v '+ g1v = g 0 R ' (30) where g0=vd, g1=Rd2Ki, g1=Rd2Kp+Rd, and g3=CRd2. The transfer function of Eq. 30 is
G ( s) = v ( s) / R ( s) = g 0 s /( g 3 s 2 + g 2 s + g1 ) .
lim v (t ) = lim sv ( s) = lim[ g 0 s /( g 3 s 2 + g 2 s + g1 )] = 0.
t s 0 s 0

(31) (32)

For a unit step perturbation R(s)=1/s, the final value theorem shows that v converges to 0: Eq. 32 shows that the output voltage transient eventually dies out and the reference voltage is tracked again after a transient. The transient trajectory is also predictable. Based on the nominal parameters shown in Section 3, Eq. 31 becomes
G ( s ) = 9s /(0.0064 s 2 + 48s + 89600).

(33)

The system response of Eq. 33 for a unit step change input is displayed in Fig. 5. The top pane shows the output voltage transient for a positive unit step change of R. It is seen that the voltage transient becomes positive, reaches the maximum value of 0.138 V and converges back to 0 V. The transient lasts about 2 ms. The bottom pane shows the output voltage transient for a negative unit step change of R. It is symmetrical to the transient in the top pane. The preceding work shows that the system output voltage experiences an undershoot when load resistance has a negative step change and an overshoot when it has a positive step change. The amplitude of the undershoot or overshoot is roughly the product of the magnitude of the step change and the transient amplitude caused by a unit step change. These predictions are to be verified by the foregoing simulation.
Output voltage transient for a positive unit step change of load resistance 0.15 0.1 v (V) 0.05 0 -0.05 -1

x 10 Output voltage transient for a negative unit step change of load resistance 0.05 0 v (V) -0.05 -0.1

2 time (Sec)

5
-3

-1

2 time (Sec)

4 x 10

5
-3

Fig. 5. Output voltage transients for a unit step change of load resistance.

3 Simulation
The nominal values of the buck converter parameters are E0 =20 V, R0=40 , L0=0.04 H, C0=4 F, and vd=9 V. As demonstrated in Section 2.1.3, Kp and Ki are obtained through pole placement. In general, a pair of complex poles with a negative and real part leads to an under-damped system; two equal and negative poles render a critically damped system; two unequal and negative poles result in an over-damped system. Two equal and negative poles are applicable to a buck converter since damping is just enough for preventing oscillation in the transient response to a step input. When the poles are closer to zero, the system will be better for
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passing low frequency signals and rejecting noises, but the system response is slower. Furthermore, disturbances or uncertainties can easily bring the system to instability if the poles are close to zero. As the poles diverge from zero, the system response gets faster and the system stability is better. Nevertheless, the fast system response is achieved with a cost. If the poles are far from zero, the magnification of noise at the output will be very large. The choice of pole location is the compromise of noise suppression and the other system performances. In this research, the desired poles are 1=-4000 and 2=-3500. The corresponding PI gains are Kp=0.005 and Ki=56. To show the capability of the proposed controller, a closed-loop simulation circuit for the buck converter is constructed with SimPowerSystems of Simulink Toolbox as shown in Fig. 6. The non-ideal circuit factors are taken into account although they are ignored when the controller is designed. The internal resistances R2=0.8 for the input voltage source E, R3=0.01 for the capacitor C, and R4= 0.1 for the inductor L are included in the circuit. An input voltage E1 and a parallel resistor R1=120 are used to create step changes of input voltage and load resistance through ideal switches. The forward voltage drops and internal resistances of the MOSFET switch S, the diode d and the diode D are considered. They are modeled with Off-the-Shelf device parameters. The parameters for the MOSFET S and its internal anti-parallel diode d are: MOSFET On resistance: 4.5m ; MOSFET forward current: 90 A (Package limitation); Diode d resistance: 0.036 ; Diode d forward voltage: 1.3 V; Diode d forward current: 90A (Package limitation). The parameters for the freewheeling diode D are: On resistance: 0.33 ; Forward voltage: 1.05 V; Forward current: 15 A. The current rating of the MOSFET switch guarantees its safety even if a continuous current goes through it for a long time. The system responses under the following conditions are reported: 1) the inductance and capacitance have uncertainties; 2) the input voltage source has a step change; 3) the load resistance has a step change; 4) the input voltage source has disturbances; 5) the reference voltage has a step change. In the first four cases, the reference voltage is constant. The last case is to test the ability of the controller for tracking a reference voltage with step changes. The simulation fixed-step size is 1 s. Since this paper deals with only simulation without A/D converters, 1 s is also the sampling period. Hence, the minimum sliding mode pulse width is 1 s or the maximum sliding mode switching frequency is 1 MHz. Such switching or sampling frequency is well achievable with modern technologies. After sliding mode occurs and in the steady state, the tracking error caused by chattering is within 1 mA for the inductor current and is within 1 mV for the output voltage. A lower maximum switching frequency (e.g., 10 to 100 kHz) can be used if a larger voltage tracking error is permitted[5, 26]. There are many advanced methods for reducing or eliminating chattering[13]. However, to pursue them is beyond the scope of this paper.

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Fig. 6. Simulation circuit with non-ideal power devices.

3.1

Inductance and Capacitance Uncertainties

Modeling uncertainties are considered with L=120%L0 and C=200%C0. The top pane of Fig. 7 shows that the inductor current i converges to id=0.225 A. The mid pane shows that the output voltage v converges to vd=9 V. The bottom pane shows the control signal u. The closed-loop system is robust against inductance and capacitance uncertainties.
inductor current 0.2 0.1 0 -0.1 i (A)

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 time (Sec) output voltage

0.02

10 v (V) 5 0 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 time (Sec) sliding mode control signal 0.02

1.5 1 0.5 0 -0.5

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 time (Sec)

0.02

Fig. 7. The inductor current, the output voltage and the sliding mode control for inductance and capacitance uncertainties.

3.2

Step Change of Input Voltage

The input voltage E equals 20 V in the first 0.01 seconds, 15 V in the next 0.01 seconds and 20 V in the remaining time. The top pane of Fig. 8 shows that the inductor current i converges to id=0.225 A. The mid pane shows that the output voltage v converges to vd=9 V. The bottom pane shows the control signal u. Although the non-ideal circuit factors are considered, the output voltage transients are still zero when the input voltage E has step changes. This is explained in Section 2.3. The closed-loop system is robust against input voltage variation.
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inductor current 0.2 0.1 0 -0.1 i (A)

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0.005

0.01

0.015 time (Sec) output voltage

0.02

0.025

0.03

10 v (V) 5 0 0 0.005 0.01 0.015 0.02 time (Sec) sliding mode control signal 0.025 0.03

1.5 1 0.5 0 -0.5

0.005

0.01

0.015 time (Sec)

0.02

0.025

0.03

Fig. 8.

The inductor current, the output voltage and the sliding mode control under step changes of input voltage.

3.3

Step Change of Load Resistance

The load resistance is 40 in the first 0.01 seconds, 30 in the next 0.01 seconds and 50 in the remaining time. The top pane of Fig. 9 shows that the inductor current i converges to id=0.225 A in the first 0.01 seconds, id=0.3 A in the next 0.01 seconds and id=0.225 A in the remaining time. The mid pane shows that the output voltage v equals 9 V in the steady state. At the time point of 0.01 seconds, v experiences an undershoot because R has a negative step change. At the time point of 0.02 seconds, v experiences an overshoot since R has a positive step change. These transients are predicted in Section 2.3. The bottom pane shows the control signal u.
inductor current 0.3 0.2 0.1 0 -0.1 i (A)

0.005

0.01

0.015 time (Sec) output voltage

0.02

0.025

0.03

v (V)

10 5 0 0 0.005 0.01 0.015 0.02 time (Sec) sliding mode control signal 0.025 0.03

1.5 1 0.5 0 -0.5

0.005

0.01

0.015 time (Sec)

0.02

0.025

0.03

Fig. 9.

The inductor current, the output voltage and the sliding mode control under step changes of load resistance.

3.4

Input Voltage with Disturbances

The input voltage source is mixed with a Gaussian distributed random signal with the 0 mean and the 2 variance. The noisy input voltage is shown in the top pane of Fig. 10. The smooth inductor current, the smooth output voltage and the sliding mode control are shown in the next three panes. The proposed controller is robust against disturbances and can filter high frequency noise signals.

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input voltage with Gaussian disturbance (mean=0,variance=1) 30 E (V) 20 10

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0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 time (Sec) inductor current

0.01

i (A)

0.2 0.1 0 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 time (Sec) output voltage 0.01

10 v (V) 5 0

0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 time (Sec) sliding mode control signal

0.01

1.5 1 0.5 0 -0.5

0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 time (Sec)

0.01

Fig. 10. The inductor current, the output voltage and the sliding mode control under input voltage mixed with a Gaussian noise signal.

3.5

Step Change of Reference Voltage

The reference voltage vd jumps from 9 V to 12 V at the time point of 0.01 seconds and jumps from 12 V to 9 V at the time point of 0.02 seconds. The top pane of Fig. 11 shows the inductor current i converges to id=0.225 A in the first 0.01 seconds, id=0.3 A in the next 0.01 seconds and id=0.225 A in the remaining time. The mid pane shows that the output voltage v converges to vd=9 V in the first 0.01 seconds, vd=12 V in the next 0.01 seconds and vd=9 V in the remaining time. With the nominal circuit and control parameters, Eq. 27 becomes . (34) Since the zero of F(s) is -11200 and its poles -3500 and -4000, the output voltage is minimum-phase and converges from one level to another monotonically without first going in the opposite direction.
inductor current 0.3 0.2 0.1 0 -0.1 i (A)

F ( s) = (0.2s + 2240) /(0.00016 s 2 + 1.2s + 2240)

0.005

0.01

0.015 time (Sec) output voltage

0.02

0.025

0.03

v (V)

10 5 0 0 0.005 0.01 0.015 0.02 time (Sec) sliding mode control signal 0.025 0.03

1.5 1 0.5 0 -0.5

0.005

0.01

0.015 time (Sec)

0.02

0.025

0.03

Fig. 11.

The inductor current, the output voltage and the sliding mode control under step changes of reference voltage. - 10 -


4 Conclusion

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The main goal of this work is to provide a guideline for the design and analysis of the cascade controller for a buck converter. The physical model and the operating procedure of the converter are introduced. Selection of the PI gains is based on the closed-loop analysis. The voltage transients caused by step changes of reference voltage, input voltage and load resistance are analyzed. The practical circuit is constructed and simulated, considering Off-the-Shelf switch devices and internal resistances of the key circuit components. The simulation results show that the system performs well under system uncertainties and disturbances and accommodates unmodeled parameters and dynamics. The design method is applicable to the other DC-DC converters under the same control structure. The future work includes maximum switching frequency limitation, chattering reduction or elimination, and integrated circuit implementation of the controller. Robust or robustness stated in the paper are the qualitative inferences based on the observations for the simulation results. The future work also includes a rigorous proof on robustness of the proposed controller.

References
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