Lecture 16 : Introduction to PIC Microcontrollers PIC Microcontrollers PIC stands for Peripheral Interface Controller given by Microchip Technology

to identify its single-chip microcontrollers These devices have been very successful in !-bit microcontrollers The main reason is that Microchip Technology has continuously upgraded the device architecture and added needed peripherals to the microcontroller to suit customers" re#uirements The development tools such as assembler and simulator are freely available on the internet at $$$ microchip com The architectures of various PIC microcontrollers can be divided as follo$s Low - end PIC Architectures : Microchip PIC microcontrollers are available in various types %hen PIC microcontroller MC& $as first available from 'eneral Instruments in early 1(!)"s* the microcontroller consisted of a simple processor e+ecuting 1,-bit $ide instructions $ith basic I-. functions These devices are /no$n as lo$-end architectures They have limited program memory and are meant for applications re#uiring simple interface functions and small program 0 data memories 1ome of the lo$-end device numbers are 1,C233 16C23 16C2)2 Mid range PIC Architectures Mid range PIC architectures are built by upgrading lo$-end architectures $ith more number of peripherals* more number of registers and more data-program memory 1ome of the mid-range devices are 16C63 16C43 165!43 Program memory type is indicated by an alphabet C 6 7P8.M 5 6 5lash 8C 6 Mas/ 8.M

Popularity of the PIC microcontrollers is due to the follo$ing factors 1peed: 9arvard :rchitecture* 8I1C architecture* 1 instruction cycle 6 ; cloc/ cycles Instruction set simplicity: The instruction set consists of <ust =2 instructions >as opposed to 111 instructions for !)21? Po$er-on-reset and bro$n-out reset @ro$n-out-reset means $hen the po$er supply goes belo$ a specified voltage >say ;A?* it causes PIC to resetB hence malfunction is avoided : $atch dog timer >user programmable? resets the processor if the soft$are-program ever malfunctions and deviates from its normal operation PIC microcontroller has four optional cloc/ sources Lo$ po$er crystal Mid range crystal 9igh range crystal 8C oscillator >lo$ cost? Programmable timers and on-chip :CC &p to 1, independent interrupt sources Po$erful output pin control >,2 m: >ma+ ? current sourcing capability per pin ? 7P8.M-.TP-8.M-5lash memory option I-. port e+pansion capability 5ree assembler and simulator support from Microchip at $$$ microchip com CPU Architecture: The CP& uses 9arvard architecture $ith separate Program and Aariable >data? memory interface This facilitates instruction fetch and the operation on data-accessing of variables simultaneously

5ig 16 1 CP& :rchitecture of PIC microcontroller PIC Memory Organisation: PIC microcontroller has 1= bits of program memory address 9ence it can address up to !/ of program memory The program counter is 1=-bit PIC 16C63 or 16C43 program memory is ,/ or ;/ %hile addressing ,/ of program memory* only 11- bits are re#uired 9ence t$o most significant bits of the program counter are ignored 1imilarly* $hile addressing ;/ of memory* 1, bits are re#uired 9ence the M1b of the program counter is ignored

5ig 16 , Program Memory map The program memory map of PIC16C4;: is sho$n in 5ig 16 , .n reset* the program counter is cleared and the program starts at ))9 9ere a "goto" instruction is re#uired that ta/es the processor to the mainline program %hen a peripheral interrupt* that is enabled* is received* the processor goes to ));9 : suitable branching to the interrupt service routine >I18? is $ritten at ));9 Data memory (Register iles!:

Cata Memory is also /no$n as 8egister 5ile 8egister 5ile consists of t$o components 'eneral purpose register file >same as 8:M? 1pecial purpose register file >similar to 158 in !)21?

ig "#$% Data Memory ma& The special purpose register file consists of input-output ports and control registers :ddressing from ))9 to 559 re#uires ! bits of address 9o$ever* the instructions that use direct addressing modes in PIC to address these register files use 4 bits of instruction only Therefore the register ban/ select >8P)? bit in the 1T:T&1 register is used to select one of the register ban/s In indirect addressing 518 register is used as a pointer to any$here from ))9 to 559 in the data memory

Lecture "' : (asic Architecture o) PIC Microcontrollers 1pecifications of some popular PIC microcontrollers are as follo$s: De*ice 16C4;: Program Memory ("+,its! ;D 7P8.M !D 5lash Data RAM (,ytes! 1(, I-O ADC Pins == ! bits + ! channels 1) bits + ! channels .imers CCP /-"# (P0M! ,its ,-1 , U1AR. 1PI I2C &1:8T 1PI , I C &1:8T 1PI , I C

165!44

De*ice 16C4;: 165!44

=6! >8:M? == ,26 >77P8.M? Interru&t Instruction 1ources 1et 1, 12 =2 =2

,-1

PIC Microcontroller Cloc3 Most of the PIC microcontrollers can operate upto ,)M9E .ne instructions cycle >machine cycle? consists of four cloc/ cycles ig "'$" Relation ,etween instruction cycles and cloc3 cycles )or PIC microcontrollers Instructions that do not re#uire modification of program counter content get e+ecuted in one instruction cycle :lthough the architectures of various midrange ! - bit PIC microcontroller are not the same* the variation is mostly interns of addition of memory and peripherals %e $ill discuss here the architecture of a standard mid-range PIC microcontroller* 16C4;: &nless mentioned other$ise* the information given here is for a PIC 16C4;: microcontroller Chip

Architecture o) PIC"#C'+A

ig "'$2 (asic Architecture o) PIC "#C'+A The basic architecture of PIC16C4;: is sho$n in fig 14 , The architecture consists of Program memory* file registers and 8:M* :L& and CP& registers It should be noted that the program Counter is 1= - bit and the program memory is organised as 1; - bit $ord 9ence the program Memory capacity is !/ + 1; bit 7ach instruction of PIC 16C4;: is 1; - bit long The various CP& registers are discussed here

CPU registers (registers commonly used ,y the CPU! %* the $or/ing register* is used by many instructions as the source of an operand This is similar to accumulator in !)21 It may also serve as the destination for the result of the instruction e+ecution It is an ! - bit register

ig "'$%

0 register

1.A.U1 Register The 1T:T&1 register is a !-bit register that stores the status of the processor This also stores carry* Eero and digit carry bits 1T:T&1 - address )=9* !=9

ig "'$+ 1.A.U1 register C 6 Carry bit CC 6 Cigit carry >same as au+iliary carry? F 6 Fero bit G.THT. and G.THPC - &sed in con<unction $ith PIC"s sleep mode 8P)8egister ban/ select bit used in con<unction $ith direct addressing mode 1R Register >5ile 1election 8egister* address 6 );9* !;9? 518 is an !-bit register used as data memory address pointer This is used in indirect addressing mode IGC5 8egister >IGCirect through 518* address 6 ))9* !)9? IGC5 is not a physical register :ccessing IGC5 access is the location pointed to by 518 in indirect addressing mode PCL Register >Program Counter Lo$ @yte* address 6 ),9* !,9? PCL is actually the lo$er !-bits of the 1=-bit program counter This is a both readable and $ritable register PCLA.4 Register >Program Counter Latch* address 6 ):9* !:9?

PCL:T9 is a !-bit register $hich can be used to decide the upper 2bits of the program counter PCL:T9 is not the upper 2bits of the program counter PCL:T9 can be read from or $ritten to $ithout affecting the program counter The upper =bits of PCL:T9 remain Eero and they serve no purpose %hen PCL is $ritten to* the lo$er 2bits of PCL:T9 are automatically loaded to the upper 2bits of the program counter* as sho$n in the figure

ig "'$5 1chematic o) how PCL is loaded )rom PCLA.4 Program Counter 1tac3 :n independent !-level stac/ is used for the program counter :s the program counter is 1=bit* the stac/ is organiEed as !+1=bit registers %hen an interrupt occurs* the program counter is pushed onto the stac/ %hen the interrupt is being serviced* other interrupts remain disabled 9ence* other 4 registers of the stac/ can be used for subroutine calls $ithin an interrupt service routine or $ithin the mainline program Register ile Ma&

5ig 14 6 8egister 5ile Map It can be noted that some of the special purpose registers are available both in @an/-) and @an/-1 These registers have the same value in both ban/s Changing the register content in one ban/ automatically changes its content in the other ban/ Port 1tructure and Pin Con)iguration o) PIC "#C'+A :s mentioned earlier* there is a large variety of PIC microcontrollers 9o$ever* the midrange architectures are $idely used .ur discussion $ill mainly confine to PIC16C4;: $hose architecture has most of the re#uired features of a midrange PIC microcontroller 1tudy of any other mid-range PIC microcontroller $ill not cause much variation from the basic architecture of PIC 16C4;:

PIC 16C4;: has 2 I-. Ports 7ach port is a bidirectional I-. port In addition* they have the follo$ing alternate functions

In addition to I-. pins* there is a Master clear pin >MCL8? $hich is e#uivalent to reset in !)21 9o$ever* unli/e !)21* MCL8 should be pulled lo$ to reset the micro controller 1ince PIC16C4;:has inherent po$er-on reset* no special connection is re#uired $ith MCL8 pin to reset the micro controller on po$er-on There are t$o ACC pins and t$o A11 pins There are t$o pins >.1C1 and .1C,? for connecting the crystal oscillator- 8C oscillator 9ence the total number of pins $ith a 16C4;: is ==I46;) This IC is commonly available in a dual-in-pin >CIP? pac/age

Fig 17.7 Pin configuration of PIC 16C74A

Lecture "/ : Instruction 1et o) PIC Microcontroller

6uidelines )rom Microchi& .echnology 5or $riting assembly language program Microchip Technology has suggested the follo$ing guidelines %rite instruction mnemonics in lo$er case >e g * mov$f? %rite the special register names* 8:M variable names and bit names in upper case >e g * PCL* 8P)* etc ? %rite instructions and subroutine labels in mi+ed case >e g * Mainline* LoopTime? Instruction 1et: The instruction set for PIC16C4;: consists of only =2 instructions 1ome of these instructions are byte oriented instructions and some are bit oriented instructions The byte oriented instructions that re#uire t$o parameters >5or e+ample* movf f* 5>%?? e+pect the f to be replaced by the name of a special purpose register >e g * P.8T:? or the name of a 8:M variable >e g * G&M1?* $hich serves as the source of the operand "f" stands for file register The 5>%? parameter is the destination of the result of the operation It should be replaced by: 5* if the destination is to be the source register %* if the destination is to be the $or/ing register >i e * :ccumulator or % register? The ,it oriented instructions also e+pect parameters >e g * btfsc f* b? 9ere "f" is to be replaced by the name of a special purpose register or the name of a 8:M variable The "b" parameter is to be replaced by a bit number ranging from ) to 4 5or e+ample: F e#u , btfsc 1T:T&1* F F has been e#uated to , 9ere* the instruction $ill test the F bit of the 1T:T&1 register and $ill s/ip the ne+t instruction if F bit is clear The literal instructions re#uire an operand having a /no$n value >e g * ):9? or a label that represents a /no$n value 5or e+ample: G&M e#u ):9 B :ssigns ):9 to the label G&M > a constant ?

movl$ G&M B $ill move ):9 to the % register 7very instruction fits in a single 1;-bit $ord In addition* every instruction also e+ecutes in a single cycle* unless it changes the content of the Program Counter These features are due to the fact that PIC micro controller has been designed on the principles of 8I1C >8educed Instruction 1et Computer? architecture Instruction set: Mnemonics bcf f* b bsf f* b clr$ clrf f movl$ / mov$f f movf f* 5>%? s$apf f* 5>%? andl$ / and$f f* 5>%? and$f f* 5>%? iorl$ / ior$f f* 5>%? +orl$ / +or$f f* 5>%? addl$ / Descri&tion Clear bit b of register f 1et bit b of register f Clear $or/ing register % Clear f Move literal "/" to % Move % to f Move f to 5 or % 1$ap nibbles of f* putting result in 5 or % :nd literal value into % :nd % $ith 5 and put the result in % or 5 :nd % $ith 5 and put the result in % or 5 inclusive-.8 literal value into % inclusive-.8 % $ith f and put the result in 5 or % 7+clusive-.8 literal value into % 7+clusive-.8 % $ith f and put the result in 5 or % :dd the literal value to % and store the result in % Instruction Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

add$f f* 5>%? subl$ / sub$f f* 5>%? rlf f* 5>%? rrf f* 5>%? btfsc f* b btfss f* b decfsE f* 5>%?

:dd % to f and store the result in 5 or % 1ubtract the literal value from % and store the result in %

1 1

1ubtract f from % and store the result in 5 or % 1 Copy f into 5 or %B rotate 5 or % left through the carry bit Copy f into 5 or %B rotate 5 or % right through the carry bit Test "b" bit of the register f and s/ip the ne+t instruction if bit is clear Test "b" bit of the register f and s/ip the ne+t instruction if bit is set Cecrement f and copy the result to 5 or %B s/ip the ne+t instruction if the result is Eero Increment f and copy the result to 5 or %B s/ip the ne+t instruction if the result is Eero 'o to the instruction $ith the label JlabelJ 'o to the subroutine JlabelJ* push the Program Counter in the stac/ 8eturn from the subroutine* P.P the Program Counter from the stac/ 8etrun from the subroutine* P.P the Program Counter from the stac/B put / in % 1 1 1-, 1-,

1-,

incfcE f* 5>%? goto label

1-, ,

call label retrun

, ,

retl$ / retie clr$dt sleep nop

, 8eturn from Interrupt 1ervice 8outine and reenable interrupt , Clear %atch Cog Timer 1 'o into sleep- stand by mode 1 Go operation 1

7ncoding o) instruction: :s has been discussed* each instruction is of 1;-bit long These 1;-bits contain both op-code and the operand 1ome e+amples of instruction encoding are sho$n here 7+ample-1:

7ncoding: The instruction is e+ecuted in one instruction cycle* i e * ; cloc/ cycles The activities in various cloc/ cycles are as follo$s

1ince this instruction re#uires modification of program Counter* it ta/es t$o instruction cycles for e+ecution K-Cycle activities are sho$n as follo$s

Lecture "8 : I-O Port Con)iguration

Discussion on I-O &orts o) PIC"#C'+A: PIC16C4;: has five I-. ports Port-@* Port-C and Port-C have ! pins each Port-: and Port-7 have 6 and = pins respectively 7ach port has bidirectional digital I-. capability In addition* these I-. ports are multiple+ed $ith alternate functions for the peripheral devices on the microcontroller In general* $hen a peripheral is enabled* that pin may not be used as a general purpose I-. pin 7ach port latch has a corresponding T8I1 >Tri-state 7nable? register for configuring the port either as an input or as an output The port pins are designated by the alphabet 8* follo$ed by the respective port >viE :* @* C* C or 7? and the pin number 5or e+ample* Port-: pins are named as 8:)* 8:1* etc Port-A Port-: pins 8:)-8:= and 8:2 are similar These pins function >alternate function? as analog inputs to the analog-to-digital converter

ig "8$" RA9-RA% and RA5 &in o) Port-A The structure of Port-: pins 8:)-8:= and 8:2 is sho$n in the figure T8I1: register decides $hether the port-pin is configured as an input or as an output >digital? pin 1etting a T8I1: register bit puts the corresponding output driver in high impedance mode In this mode* the pin can be used as a digital or analog input Clearing a bit in the T8I1: register puts the contents of the data latch on the selected pins* i e * the pin functions as a digital output Pins 8:)8: and 8:2 have current sourcing capability of ,2m:

The alternate function of 8:; pin is Timer-) cloc/ input >T)CDI? 8:; pin is an open drain pin and hence re#uires e+ternal pull-up $hen configured as output pin It is sho$n in the follo$ing figure

ig "8$2 RA+ &in Con)iguration

Con)iguration o) Port-A &ins

Port-( Port-@ is an !-bit bidirectional I-. port The data direction in Port-@ is controlled by T8I1@ register 1etting a bit in T8I1@ register puts the corresponding output in high impedance input mode %hen a bit in T8I1@ is made Eero* the corresponding pin in Port-@ outputs the content of the latch >output mode? 7ach port pin has a $ea/ internal pull-up that can be enabled by clearing bit of .PTI.G register >bit-4? %hen a pin is configured in the output mode* the $ea/ pull-up is automatically turned off Internal pull- up is used so that $e can directly drive a device from the pins

ig "8$% Pins R(9-R(% o) Port-( Con)iguration o) Port-( &ins 7+ample : 1et 8@)-8@= as outputs* 8@;-8@2 as inputs* 8@4 as output bcf 1T:T&1* 8P) clrf P.8T@ bsf 1T:T&1* 8P) movl$ 4)9 mov$f T8I1@

Lecture 29 :.imer modules in PIC Microcontroller O*er*iew o) .imer Modules : PIC 16C4;: has three modules* viE * Timer-)* Timer-1 and Timer-, Timer-) and Timer-, are !-bit timers Timer-1 is a 16-bit timer 7ach timer module can generate an interrupt on timer overflo$ .imer-9 O*er*iew: The timer-) module is a simple !-bit &P counter The cloc/ source can be either the internal cloc/ >fosc -;? or an e+ternal cloc/ %hen the cloc/ source is e+ternal* the Timer-) module can be programmed to increment on either the rising or falling cloc/ edge Timer-) module has a programmable pre-scaler option This pre-scaler can be assigned either to Timer-) or the %atch dog timer* but not to both The Timer-) Counter sets a flag T)I5 >Timer-) Interrupt 5lag? $hen it overflo$s and can cause an interrupt at that time if that interrupt source has been enabled* >T)I7 6 1?* i e * timer-) interrupt enable bit 6 1 OP.IO: Register Con)iguration : .ption 8egister >:ddr: !19? Controls the prescaler and Timer -) cloc/ source The follo$ing .PTI.G register configuration is for cloc/ source and no %atchdog timer

.imer-9 use without &re-scalar Internal cloc/ source of f osc -; >7+ternal cloc/ source* if selected* can be applied at 8:;-T.CDI input at P.8T:? The follo$ing diagram sho$s the timer use $ithout the prescaler

Fig 20.1 Timer - 0 operation without prescaler .imer-9 use with &re-scalar: The pre-scalar can be used either $ith the Timer-) module or $ith the %atchdog timer The pre-scalar is available for Timer-) if the pre-scalar assignment bit P1: in the .PTI.G register is ) Pre-scalar is a programmable divide by n counter that divides the available cloc/ by a pre-specified number before applying to the Timer-) counter

5ig ,) , Timer - ) $ith prescaler

Lecture 2" : .imer modules in PIC Microcontroller (contd$! .imer - " Module Timer 1 module is a 16-bit timer-counter consisting of t$o !-bit registers >TM819 and TM81L? $hich are readable and $ritable The TM81 register pair >TM819:TM81L? increments from ))))9 to 55559 and rolls over to ))))9 The TM81 interrupt* if enabled* is generated on overflo$* $hich sets the interrupt flag bit TM81I5 >bit-) of PI81 register? This interrupt can be enabled-disabled by setting-clearing TM81 interrupt enable bit TM81I7 >bit-) of the PI71 register? The operating and control modes of Timer1 are determined by the special purpose register T1C.G Aarious bits of T1C.G register are given as follo$s:5ig ,1 1 T1C.G 8egister

1elect ,its ."C<P1" 1 1 ."C<P19 1 )

Prescaler ;alue 1:! 1:;

) ) 5ig ,1 ,

1 )

1:, 1:1

.peration of Timer 1

Timer 1 can operate in one of the t$o modes

:s a timer >TM81C1 6 )? In the timer mode* Timer 1 increments in every instruction cycle The timer 1 cloc/ source is 1ince the internal cloc/ is selected* the timer is al$ays synchroniEed and there is no further need of synchroniEation :s a counter >TM81C1 6 1? In the counter mode* e+ternal cloc/ input from the pin 8C.-T1CDI is selected Reading and writing .imer " 8eading TM819 and TM81L from Timer 1* $hen it is running from an e+ternal cloc/ source* have to be done $ith care 8eading TM819 or TM81L for independent ! - bit values does not pose any problem %hen the 16-bit value of the Timer is re#uired* the high byte >TM819? is read first follo$ed by the lo$ byte >T981lL? It should be ensured that TM81L does not overflo$ >that is goes from 559 to ))9? since T9819 $as read This condition is verified by reading TM819 once again and comparing $ith previous value of TM819 7+ample Program 8eading 16bit of free running Timer 1 movf TM819 B read high byte

.imer 2 O*er*iew

ig 2"$% 1chematic diagram showing o&eration o) .imer 2 Timer , is an ! - bit timer $ith a pre-scaler and a post-scaler It can be used as the P%M time base for P%M mode of capture compare P%M >CCP? modules The TM8, register is readable and $ritable and is cleared on device reset The input cloc/ > ? has a pre-scaler option of 1:1* 1:; or 1:16 $hich is selected by bit ) and bit 1 of T,C.G register respectively The Timer , module has an !bit period register >P8,? Timer-, increments from ))9 until it is e#ual to P8, and then resets to ))9 on the ne+t cloc/ cycle P8, is a readable and $ritable register P8, is initailised to 559 on reset The output of TM8, goes through a ;bit post-scaler >1:1* 1:,* to 1:16? to generate a TM8, interrupt by setting TM8,I5

5ig ,1 ; The T,C.G 8egister

Interrupt Logic in PIC 16C4;: PIC 16C4;: microcontroller has one vectored interrupt location >i e * )));9? but has 1, interrupt sources There is no interrupt priority .nly one interrupt is served at a time 9o$ever interrupts can be mas/ed The interrupt logic is sho$n belo$ :

5ig ,1 2 1chematic diagram sho$ing the interrupt logic for PIC

Lecture 22 : CCP Modules

Ca&ture - Com&are -P0M (CCP! Modules: PIC16C4;: has t$o CCP Modules 7ach CCP module contains a 16 bit register >t$o !-bit registers? and can operate in one of the three modes* viE * 16-bit capture* 16-bit compare* or up to 1)-bit Pulse %idth Modulation >P%M? The details of the t$o modules >CCP1 and CCp,? are given as follo$s CCP" Module: CCP1 Module consists of t$o !-bit registers* viE * CCP81L >lo$ byte? and CCP819 >high byte? The CCP1C.G register controls the operation of CCP1 Module

CCP2 Module: CCP, Module consists of t$o ! bit registers* viE * CCP8,L >Lo$ byte? and CCP8,9 >high byte? The CCP1C.G register controls the operation of CCP, Module @oth CCP1 and CCP, modules are identical in operation $ith the e+ception of the operation of special event trigger The follo$ing table sho$s the timer resources for the CCP Mode CCP Mode Capture Compare P%M Timer &sed Timer 1 Timer 1 Timer ,

CP1C.G 8egister >:ddress 149? CCP,C.G 8egister is e+actly similar to CCP1C.G register CCP,C.G 8egister address is 1C9 CCP1C.G controls CCP module1 $here as CCP,C.G controls CCP Module,

@it 2-;: CCP13 CCP1L: P%M least significant bits These bits are of no use in Capture mode In P%M Mode* these bits are the t$o Lsbs of the P%M duty cycle The eight Msbs are found in CCP81L Thus the P%M mode operates in 1)-bit mode @it =-): CCP1M=:CCP1M. >CCP1 Mode select bits? ))))6Capture-Compare-P%M Mode off )1))6Capture mode* every falling edge )1)16Capture mode* every rising edge

)11)6Capture mode* every ; th rising edge )1116Capture mode* every 16 th rising edge 1)))6Compare mode* set output on match >CCP1I5 bit is set? 1))16Compare mode* clear output on match >CCP1I5 bit is set? 1)1)6Compare mode* generate soft$are interrupt on match >CCP1I5 bit is set* CCP1 pin unaffected? 1)116Compare mode* trigger special event >CCP1I5 bit is setBCCP1 resets Tmr1B CCP, resets TM81 and starts :-C conversion if :-C module is 7nabled? 11336P%M mode Ca&ture Mode (CCP"!: Capture Mode captures the 16-bit value of TM81 into CCP819:CCP81L register pair in response to an event occurring on 8C,-CCP1 pin Capture Mode for CCP, is e+actly similar to that of CCP1 :n event on 8C,-CCP1 pin is defined as follo$s: 7very falling edge 7very rising edge 7very ; th rising edge 7very 16 th rising edge :s mentioned earlier* this event is decided by bit =-) of CCP1C.G register 1chematic diagram )or ca&ture mode o) o&eration

5ig ,, 1 Capture operation

Re=uired condition )or ca&ture mode: 8C,-CCP1 pin should be configured as an input by setting T8I1C >bit ,? Timer 1 should be operated from the internal cloc/ >fosc-;?* i e * timer mode or in synchroniEed counter mode Com&are Mode (CCP"! Compare mode for CCP, is similar to that of CCP1* e+cept that in special event trigger mode* CCP1 resets TM81 only* $hereas CCP, resets TM81 and starts :-C conversion if :-C module is enabled In compare mode* the 16-bit CCP81 register value is compared against TM81 register pair >TM819 and TM81L? value %hen a match occurs* the 8C,-CCP1 pin is driven high or driven lo$ or remains unchanged as decided by CCP1C.GM=:)N bits

ig 22$2 Com&are O&eration Re=uired conditions )or com&are mode 8C,-CCP1 pin must be configured as an output by clearing T8I1CM,N bit Timer-1 should be operated in timer mode >i e * internal cloc/ source of fosc-;? or in synchroniEed counter mode In soft$are interrupt mode* CCP1I5 bit is set but CCP1 pin in unaffected :s sho$n in the figure* in special event trigger mode* both CCP1 and CCP, intiates an :-C conversion P0M mode (CCP"! @oth CCP1 and CCP, have similar operation in P%M mode 9ere $e $ill discuss P%M $ith respect to CCP1

In P%M mode* the CCP1 pin produces upto a 1)-bit resolution Pulse %idth Modulation >P%M? output 8C,-CCP1 pin should be configured in the uotput mode by clearing T8I1CM,N bit The schematic bloc/ diagram of CCP1 module in P%M mode is sho$n in the figure

ig 22$% P0M O&eration It can be noted that P8, >Period 8egister* ! bit? decides the P%M period $here CCP81L >!-bits? and CCP1C.G M2:;N >,-bits? decide the P%M duty cycle %hen TM8, e#uals P8,* the 18 latch is set and 8C,-CCP1 pin is pulled high In the same time* TM8, is cleared and the duty cycle value available in CCP81L is latched to CCP819 CCP819* CCP1C.G M2:;N decide the duty cycle and $hen this 1)-bit e$#uals the TM8,I, prescaler or K-bits* the 18 latch is set and 8C,-CCP1 pin is driven lo$

: P%M output as sho$n has a time period The time for $hich the output stays high is called duty cycle P0M Period The P%M period is specified by $riting to P8, register The P%M period can be calculated using the follo$ing formula: P%M period 6 O> P8 ,? I 1P Q ; Q T osc Q >TM8, prescale value? P%M fre#uency 6 1- P%M period %hen TM8, is e#ual to P8,* the follo$ing events occur on the ne+t increment cycle TM8, is cleared the CCP1 pin is set >if P%M duty cycle is ) The P%M duty cycle is latched from CCP81L into CCP819

P0M duty cycle The P%M duty cycle is specified by $riting to the CCP81L register and to CCP1C.G M 2 : ; N bits &p to 1)-bit resolution is available $here CCP81L contains the eight M1@s and CCP1C.G M 2 : ; N contains the t$o L1@"s The 1)-bit value is represented by CCP81L : CCP1C.G M 2 : ; N The P%M duty cycle is given by P%M duty cycle 6 >CCP81L : CCP1C.G M 2 : ; N ? T osc >TM8, prescale value? To understand the 1)-bit counter configuration from Timer-,* let us first see the counting mechanism of Timer-,* as sho$n in 5ig ,, ;

ig 22$+ Counting mechanism in .imer - 2 If the prescaler is 1* the 1)-bit counter is configured as follo$s

ig 22$5 Prescaler set to di*ide ,y one If the prescaler is ;* the 1)-bit counter is configured as follo$s

ig 22$# Prescaler &rogramed to di*ide ,y )our If the prescaler is 16* the 1)-bit counter is realiEed as follo$s

ig 22$' Prescaler &rogramed to di*ide ,y "# :lthough CCP81L and CCP1C.G M 2 : ; N can be $ritten to at anytime* the duty cycle value is not latched into CCP819 until a match bet$een P8, and TM8, occurs In P%M mode* CCP819 is a read-only register The CCP819 register and a ,-bit internal latch are used to double buffer the P%M duty cycle This double buffering is essential for glitchless P%M operation %hen the CCP819 and ,-bit latch match TM8, concatenated $ith an internal ,-bit K cloc/ or ,-bits of prescaler* the CCP1 pin is cleared Ma+imum P%M resolution >bits? for a given P%M fre#uency can be calculated as

If the P%M duty cycle is longer than the P%M period* then the CCP1 pin $ill not be cleared P%M Period and duty cycle calculation

7+ample: Cesired P%M fre#uency 6 4! 1,2 /9E

5ind the ma+imum resolution of duty cycle that can be used $ith a 4! 1,; /9E fre#uency and ,) M9E oscillator

,26 6 ,P%M 8esolution :t most* an !-bit resolution duty cycle can be obtained from a 4! 1,2 /9E fre#uency and ,) M9E oscillator ie* ) CCP81L : CCP1C.G M2 : ;N R ,22 :ny value greater than ,22 $ill result in a 1)) S duty cycle The follo$ing table gives the P%M fre#uency fP%M if fosc 6 ,)M9E Duty 10-Bit PR2 cycle counte value resolutio r scale n Prescaler 1 Prescaler 4 Prescaler 16

10 bit 10 bit 8 bit 6 bit

1024 1000 256 64

255 249 63 15

19.53 KHz 20kHz 78.125k Hz 312.5kH z

4.88 kHz 5kHz

1.22 kHz 1.25kHz

19.53kH 4.88kHz z 78.125k 19.53kH Hz z

Lecture 2% : Analog to Digital Con*ertor Module

ADC Module :n analog-to-digital converter >:CC? converts an analog signal into an e#uivalent digital number PIC 16C4;: has an inbuilt :CC $ith the follo$ing features !-bit conversion ! analog input channels :n analog multiple+er : sample and hold circuit for signal on the selected input channel :lternative cloc/ sources for carrying out conversion :d<ustable sampling rate Choice of an internal or e+ternal reference voltage Interrupt to microcontroller on end of conversion Port : and Port 7 pins are used for analog inputs-reference voltage for :CC In :-C conversion* the input analog voltage is digitiEed and an e#uivalent digital output is generated as sho$n in the figure

ig 2%$" Digital out&ut *ersus analog in&ut

Port-: pins >:lternate functions? 8:)-:G) 8:1-:G1 8:,-:G, can be used as analog input-) can be used as analog input-1 can be used as analog input-, can be used as analog input-= or analog reference voltage cloc/ input to Timer-) can be used for analog input ; or slave select for the synchroniEed serial port Port-7 pins >:lternate functions? 87)- -:G2 - can be used as analog input-2 871- -:G6 - can be used as analog input-6 87,- -:G4 - can be used as analog input-4 PIC microcontroller has internal sample and hold circuit The input signal should be stable across the capacitor before the conversion is initiated

8:=-:G=-Aref 8:;-T.CDI 8:2- -:G; -

ig 2%$2 1am&le and 4old Circuit :fter $aiting for the sampling time* a conversion can be initiated The :CC Circuit $ill open the sampling s$itch and carry out the conversion of the input voltage as it $as at the moment of opening of the s$itch &pon completion of the conversion* the sampling s$itch is again closed and A9old once again trac/s A1ource &sing the :-C Converter 8egisters :CC.G1* T8I1:* and T8I17 must be initialiEed to select the reference voltage and input channels The first step selects the :CC cloc/ from among the four choices >fosc-,* fosc-!* fosc-=,* and 8C? The constraint for selcting cloc/ fre#uency is that the :CC cloc/ period must be 1 6micro seconds or greater

The :-C module has =registers These registers are::-C result register >:C871? :-C control register ) >:CC.G )? :-C control register 1 >:CC.G 1? The :CC.G) register* $hich is sho$n belo$* controls the operation of :-C module

ig 2%$% ADCO:9 register @it 4-6 - :-C Cloc/ select bits :CC11::CC1) )) 6 fosc-, )1 6 fosc-! 1) 6 fosc-=, 11 6 f8C- cloc/ derived from an internal 8C oscillator @it 2-= - :-C Channel 1elect C91,:C91) ))) - Channel ) - :G) ))1 - Channel 1 - :G1 )1) - Channel , - :G, )11 - Channel = - :G= 1)) - Channel ; - :G; 1)1 - Channel 2 - :G2 11) - Channel 6 - :G6 111 - Channel 4 - :G4

:CC.G1 8egister This register specifies the analog inputs

ig 2%$+ ADCO:" register

PCFG2:PC FG0 000 001 010 011 100 101 11X

RA RA RA RA RA RE RE RE VRE 0 1 2 5 3 0 1 2 F A A A A A A A A VD
D

A A A A A D

A A A A A D

A A A D D D

A A A D D D

VRE A
F

A D D D D D

A D D D D D

RA
3

VD
D

VRE D
F

RA
3

VD
D

VRE D
F

RA
3

ig 2%$5 PC 62:PC 69 > A-D Port con)iguration control ,its

: 6 :nalog input C 6 Cigital I-.

ig 2%$# 1chematic diagram o) A-D con*ertor analog in&uts and re)erence *oltage 1teps for :-C conversion Configure :-C module Configure analog inputs-voltage reference and digital I-. >:CC.G1? 1elect :-C Channel >:CC.G)? 1elect :-C Conversion Cloc/ >:CC.G)? Turn on :-C Module >:CC.G)? Configure :-C Interrupt >.ptional? Clear :CI5 bit in PI81 register 1et :CI7 bit in PI71 register 1et 'I7 bit

7?am&le Program :-C conversion $ith interrupt

Interrupt 1ervice 8outine .rg ));9 Movf :C871* % B 8esult of :-C conversion in % Consideration of 1ampling Time %hen a channel is selected >$riting to :CC.G)?* the s$itch "1%" in 5ig ,= ! is closed* changing C9.LC to A1ource %hen :-C conversion is started >setting 'o bit in :CC.G)?* 1% is opened The time from the closure of "1%" till the voltage across C9.LC >Ao? reaches A1ource is the minimum sampling time Ts The actual sampling time can be higher than Ts The graph bet$een Ts and source resistance 81ource is sho$n in 5ig ,= 4 I

ig 2%$' Relation ,etween sam&ling time and source resistance

ig 2%$/ 1am&ling circuit in the PIC @C 8ss is the resistance of the sampling s$itch "1%" and C 9old is the charge holding capacitance C9old is nearly 2)p5 81ource is the impedance of the e+ternal analog source Asource .nce the s$itch "1%" is closed* the capacitor Chold ta/es some time to charge up This time it is called the sampling time >T s? This time varies linearly $ith 81ource as sho$n The recommended value of impedance of the e+ternal analog source* Asource* is less than 1)/T The circuit in 5ig ,= ! is a first order 8C circuit %hen 1% is closed* A o varies as sho$n in 5ig ,= (

5ig ,= ( *5rom 5ig ,= (*

Lecture 2# : I2C Communication in PIC Microcontroller:

I2C Communication in PIC Microcontroller I,C stands for Inter-Integrated circuit I,C communication is a t$o $ire bidirectional interface for connecting one or more master processors

$ith one or more slave devices* such as an 77P8.M* :CC* 8:M* LCC display* C:C* etc I,C interface re#uires t$o open drain I-. pins* viE 1C: >1erial Cata? and 1CL >1erial Cloc/? The reason for open drain connection is that the data transfer is bi- directional and any of the devices connected to the I ,C bus can drive the data line >1C:? The serial cloc/ line >1CL? is usually driven by the master 1ince 1C: and 1CL pins are open drain pins* e+ternal pull-up resistances are re#uired for operation of I,C bus : typical I,C bus sho$ing the connection of multi-master and multi- slave configuration is sho$n in the follo$ing figure

ig 2#$" Multimaster Multisla*e Connection 1ome conventions are follo$ed in I,C communication Let us assume that there is one master and one slave and !-data bits are sent %e $ill initially assume that the master is the transmitter and the slave is the receiver The cloc/ is driven by the master .n receiving !-bits* an ac/no$ledgement bit is driven by the receiver on 1C: line ac/no$ledgement bit is usually Lo$ >)? The follo$ing diagram sho$s The

the data communication pattern having ! data bits and one ac/no$ledgement bit

ig 2#$2 .iming diagram )or data trans)er The follo$ing features are to be noted 1C: line transmits- receives data bits M1@ is sent first Cata in 1C: line is stable during cloc/ >1CL? high : ne$ bit is initiated at the negative cloc/ transition after a specified hold time 1erial cloc/ >1CL? is driven by the master :n ac/no$ledgement bit >)? is driven by the receiver after the end of reception If the receiver does not ac/no$ledge* 1C: line remains high >1?

I,C bus transfer consists of a number of byte transfers $ithin a 1T:8T condition and either another 1T:8T condition or a 1T.P condition Curing the idle state $hen no data transfer is ta/ing place* both 1C: and 1CL lines are released by all the devices and remains high %hen a master $ants to initiate a data transfer* it pulls 1C: lo$ follo$ed by 1CL being pulled lo$ This is called 1T:8T condition 1imilarly* $hen the processor $ants to terminate the data transfer it first releases 1CL >1CL becomes high? and then 1C: This is called a 1T.P condition 1T:8T and 1T.P conditions are sho$n in the diagram as follo$s

ig 2#$% .iming diagram )or 1.AR. and 1.OP Conditions 1T:8T and 1T.P conditions are uni#ue and they never happen $ithin a data transfer Data Communication Protocol: In I,C communication both 4-bit and 1)-bit slave addressing are possible In 4bit addressing mode 1,! slaves can be interfaced $ith a single master 1imilarly* in 1)-bit addressing mode* 1),; slaves can be interfaced $ith the master %e $ill discuss here 4-bit addressing mode only 1)bit addressing mode is similar to 4-bit addressing e+cept from the fact that the number of address bits is more

5ollo$ing a "start" condition* the master sends a 4-bit address of the slave on 1C: line The M1@ is sent first :fter sending 4-bit address of the

:fter sending the 4-bit address of the slave* the master sends the address >usually ! bit? of the internal register of the slave $herefrom the data has to be read or $ritten to The subse#uent access is automatically directed to the ne+t address of the internal register The follo$ing diagrams give the general format to $rite and read from several peripheral internal registers

ig 2#$+ Data trans)er &rotocol )or writing to a sla*e de*ice 8- >8ead - %rite? bit indicates $hether the data is to be $ritten by the master or read by the master If 8- is 1* the subse#uent data are to be read by the master If 8- 6 )* the subse#uent data are to be $ritten by the master to the addressed slave It has to be noted that the slave address is sent first* follo$ing a "start" condition The addressed slave responds by ac/no$ledging and gets ready for data transfer If data has to be read from a specific address of the slave device* the master sends the 4-bit address of the slave first follo$ing a "start" condition 8- bit is sent as "lo$" The addressed slave ac/no$ledges by pulling the :CD line lo$ The master then sends the !-bit internal address of the slave from $hich data has to be read The slave ac/no$ledges 1ince 8- bit $as initially )* the master is in the $rite mode To change this to read mode* the "start" condition is again generated follo$ed by 4-bit address of the slave $ith 86 1 The slave ac/no$ledges The slave then sends data from previously specified internal address to the master The master ac/no$ledges by pulling

:CD bit lo$ The data transfer stops $hen the master does not ac/no$ledge the data reception and a "stop" condition is generated