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1. DRAM 20 points. a.

[15 points] The off-chip interconnect and memory architecture can affect

overall system performance in dramatic ways. Analyze the performance for data transfer for replacing a cache block from memory using following assumptions. 1. 1 memory bus clock cycle to send the address 2. 30 memory bus clock cycles for row access time 3. 5 memory bus clock cycles for column access time in open page 4. 1 memory bus clock cycle to return a word of data 5. The memory bus operates at 400MHz. 6. Block size is 4 words. How much time does it take to transfer eight contiguous words? Five of the words fit in one page and three others fit in another page.

b.

Explain two key differences in accessing a DRAM and SRAM, one in terms of access sequence and another due to technology. (5 points)

Name ____________________________________________________________________________ 2. Interrupts/Polling a. Explain the two differences between a trap and an interrupt. Indicate all steps involved in handling an interrupt. (10 points)

Name ____________________________________________________________________________ b. [15 points] Write MIPS assembly code using polling to read a byte from the following memorymapped device and output the byte in the output memory-mapped device.

Name ____________________________________________________________________________

Name ____________________________________________________________________________ 3. [10 points] Write a Verilog behavioral expression to calculate the branch target address in a branch instruction in the MIPS architecture. Assume a 32-bit program counter in PC, and a 32bit instruction in IR (instruction register). Place the result in a 32-bit register BT.

(10 points) Explain how the target address are calculated for the following instructions (i) (ii) (iii) (iv) j jal beq (explain both cases) jr

Name ____________________________________________________________________________ 4. Cache Memory (20 points) a. A designer reconfigures a 32Kbyte direct-mapped cache with a block size of one word for a 32bit MIPS architecture to the following configurations. Calculate the increase in number of tag bits due to the following changes. Treat each sub-part independently. All parameters not changed, remain same as base-line. (10 points) a. b. c. d. e. Direct-mapped to Fully-associative Increase block size to two words Direct-mapped to 2-way set associative Change 32-bit MIPS to 64-bit MIPS architecture Increase cache size to 64Kbyte

(10 pts) A CPU issues the following series of address references (references are word addresses): 1, 4, 8, 5, 20, 17, 19, 56, 9, 11, 4, 43, 5, 6, 9, 17. Assuming a direct-mapped cache with 16 one-word blocks that is initially empty, label each reference in the list as a hit or a miss and show the final contents of the cache.

Name ____________________________________________________________________________ 5. (10 points). Modify this MIPS pipeline to support the jump (j) instruction. It already supports Rtype instructions and lw/sw. Identify additional datapath components, and control signals.

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