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Objectives
After completing this module, you will be able to:
Identify the basic architectural resources of the Virtex-II FPGA List the differences between the Virtex-II, Virtex-II Pro, Spartan3, and Spartan-3E devices List the new and enhanced features of the new Virtex-4 device family
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 3
Overview
All Xilinx FPGAs contain the same basic resources
Slices (grouped into CLBs)
Contain combinatorial logic and register resources
IOBs
Interface between the FPGA and the outside world
Basic Architecture 4
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 5
Slice S1
Slice S0
Local Routing
CIN
CIN
Basic Architecture 6
LUT LUT
Carry Carry
LUT LUT
Carry Carry
D PRE Q CE CLR
Basic Architecture 7
Basic Architecture 8
Look-Up Tables
Combinatorial logic is stored in Look-Up Tables (LUTs)
Also called Function Generators (FGs) Capacity is limited by the number of inputs, not by the complexity
A 0 0 0 0 0 0 1 1 1 1 B 0 0 0 0 1 1 . 1 1 1 1 C 0 0 1 1 0 0 . 0 0 1 1 D 0 1 0 1 0 1 . 0 1 0 1 Z 0 0 0 1 1 1 0 0 0 1
A B C D
Basic Architecture 9
MUXF8 combines the two MUXF7 outputs (from the CLB above or below) MUXF6 combines slices S2 and S3 MUXF7 combines the two MUXF6 outputs MUXF6 combines slices S0 and S1 MUXF5 combines LUTs in each slice
Basic Architecture 10
F5
Slice S0
F6
F5
Slice S1
F5
F6
COUT
To S0 of the next CLB
COUT
To CIN of S2 of the next CLB
SLICE S3
CIN COUT
Basic Architecture 11
MULT_AND Gate
Highly efficient multiply and add implementation
Earlier FPGA architectures require two LUTs per bit to perform the multiplication and addition The MULT_AND gate enables an area reduction by performing the multiply and the add in one LUT per bit
LUT
S CO DI CI
CY_MUX
CY_XOR MULT_AND
AxB
LUT
LUT
Basic Architecture 12
Basic Architecture 13
D Q CE
D Q CE
LUT
D Q CE
Basic Architecture 14
12 Cycles
Operation A Operation B
64
44Cycles Cycles
Operation C
88Cycles Cycles
Operation D - NOP
64
33Cycles Cycles
12 Cycles
99Cycles Cycles
Basic Architecture 15
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 16
IOB Element
Input path
Two DDR registers
IOB
OCK1
Output path
Two DDR registers Two 3-state enable DDR registers
Input
Reg Reg
ICK1
OCK2
3-state
Separate clocks and clock enables for I and O Set and reset signals are shared
ICK2
Reg Reg
OCK1
PAD PAD
OCK2
Output
Basic Architecture 17
SelectIO Standard
Allows direct connections to external signals of varied voltages and thresholds
Optimizes the speed/noise tradeoff Saves having to place interface components onto your board
Basic Architecture 18
DCI advantages
Improves signal integrity by eliminating stub reflections Reduces board routing complexity and component count by eliminating external resistors Eliminates the effects of temperature, voltage, and process variations by using an internal feedback circuit
Basic Architecture 19
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 20
Basic Architecture 21
LUT LUT
A0 A1 A2 A3
RAM32X1S D WE
Slice LUT
WCLK A0 A1 A2 A3 A4
LUT
DOA DOPA
Supports initial values Synchronous reset on output latches Supports parity bits
One parity bit per eight data bits
Basic Architecture 23
DOB DOPB
4 x 4 signed
18 18xx18 18 Multiplier Multiplier
Output (36 bits)
Basic Architecture 24
Up to eight clock nets can be used in each clock region of the device
Each device contains four or more clock regions
Basic Architecture 25
Up to four outputs of each DCM can drive onto global clock buffers
All DCM outputs can drive general routing
Basic Architecture 26
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 27
More I/O pins per package Only one-half of the slices support RAM or SRL16s (SLICEM) Fewer block RAMs and multiplier blocks
Same size and functionality
Eight global clock multiplexers Two or four DCM blocks No internal 3-state buffers
3-state buffers are in the I/O
Basic Architecture 28
Slice X1Y1
Slice X0Y1
Slice X0Y0
Fast Connects
SHIFTOUT
CIN
CIN
Basic Architecture 29
Spartan-3E Features
More gates per I/O than Spartan-3 Removed some I/O standards
Higher-drive LVCMOS GTL, GTLP SSTL2_II HSTL_II_18, HSTL_I, HSTL_III LVDS_EXT, ULVDS
DDR Cascade
Internal data is presented on a single clock edge
Basic Architecture 30
Basic Architecture 31
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 32
Smart RAM
New block RAM/FIFO
Advanced CLBs
200K Logic Cells
1 Gbps SelectIO
ChipSync Source synch, XCITE Active Termination
Basic Architecture 33
FX
12K 12K140K LCs 0.6 0.610 Mb 420 32 32192 240 240896 024 Channels 1 or 2 Cores 2 or 4 Cores
SX
23K 23K55K LCs 2.3 2.35.7 Mb 48 128 128512 320 320640 N/A N/A N/A
Logic Memory DCMs DSP Slices SelectIO RocketIO PowerPC Ethernet MAC
14K 14K200K LCs 0.9 0.96 Mb 412 32 3296 240 240960 N/A N/A N/A
Basic Architecture 34
Outline
Overview Slice Resources I/O Resources Memory and Clocking Spartan-3, Spartan-3E, and Virtex-II Pro Features Virtex-4 Features Summary Appendix
Basic Architecture 35
Review Questions
List the primary slice features List the three ways a LUT can be configured
Basic Architecture 36
Answers
List the primary slice features
Look-up tables and function generators (two per slice, eight per CLB) Registers (two per slice, eight per CLB) Dedicated multiplexers (MUXF5, MUXF6, MUXF7, MUXF8) Carry logic MULT_AND gate
Basic Architecture 37
Summary
Slices contain LUTs, registers, and carry logic
LUTs are connected with dedicated multiplexers and carry logic LUTs can be configured as shift registers or memory
IOBs contain DDR registers SelectIO standards and DCI enable direct connection to multiple I/O standards while reducing component count Virtex-II memory resources include the following:
Distributed SelectRAM resources and distributed SelectROM (uses CLB LUTs) 18-kb block SelectRAM resources
Basic Architecture 38
Summary
The Virtex-II devices contain dedicated 18x18
multipliers next to each block SelectRAM resource Digital clock managers provide the following:
Delay-Locked Loop (DLL) Digital Frequency Synthesizer (DFS) Digital Phase Shifter (DPS)
Basic Architecture 39
Application Notes
www.xilinx.com Documentation Application Notes
Education resources
Designing with the Virtex-4 Family course Spartan-3E Architecture free Recorded e-Learning
Basic Architecture 40