A Project report on

F2812 DSP BASED DC BUCK-BOOST CONVERTER

Submitted in partial fulfillment of the requirement for the award of the degree of

BACHELOR OF TECHNOLOGY IN ELECTRICAL AND ELECTRONICS ENGINEERING

By

SINDHURI P (08241A0246) KRISHNA PRIYA Y (08241A0272) PRIYANKA K (08241A0284) RAJITHA V (08241A0286) TEJASWINI G (08241A02B0)
Under the guidance of

DR. C.K.SARMA Professor

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY (Affiliated to Jawaharlal Nehru Technological University, Hyderabad) 2012
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GOKARAJU RANGARAJU INSTITUTE OF ENGINEERING AND TECHNOLOGY

(Affiliated to Jawaharlal Nehru Technological University, Hyderabad)
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

CERTIFICATE
This is to certify that the project work titled F2812 DSP BASED DC BUCK - BOOST CONVERTER has been submitted by P Sindhuri (08241A0246), Y Krishnapriya (08241A0272), K Priyanka (08241A0284), V Rajitha (08241A0286), G Tejaswini (08241A02B0) in partial fulfillment of the requirements for the award of the degree of bachelor of technology in ELECTRICAL AND ELECTRONICS ENGINEERING from Jawaharlal Nehru Technological University, Hyderabad. The results embodied in this project have not been submitted to any other University or Institute for the award of any degree or diploma.

Internal Guide

Head Of The Department

External

DR. C.K. SARMA

Professor, Dept. of Electrical& Electronics Engg.

Mr. P. M. SARMA
Professor, Dept. of Electrical& Electronics Engg.

ACKNOWLEDGEMENT
This is to place on record my appreciation and deep gratitude to the persons without whose support this project would never seen the light of day. I wish to express my propound sense of gratitude to Mr. P. S. Raju, Director, G.R.I.E.T for his guidance, encouragement, and for all facilities to complete this project. I also express my sincere thanks to Mr.P.M.Sarma, Head of the Department, G.R.I.E.T and for extending their help. I have immense pleasure in expressing my thanks and deep sense of gratitude to my guide Dr.C.K.Sarma, Professor, Department of Electrical and Electronics Engineering, G.R.I.E.T for his guidance throughout this project. Finally I express my sincere gratitude to Mr.Chakravarthy, Assistant Professor, Department of Electrical and Electronics Engineering, G.R.I.E.T and Mr.Anil Kumar, Assistant Professor, Department of Electrical and Electronics Engineering, G.R.I.E.T and all the members of faculty and my friends who contributed their valuable advice and helped to complete the project successfully.

SINDHURI P (08241A0246) KRISHNA PRIYA Y (08241A0272) PRIYANKA K (08241A0284) RAJITHA V (08241A0286) TEJASWINI G (08241A02B0)

ABSTRACT
The buckboost converter is a type of DC-to-DC converter that has an output voltage magnitude that is either greater than or less than the input voltage magnitude. The output voltage is of the opposite polarity as the input. The output voltage is adjustable based on the duty cycle of the switching transistor. F2812 DSP is used to generate PWM waveform. The duty cycle and frequency of the PWM waveform is set by user in code composer studio. The PWM pulse obtained from the DSP is of +3.3V.This voltage is not sufficient to drive a MOSFET .Hence a gate driver circuit is used to amplify the output voltage from DSP. The output of gate driver circuit is connected to the gate of the MOSFET IRF740.The drain terminal is connected to +5V and the source terminal is connected to DC Buck Boost converter.

CONTENTS
S. No. TOPIC Pg.No

1.

Introduction

2. 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.5

DC Buck Boost Converter Introduction Circuit diagram Principle of operation Modes of operation Continuous conduction mode Discontinuous conduction mode Expression for output voltage

9-13 9 9 9 10 10 12 12

3. 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4

PWM signal generation from DSP Event managers General purpose timers General purpose Timer registers Individual timer Control Register (TxCON) GP Timer Control Register (GPTCONA) GP Timer Compare Register (TxCMPR) GP Timer Period Register (TxPR)

14-32 14 14 17 17 20 21 21

3.4 3.5 3.6

PWM Output And GP Timer Compare Operation Generation of PWM waveform of 50 kHz frequency Compare Units 3.6.1 3.6.2 3.6.3 3.6.4 Compare control register (COMCONA) Compare action control register (ACTRA) Dead-band timer control registers (DBTCONA) Capture Control Register (CAPCONA) Gate Driver Circuit

22 23 25 25 26 28 30 33-35 33 33 33 35

4. 4.1 4.2 4.3 4.4

Introduction Circuit Diagram Operation Waveforms

5. 5.1 5.2

Connecting The Hardware Load The Program To DSP Connecting The DSP To Gate Driver And Buck-Boost Converter 5.3 5.4 Simulation Results Practical Results Conclusion 6.1 6.2 Difficulties faced Future Scope

36-41 36

37 37 39 42 42 42

6.

APPENDIX-A APPENDIX-B APPENDIX C APPENDIX D

43-45 46-49 50 51-67

LIST OF TABLES:
Table 5.1 Simulation Results Table 5.2 Practical Results 37 39

LIST OF FIGURES:
Figure 2.1 Buck-Boost Converter Figure 2.2 Current through the Inductor Figure 2.3 Discontinuous conduction mode current waveform Figure 3.1 shows the continuous up-counting mode of the GP Timer. Figure 3.2 Continuous up/down counting mode Figure 3.3 GP timer directional up/down-counting mode Figure 3.4 Timer compare match and associated change on TxPWM pin. Figure 3.5 PWM waveform generated by a GP timer in continuous up-count mode. Figure 4.1 Gate Driver Circuit Figure 4.2 pin configuration of 74LS40 Figure 4.3 Pin Configuration of TLP250 Figure 4.4 PWM waveform from DSP for 50% dutycycle Figure 4.5 Output from Gate driver circuit. Figure 5.1 Output from DSP of magnitude 3.3V 50 kHz frequency Figure 5.2 Output from Buck Boost converter Figure 5.3 Output from DSP of magnitude 3.3V 50 kHz frequency 90 % duty cycle. Figure 5.4 Output from Buck Boost converter. 9 10 11 16 16 17 23 24 33 34 34 35 35 39 40 40 41

1. INTRODUCTION
DC conversion is of great importance in many applications, starting from low power applications to high power applications. The goal of any system is to emphasize and achieve the efficiency to meet the system needs and requirements. Several topologies have been developed in this area, but all these topologies can be considered as apart or a combination of the basic topologies which are buck, boost and flyback. This project deals with Buck Boost converter.

A buck-boost converter is a type of dc-dc converter used to step-up/step down the input voltage. This converter has two dominant characteristics: the output voltage is always negative with respect to the input voltage and the output voltage may be higher or lower than the input voltage. The circuit contains at least two semiconductor switches (a diode and a transistor) and at least one energy storage element. Filters made of capacitors are normally added to the output of the converter to reduce output voltage ripple. The output voltage is adjustable based on the duty cycle of the switching transistor. The switching waveform to adjust the duty cycle can be provided using a DSP.

APPLICATIONS:
Laboratory equipment, test instruments, desktop PC's, static telecoms Hybrid electrical vehicles. Lighting systems. Operating cold cathode fluorescent tubes in devices such as LCD backlights and flashlights

2. DC BUCK-BOOST CONVERTER
2.1 INTRODUCTION:
In a large number of industrial applications, it is required to convert a dc voltage to a different dc voltage level, often with a regulated output. To perform this task, a dc-dc converter is needed. A dc-dc converter directly converts a dc voltage of one level to another. It can be used to step-down (buck), or step-up (boost) a dc voltage source.

2.2 CIRCUIT DIAGRAM:

Figure 2.1 Buck-Boost Converter

2.3 PRINCIPLE OF OPERATION:

The buck-boost converter has the structure shown in 2.2. The principle of operation is that when the transistor T is turned on, the input voltage V is applied across the inductor L and the current i in the inductor rises. Then the transistor is turned off. The current in the inductor must continue to flow somehow, and consequently finds its path through the load resistor R, and back to the inductor L through the diode D. This discharges the inductor, and the current through it decreases. The capacitor C filters the output voltage ripple. The description given in the above is with the continuous conduction mode, meaning the inductor current never goes discontinuous. The continuous mode will be discussed further in the next section.
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This converter has two dominant characteristics: the output voltage is always negative with respect to the input voltage and the output voltage may be higher or lower than the input voltage. This is why this converter may also be referred to as a step-up/step-down converter.

2.4 MODES OF OPERATION:

2.4.1 Continuous conduction mode:
The switching results in a cyclic current increase and decrease in the inductor. This current ripple has a non-negligible influence on the operation of the converter. If during the switching period T the current never goes to zero, then the converter is said to operate in continuous conduction mode.

Figure 2.2 Current through the Inductor The input and output voltages are related by the following equation:

In this equation, d is the transistor or switch duty cycle. The below figure shows the switching pattern command to turn on or off, which must be fed to the transistor for proper operation of the buck-boost converter.

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Obviously, the duty cycle may vary only from 0 to 1. The resulting values for the converter voltage gain are:

The theoretical gain range achievable is potentially very large. Practically, it is limited by the parasitic characteristics of the converter. In addition, it is often desirable to keep the duty cycle between 0.1 (10%) and 0.9 (90%) for practical engineering considerations.

2.4.2 Discontinuous conduction mode:

If the current does go to zero at any time, then the conduction is said to be discontinuous. In discontinuous conduction mode, the voltage gain of the converter is not solely a function of the duty cycle, but also of the output current. An example of a discontinuous conduction current waveform is

Figure 2.3 Discontinuous conduction mode current waveform

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2.5 EXPRESSION FOR OUTPUT VOLTAGE: The rate of change of inductor current is a constant, indicating a linearly increasing inductor current. The equation can be expressed as,

(i) Solving for iL when the switch is closed, (ii) When the switch is open, the current in the inductor cannot change instantly, resulting in a forward-biased diode and current into the resistor and capacitor. In this condition, the voltage across the inductor is, (iii)

Again the rate of change of inductor current is constant, and the change in current is, (iv) Solving for L, (v) For steady-state operation, the net change in inductor current must be zero over one period using Equations (ii) and (v)

Solving for

O,

(vi) Equation (vi) shows the output voltage has opposite polarity form the source voltage. Output magnitude of the buck boost converter can be less than the source greater than the source, depending on the duty ratio of the switch. If D > 0.5, the output is larger than the input, and if D < 0.5, output is smaller than the input. Note that the source is never connected directly to the load in the buck boost converter. Energy is stored in the inductor when the switch is closed and transferred to the load when switch is open. Hence, the buck boost converter is also referred to as an indirect converter. Power absorbed by the load must be the same as that supplied by the source, where
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(vii) (viii) Average source current is related to average inductor current by S= LD Resulting in

(ix)

(x) Substituting for using Eq (vi) and solving for (xi) Maximum and minimum inductor current is determined using Eq (ii) and (xi) (xii) (xiii) For continuous current, the inductor current must remain positive. To determine the boundary between continuous and discontinuous current min is set to zero in Eq (xiii) or When f is switching frequency in hertz.

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3. PWM SIGNAL GENERATION WITH DSP

The PWM signal generated from the DSP was used to switch the MOSFET .The required PWM signal was generated by programming the DSP F2812 with a software- code composer studio (CCS). The program was written with the knowledge of the following registers of DSP.

3.1 EVENT MANAGERS

Event managers are one of the most important modules in DSP F2812. The two EVs (EVA/B) are identical to one another in terms of functionality and register/bit definition, but have different register names and addresses. Since both EV1 and EV2 are identical, only the functionality of EV1 will be explained. Each EV module in the F2812 contains the following sub-components: Interrupt logic Two general-purpose (GP) timers Three compare units PWM circuits that include space vector PWM circuits, dead-band generation units, and output logic Three Capture Units Quadrature encoder pulse (QEP) circuit

The different modules in the event managers are discussed in detail.

3.2 GENERAL PURPOSE TIMERS

A General Purpose (GP) timer is simply a 16-bit counter, which may be configured to count up, down or continuously up and down. There are two GP Timers in each EV: Timer1 and Timer2 for EVA and Timer3 and Timer4 for EVB. All timers use the CPU clock as a general timing reference, but each individual timer may use a pre-scaled or frequency reduced time base which is specified in each timers control register. Each GP Timer consists of the following components: One readable and writeable (RW) 16-bit up and up/down counter register TxCNT (x = 1, 2, 3, 4). This register holds the current count value and increments or decrements depending on the direction of counting 16-bit timer compare register, TxCMPR (x = 1, 2, 3, 4) 16-bit timer period register, TxPR (x = 1, 2, 3, 4) 16-bit individual timer control register, TxCON (x = 1, 2, 3, 4) Programmable input clock divider (pre-scaler) applicable to both internal and external clock inputs
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One GP Timer compare output pin, TxCMP (x = 1, 2, 3, 4) Interrupt logic

GP Timers have four possible modes of counting operation: 1. Stop/Hold mode 2. Continuous Up-Counting mode 3. Directional Up/Down-Counting mode 4. Continuous Up/Down-Counting mode Stop/Hold mode is like the pause button for the timer. In stop/hold mode the GP Timer stops and holds at its current state. The timer counter, the compare output, and the pre-scale select all remain unchanged. Continuous Up-Counting Mode: The continuous up-counting mode is useful in creating asymmetric PWM signals. In the continuous up-count mode the following events occur: 1. The GP Timer in this mode counts up in sync with the pre-scaled input clock until the value of the timer counter matches that of the period register. 2. On the next rising edge of the input clock after the match, the GP Timer resets to zero and starts counting up again. 3. The period interrupt flag of the timer is set one clock cycle after the match between the timers counter and period register. If the flag is not masked, a peripheral interrupt request is generated. An ADC start is sent to the ADC module at the same time the flag is set if the period interrupt of this timer has been selected by the appropriate bits in GPTCONA/B to start the ADC. 4. One clock cycle after the GP Timer becomes 00001, the underflow interrupt flag of the timer is set. A peripheral interrupt request is generated by the flag if it is unmasked. An ADC start is sent to the ADC module at the same time if the underflow interrupt flag of this timer has been selected by the appropriate bits in the GPTCONA/B to start the ADC.

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Figure 3.1 shows the continuous up-counting mode of the GP Timer. Continuous Up/Down-Counting Mode The continuous up/down-counting mode is useful in generating symmetric PWM waveforms. This mode of operation is the same as the directional up-/down counting mode, except for the fact that the TDIRA/B pin has no effect on the counting direction. The counting direction changes from up to down when the timer reaches the period value. The timer direction changes from down to up when the timer reaches zero. Continuous up/down-counting mode is particularly useful in generating centered or symmetric PWM waveforms. The counting direction indication bit in the GPTCONA/B indicates 1 when the timer counts upward and 0 when the timer is counting downward. Either an external clock reference from the TCLKINA/B pin or the internal CPU clock can be selected as the input clock. Since the change of count direction is automatic in this mode, the TDIRA/B pin has no effect. Figure 3.2 shows the continuous up-/down-counting mode of the GP Timer.

Figure 3.2 Continuous up/down counting mode (timer period register = 3 or 2).
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Note: The period of the timer in this mode is 2*(TxPR) cycles of the scaled clock input, except for the first period. Directional Up/Down-Counting Mode: A GP Timer in directional up/down-counting mode counts either up or down according to the pre-scaled clock and TDIRA/B inputs. The input pin TDIRA/B determines the direction of counting when the GP Timer is in directional up/down counting mode. When TDIRA/B is high, upward counting is specified; when TDIRA/B is low, downward counting is specified. When the TDIRA/B pin is held high, the GP Timer will count up until it reaches the value of the period register. When the timer value equals that of its period register the timer will reset to zero and start counting up to the period again. In the directional up/down mode, the period, underflow, and overflow interrupt flags, interrupts, and associated actions are generated on respective events in the same manner as they are generated in the continuous up-counting mode. The direction of counting is indicated for the timer in this mode by the corresponding direction indication bit in GPTCONA/B: 1 means counting up; 0 means counting down. Either the external clock from the TCLKINA/B pin or the internal device clock can be used as the input clock for the timer in this mode. Figure 3.3 shows the directional up-/down-counting mode of the GP Timers.

Figure 3.3 GP timer directional up/down-counting mode: prescale factor 1 and TxPR = 3A.

3.3 GENERAL PURPOSE TIMER REGISTERS

3.3.1Individual Timer Control Registers (TxCON) Individual Timer Control Registers (TxCON), where x=1,2,3,4 .The operational mode of each GP Timer is controlled by the timers corresponding control register (TxCON).

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Timer x Control Register Bit Descriptions (TxCON; x = 1, 2, 3, or 4) Addresses: 7404h (T1CON), 7408h (T2CON), 7504h (T3CON), and 7508h (T4CON) 15 14 13 Free Soft Reserved RW-0 RW-0 RW-0 7 6 5 T2SWT1/ TENABLE TCLKS1 T4SWT31 RW-0 RW-0 RW-0 Reserved in T1CON andT3CON 12 11 TMODE1 TMODE0 RW-0 RW-0 4 3 TCLKS0 RW-0 TCLD1 RW-0 10 TPS2 RW-0 2 TCLD0 RW-0 8 TPS0 RW-0 0 SELT1PR/ TECMPR SELT3PR1 RW-0 RW-0 9 TPS1 RW-0 1

Note: R = read access, W = write access, -0 = value after reset. Bits 1514 Free, Soft. Emulation control bits. 00 01 10 11 Stop immediately on emulation suspend Stop after current timer period is complete on emulation suspend Operation is not affected by emulation suspend Operation is not affected by emulation suspend

Bit 13 Reserved. Reads return zero, writes have no effect. Bits 1211 TMODE1TMODE0. Count Mode Selection. 00 01 10 11 Stop/Hold Continuous-Up/-Down Count Mode Continuous-Up Count Mode Directional-Up/-Down Count Mode

Bits 108 TPS2TPS0. Input Clock Prescaler. 000=x/1 , 001=x/2, 010=x/4, 011=x/8, 100=x/16, 101=x/32,110=x/64 111=x/128 ; x = device (CPU) clock frequency Bit 7 T2SWT1. In the case of EVA, this bit is T2SWT1. (GP Timer 2 start with GP Timer 1.) Start GP Timer 2 with GP Timer 1s timer enable bit. This bit is reserved in T1CON. T4SWT3. In the case of EVB, this bit is T4SWT3. (GP Timer 4 start with GP Timer 3.) Start GP Timer 4 with GP Timer 3s timer enable bit. This bit is reserved in T3CON. 0 Use own TENABLE bit

1 Use TENABLE bit of T1CON (in case of EVA) or T3CON (incase of EVB) to enable and disable operation ignoring own TENABLE bit
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Bit 6 TENABLE.Timer enable. 0 1 Disable timer operation(the timer is put in hold and the prescaler counter is reset) Enable timer operations

Bits 54 TCLKS1, TCLKS0. Clock Source Select. 54 00 01 10 11 Source Internal External Reserved QEP Circuit (in case of Timer 2/Timer 4) Reserved (in case of Timer 1/Timer 3) This option is valid only if SELT1PR = 0 Bits 32 TCLD1, TCLD0. Timer Compare Register Reload Condition. 00 01 10 11 When counter is 0 When counter value is 0 or equals period register value Immediately Reserved

Bit 1 TECMPR. Timer compare enable. 0 1 Disable timer compare operation Enable timer compare operation

Bit 0 SELT1PR. In the case of EVA, this bit is SELT1PR (Period register select). When set to 1 in T2CON, the period register of Timer 1 is chosen for Timer 2 also, ignoring the period register of Timer 2. This bit is a reserved bit in T1CON. SELT3PR. In the case of EVB, this bit is SELT3PR (Period register select). When set to 1 in T4CON, the period register of Timer 3 is chosen for Timer 4 also, ignoring the period register of Timer 4. This bit is a reserved bit in T3CON 0 Use own period register

1 Use T1PR (in case of EVA) or T3PR (in case of EVB) as period register ignoring own period register

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3.3.2 GP Timer Control Register (GPTCONA)

GP Timer Control Register A (GPTCONA) Bit Descriptions Address 7400h 15 14 Reserved T2STAT RW-0 R-1 6 TCOMPOE RW-0 13 T1STAT R-1 5-4 Reserved RW-0 12-11 Reserved RW-0 3-2 T2PIN RW-0 10-9 T2TOADC RW-0 8-7 T1TOADC RW-0 1-0 T1PIN RW-0

Note: R = read access, W = write access, -n = value after reset.

Bit 15 Reserved. Reads return zero; writes have no effect. Bit 14 T2STAT. GP Timer 2 Status. Read only. 0 1 Counting downward Counting upward

Bit 13 T1STAT. GP Timer 1 Status. Read only. 0 1 Counting downward Counting upward

Bits 1211 Reserved. Reads return zero; writes have no effect. Bits 109 T2TOADC. Start ADC with timer 2 event. 00 01 10 11 No event starts ADC Setting of underflow interrupt flag starts ADC Setting of period interrupt flag starts ADC Setting of compare interrupt flag starts ADC

Bits 87 T1TOADC. Start ADC with timer 1 event. 00 01 10 11 No event starts ADC Setting of underflow interrupt flag starts ADC Setting of period interrupt flag starts ADC Setting of compare interrupt flag starts ADC

Bit 6 TCOMPOE. Compare output enable. If PDPINTx is active this bit is set to zero. 0 Disable all GP Timer compare outputs (all compare outputs are put in the highimpedance state)
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Enable all GP Timer compare outputs

Bits 54 Reserved. Reads return zero; writes have no effect. Bits 32 T2PIN. Polarity of GP Timer 2 compare output. 00 01 10 11 Forced low Active low Active high Forced high

Bits 10 T1PIN. Polarity of GP Timer 1 compare output. 00 01 10 11 Forced low Active low Active high Forced high

3.3.3 GP Timer Compare Register (TXCMPR)

GP Timer Compare Registers (TxCMPR), x=1,2,3,4 User Specified Value Addresses 7402h (T1CMPR), 7406h (T2CMPR), 7502h (T3CMPR), 7506h (T4CMPR) The compare register associated with each GP Timer stores the value that will be constantly compared with the current value of the GP Timer. When a compare match occurs, the following events also occur: 1. A transition occurs on the associated compare output according to the bit pattern in GPTCONA/B 2. The corresponding interrupt flag is set 3. A peripheral interrupt request is generated if the interrupt is unmasked 4. The compare operation of a GP Timer can be enabled or disabled by the appropriate bit in TxCON 5. The compare operation and outputs can be enabled in any of the timer counting modes, including the QEP circuit

3.3.4 GP Timer Period Registers (TxPR)

GP Timer Period Registers (TxPR) User Specified Value Addresses 7403h (T1PR), 7407h (T2PR), 7503h (T3PR), 7507h (T4PR)

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The period register determines the rate at which the timer resets itself or changes direction (the period of the timer). This register in combination with the input clock frequency (and clock prescale factor) determines the frequency of a PWM signal created by the compare output pin. The corresponding timer either resets to 0, or starts counting downward (depending on the operating mode) when a match occurs between the period register and the timer counter (TxCNT).

3.4 PWM OUTPUT AND COMPARE OPERATION

GENERAL

PURPOSE

TIMER

A PWM waveform is a sequence of pulses with fixed frequency but varying pulse widths. The width of the pulse might vary from 0% to 100% of the fixed period. The pulse widths are modulated by another signal called the modulation signal. In order to generate a PWM signal digitally, a timer is set to continuously repeat a counting period. This period is known as the PWM carrier period. The inverse of the carrier period is called the carrier frequency. The counting pattern of the timer will either be a saw-tooth (asymmetric) or triangle (symmetric) wave depending on what counting mode the timer has been configured for. As always, the compare value is constantly being compared with the value of the timer counter. When a match occurs, the output toggles High to Low, or Low to High. When the timer period value is reached or a second match occurs, the output toggles again. The on and off time of the pulse is directly dependent on the value loaded into the timers compare r egister. By varying the number in the compare register by the modulation signal (usually a sinusoid), a PWM signal that represents the modulating signal can be produced. The output discussed above refers to each GP Timers associated PWM output pin ( TxPWM). The logic level of the PWM output pin is determined automatically by hardware. This level is based on the value of the associated compare register and timer count value (see Fig. 3.4, note the compare match points and the output change at these points). If the compare operation is enabled in TxCON, the following events occur on a compare match: 1. The compare interrupt flag of the timer is set one clock cycle after the match. 2. A transition occurs on the associated PWM output pin one device clock cycle after the match according to the bit configuration in GPTCONA/B. 3. If the compare interrupt flag has been selected by the appropriate GPTCONA/B bits to start the ADC, an ADC start signal is generated at the same time the compare interrupt flag is set. 4. A peripheral interrupt request is generated by the compare interrupt flag if it is unmasked.

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Figure 3.4 Timer compare match and associated change on TxPWM pin. The polarity of the compare output (see diagram in Fig. 6.6) of a GP Timer can be specified active high, active low, forced high, or forced low. This polarity is determined by setting the bits in the GPTCONA/B register. By default (after a reset or power-on) all GP Timer PWM output pins are put in a high-impedance (HI-Z) state. The PWM output must be made active by configuring the GPTCONA/B registers. At anytime the PWM outputs will be made HI-Z whenever the power drive protection pin PDPINTx is active and is pulled low. Additionally, the corresponding PWM pin will be made HI-Z when bit 1 of the TxCON register is zeroed by software. The transition on the PWM output pin is controlled by the asymmetric or symmetric timer waveform and the associated output logic. For an asymmetric wave form, the timer is set up in continuous up-count mode. To generate a symmetric waveform, the timer needs to be configured to continuous up/down counting.

3.5 GENERATION OF PWM WAVEFORM OF 50 kHz FREQUENCY

The PWM waveform in Fig. 3.5 is generated when the GP Timer is in continuous up-counting mode. To generate this waveform the following registers are to be used: TxPR value specifies the maximum value/peak value of the asymmetric waveform, the timer starts counting to this value. This also determines the frequency of the PWM waveform. For a 50 kHz frequency TxPR value must be set to 0x05DC. The value in the TxCMPR register specifies the constant compare value that will be compared while timer counts. This also determines the duty cycle of the PWM
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waveform. For a duty cycle of 50% the value in the TxCMPR register must be 0x02EE(50% of 0x05DC) The count register can be set to any value between 0000h and the value in TxPR register, accordingly the output will change. Hence TxCNT register must be set to 0000h. The timer and timer compare operation must be enabled and the counting mode for asymmetric waveform (continuous-up counting)must be set in TxCON register. Hence TxCON must be set to 0x1042. To enable the PWM pins and the actions that take place on a compare match the registers ACTRA and COMCONA must be set to 0x6666 and 0xA600. The registers when set to the above mentioned values the following events occur: the timer that is enabled starts and the value in the TxCNT register increments starting from 0000h,and when a compare match occurs depending on the action mentioned in ACTRA register the PWM pin is either set to high or low. the TxCNT register is reset to 0000h upon reaching the TxPR value and the PWM pin status gets changed. the status of the PWM pin changes again when a second compare match happens.

Figure 3.5 PWM waveform generated by a GP timer in continuous up-count mode. If the compare value is zero at the very beginning of the period, then a compare match is made at the very beginning and, consequently, the output is the active level for the period. If the output is active for the whole period and the new compare value for the next period is zero, then the output will stay at the active level so as not to cause a glitch. If the value in the compare register is greater than the value in the period register, then a compare match will never be made and consequently the output will be at the inactive level through the whole period.
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The above allows the duty cycle of the PWM to range from 0 to 100% without glitches being present. If the compare value is the same as the period value, which causes a compare match, then the output pin will be at the active level for exactly one pre-scaled clock cycle.

3.6 COMPARE UNITS

A PWM signal can also be generated using the compare unit (CMPRx). The compare units (CMPRx) in the LF2407 function identically to the GP Timer compare units (TxCMPR) discussed above. Unlike the GP Timer compare function, each compare unit has two associated PWM outputs which both toggle on the same compare match. The PWM outputs associated with the compare units allow for the generation of six PWM outputs per EV. The Compare units include: Three 16-bit compare registers (CMPR1, CMPR2, and CMPR3 for EVA; and CMPR4, CMPR5, and CMPR6 for EVB), all double-buffered One 16-bit compare control register (COMCONA for EVA, and COMCONB for EVB) One 16-bit action control register (ACTRA for EVA, and ACTRB for EVB), with an associated buffer register Six PWM (3-state; Low, High, High Z) output (compare output) pins (PWMy, y = 1, 2, 3, 4, 5, 6 for EVA and PWMz, z = 7, 8, 9, 10, 11, 12 for EVB)

3.6.1 Compare Control Registers (COMCONA)

These registers (COMCONA and COMCONB) control the operation of the compare units. They determine whether the compare operation is enabled, whether the compare outputs are enabled, the condition on which the compare registers are updated with the values in their buffer registers, and whether the Space Vector PWM (SVPWM) mode is enabled. Compare Control Register A (COMCONA) Address 7411h 8 PDPINTA/ CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE STATUS RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7-0 RESERVED R-0 15 14 13 12 11 10 9

Bit 15 CENABLE. Compare enable. 0 Disables compare operation. All shadowed registers (CMPRx, ACTRA) become transparent 1 Enables compare operation
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Bits 1413 CLD1, CLD0. Compare register CMPRx reload condition. 00 01 10 11 When T1CNT = 0 (that is, on underflow) When T1CNT = 0 or T1CNT = T1PR (that is, on underflow or period match) Immediately Reserved; result is unpredictable

Bit 12 SVENABLE. Space vector PWM mode enable. 0 1 Disables space vector PWM mode Enables space vector PWM mode

Bits 1110 ACTRLD1, ACTRLD0. Action control register reload condition. 00 01 10 11 When T1CNT = 0 (on underflow) When T1CNT = 0 or T1CNT = T1PR (on underflow or period match) Immediately Reserved

Bit 9 FCOMPOE. Compare output enable. Active PDPINTA clears this bit to zero. 0 1 PWM output pins are in high-impedance state; that is, they are disabled PWM output pins are not in high-impedance state; that is, they are enabled

Bit 8 PDPINTA STATUS. This bit reflects the current status of the PDPINTA pin. (This bit is applicable to 240xA devices only it is reserved on 240x devices and returns a zero when read.) Bits 70 Reserved. Read returns zero; writes have no effect.

3.6.2 Compare Action Control Register (ACTRA)

The double buffered, compare action control registers (ACTRA) determine what action occurs on each of the six compare output pins when a compare event occurs (if the compare operation is enabled by COMCONx[15]). The compare output pins are PWMx, where x = 1 6 for ACTRA, and x = 712 for ACTRB. The condition on which ACTRA and ACTRB are reloaded is defined by the bits in COMCONx.

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Compare Action Control Register A (ACTRA) Address 7413h 15 14 13 12 11 10 SVRDIR D2 D1 D0 CMP6 ACT0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1 CMP4 CMP4 CMP3 CMP3 CMP2 CMP2 CMP1 ACT1 ACT0 ACT1 ACT0 ACT1 ACT0 ACT1 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Note: R = read access, W = write access, -0 = value after reset. 9 CMP5 RW-0 0 CMP1ACT0 RW-0 8 ACT0 RW-0

Bit 15 SVRDIR. Space vector PWM rotation direction. Used only in space vector PWM output generation. 0 1 Positive (CCW) Negative (CW)

Bits 1412 D2D0. Basic space vector bits. Used only in space vector PWM output generation. Bits 1110 CMP6ACT10. Action on compare output pin 6, CMP6. 00 01 10 11 Forced low Active low Active high Forced high

Bits 98 CMP5ACT10. Action on compare output pin 5, CMP5. 00 01 10 11 Forced low Active low Active high Forced high

Bits 76 CMP4ACT10. Action on compare output pin 4, CMP4. 00 01 10 Forced low Active low Active high

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11

Forced high

Bits 54 CMP3ACT10. Action on compare output pin 3, CMP3. 00 01 10 Forced low Active low Active high

Bits 32 CMP2ACT10. Action on compare output pin 2, CMP2. 00 01 10 11 Forced low Active low Active high Forced high

Bits 10 CMP1ACT10. Action on compare output pin 1, CMP1. 00 01 10 11 Forced low Active low Active high Forced high

3.6.3 Dead-Band Timer Control Register A (DBTCONA)

The dead-band generators generate the dead-band delay between the toggling of the independent and dependent PWM outputs. Each programmable dead-band unit features: One 16-bit dead-band control register, DBTCONx (RW) One input clock prescaler: x/1, x/2, x/4, etc., to x/32 Device (CPU) clock input Three 4-bit down-counting timers Control logic

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Dead-Band Timer Control Register A (DBTCONA) Address 7415h 15-12 11 10 9 8 Reserved DBT3 DBT2 DBT1 DBT0 R-0 RW-0 RW-0 RW-0 RW-0 7 6 5 4 3 2 1-0 EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 Reserved RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 R-0 Note: R = read access, W = write access, -0 = value after reset. Bits 1512 Reserved. Reads return zero; writes have no effect. Bits 118 DBT3 (MSB)DBT0 (LSB). Dead-band timer period. These bits define the period value of the three 4-bit dead-band timers. Bit 7 EDBT3. Dead-band timer 3 enable (for pins PWM5 and PWM6 of Compare Unit 3). 0 1 Disable Enable

Bit 6 EDBT2. Dead-band timer 2 enable (for pins PWM3 and PWM4 of Compare Unit 2). 0 1 Disable Enable

Bit 5 EDBT1. Dead-band timer 1 enable (for pins PWM1 and PWM2 of Compare Unit 1). 0 1 Disable Enable

Bits 42 DBTPS2 to DBTPS0. Dead-band timer prescaler. 000 001 010 011 100 101 x/1 x/2 x/4 x/8 x/16 x/32
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110 111

x/32 x/32

x = Device (CPU) clock frequency Bits 10 Reserved. Reads return zero; writes have no effect.

3.6.4 Capture Control Register A (CAPCONA)

Upon a RESET, all capture registers are cleared to zero. There are four 16-bit registers that control the functionality of the Capture Units. These registers are CAPCONA, CAPCONB, CAPFIFOA, and CAPFIFOB. In addition to these four registers the individual timer control registers (TxCON, x = 1, 2, 3, or 4) control the selected timer which acts as the time base for the Capture Unit. CAPCONA and CAPCONB also control the QEP functionality. Capture Control Register A (CAPCONA) Address 7420h 10 9 8 CAP3TS CAP3TO CAPRES CAPQEPN CAP3EN Reserved CAP12TSEL EL ADC RW0 RW0 RW0 R0 RW0 RW0 RW--0 7-6 5-4 3-2 1-0 CAP1EDGE CAP2EDGE CAP3EDGE Reserved RW0 RW0 RW0 R-0 Note: R = read access, W = write access, -0 = value after reset. Bit 15 CAPRES. Capture reset. Always reads zero. Note: This bit is not implemented as a register bit. Writing a 0 simply clears the capture registers. 0 1 Clear all registers of Capture Units and QEP circuit to 0 No action 15 14-13 12 11

Bits 1413 CAPQEPN. Capture Units 1 and 2 control. 00 01 10 11 Disables Capture Units 1 and 2; FIFO stacks retain their contents Enables Capture Units 1 and 2 Reserved Reserved

Bit 12 CAP3EN. Capture Unit 3 control.

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0 1

Disables Capture Unit 3; FIFO stack of Capture Unit 3 retains its contents Enable Capture Unit 3

Bit 11 Reserved. Reads return zero; writes have no effect. Bit 10 CAP3TSEL. GP Timer selection for Capture Unit 3. 0 1 Selects GP Timer 2 Selects GP Timer 1

Bit 9 CAP12TSEL. GP Timer selection for Capture Units 1 and 2. 0 1 Selects GP Timer 2 Selects GP Timer 1

Bit 8 CAP3TOADC. Capture Unit 3 event starts ADC. 0 1 No action Starts ADC when the CAP3INT flag is set

Bits 76 CAP1EDGE. Edge detection control for Capture Unit 1. 00 01 10 11 No detection Detects rising edge Detects falling edge Detects both edges

Bits 54 CAP2EDGE. Edge detection control for Capture Unit 2. 00 01 10 11 No detection Detects rising edge Detects falling edge Detects both edges

Bits 32 CAP3EDGE. Edge detection control for Capture Unit 3. 00 01 No detection Detects rising edge
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10 11

Detects falling edge Detects both edges

Bits 10 Reserved. Reads return zero; writes have no effect.

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4. GATE DRIVER CIRCUIT

4.1 INTRODUCTION
A Gate Driver circuit is an integrated drive which uses opto-isolator TLP250 and amplifier,NAND buffer 74LS40 with two power supplies at 15V and 5V.In addition to this ,two resistors are used to complete the circuit. The output pulse of magnitude 3.3V of 50 kHz from the DSP was amplified to a voltage of 12V magnitude to drive MOSFET IRF740.

4.2 CIRCUIT DIAGRAM

Fig 4.1 Gate Driver Circuit

4.3 OPERATION
The gate driver circuit consists of a dual 4-input NAND buffer 74LS40 and TLP250 which acts as an opto-isolator and amplifier. The output from DSP is given to the 74LS40 as input. It has 14 pins and its pin configuration is as shown in fig 4.2

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Fig 4.2 pin configuration of 74LS40 The output from 74LS40 is given as a input to TLP250.TLP250 acts as opto isolator. It has 8 pins as shown in the fig 4.3. The output from TLP250 used to the MOSFET of buck boost converter.

Fig 4.3 Pin Configuration of TLP250

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4.4 WAVEFORMS
The output from DSP is 3.3V.The output from DSP for 50% dutycycle and 50KHZ frequency is as shown in the fig 4.4

Fig 4.4 PWM waveform from DSP for 50% dutycycle The output from DSP is given to gate driver circuit. The output from gate driver circuit for 50% dutycycle and 50kHz frequency is of magnitude 12V as shown in the fig 4.5

Fig 4.5 Output from Gate driver circuit

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5. CONNECTING THE HARDWARE

5.1 LOAD THE PROGRAM INTO DSP
The program to generate 50 kHz frequency pulse waveform of a specified duty cycle was loaded into the DSP and run using Code Composer Studio software.

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5.2 CONNECTING GATE DRIVER CIRCUIT AND BUCKBOOST CONVERTER TO DSP

The output at the PWM pins in the DSP are connected to the gate driver circuit at input pins of 74LS40 and the amplified output from TLP250 is connected across the gate and source terminals of the MOSFET.

5.3 SIMULATION RESULTS:

Table 5.1 Simulation Results Vin =5V. S.No. 1. 2. 3. 4. 5. Duty Cycle(%d) 10 40 50 75 90 Output Voltage(Vo) 0.7 4.8 5.4 17.6 47

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5V-40% DUTY CYCLE:

5V-90% DUTY CYCLE:

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5.4 PRACTICAL RESULTS:

The practical results were obtained by programming the DSP to generate a 50 kHz frequency pulse waveform by setting its timer registers to the required values : Timer period register TxPR = 0X05DC (for a frequency of 50 kHz)

Timer compare register TxCMPR = 0x0096 (for a duty cycle of 10 %) Timer count register TxCNT = 0x0000 (the counting starts from 0000h)

To obtain different duty cycles for a fixed frequency of 50 kHz the value in the TxCMPR register was modified.

Table 5.2 Practical results Vin = 5V. S.No. 1. 2. 3. 4. 5. Duty Cycle(% d) 10 25 50 75 90 TxCMPR 0x0096 0x0177 0x02EE 0x0456 0x0546 Output voltage Vo 4.8 10 12.5 17.4 40

5V-10 % DUTY CYCLE: For 10 % duty cycle the registers are set as: TxPR =0x05DC TxCMPR =0x0096 TxCNT = 0x0000

Figure 5.1 Output from DSP of magnitude 3.3V 50 kHz 10 % duty cycle
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Figure 5.2 Output from Buck Boost converter

5V-90 % DUTY CYCLE: For 90% duty cycle the registers were set as: TxPR = 0x05DC

TxCMPR = 0x0546 TxCNT = 0x0000

Figure 5.3 Output from DSP of magnitude 3.3V 50 kHz frequency 90 % duty cycle.

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Figure 5.4 Output from Buck Boost converter.

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6. CONCLUSION
The operation of Buck Boost converter for different values of duty cycle was observed. Different values of duty cycle were set by programming the DSP for a fixed frequency with a variable duty cycle. In doing so Event managers and Timer modules of DSP were studied in detail. In simulation the output values of voltage from buck boost converter were similar to the theoretically calculated values.

6.1 DIFFICULTIES ENCOUNTERED WHILE DOING THE PROJECT

There was a problem with MATLAB as there was an error when we connected the DSP with MATLAB, so the project was done using code composer studio. There was also a problem with DSP as it sometimes showed an error while getting connected. Since Code Composer Studio 3.3 was a new software to us, it took time to understand the process of building the program to DSP. The output from the DSP was not 3.3V always hence there was a difficulty in getting the expected output.

6.2 FUTURE SCOPE

The control of the converter can be done in a closed loop manner by taking a feedback from the buck boost converter and giving to the ADC pins of DSP. The DSP upon receiving information of the instantaneous current and voltage from the load via the analog to digital converter inputs can be programmed to maintain the output voltage constant. In USB applications, a constant 5 V is often required. But according to the USB standard, the input voltage can vary from 4.5 to 5.25 V. So converters must be used to stabilize the voltage. A buck-boost converter is needed which permits stable operation when the input voltage is either higher or lower than the desired output voltage. The output from the buck boost converter can be used to achieve closed loop control of a DC motor.

REFERENCES: [1] Rev.F, Technical Reference eZdsp F2812, Spectrum Digital, 2003. [2] Toliyat- DSP-Based Electromechanical Motion Control [3] M.H.Rashid- Circuits, Devices and Applications [4] Website: www.spectrumdigital.com [5] Website: www.alldatasheets.com
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APPENDIX A
PROGRAM
// TI File $Revision: /main/3 $+ // Checkin $Date: July 2, 2007 11:32:39 $ //########################################################################### // // FILE: Example_281xEvPwm.c // // TITLE: DSP281x Event Manager PWM Generation. // // ASSUMPTIONS: // // This program requires the DSP281x V1.00 header files. // As supplied, this project is configured for "boot to H0" operation. // // Other then boot mode pin configuration, no other hardware configuration // is required. // // DESCRIPTION: // // This program sets up the EV timer (TIMER1) // to generate T1PWM and PWM1-6waveforms. // The user can then observe the waveforms using an scope. // // //########################################################################### // $TI Release: DSP281x C/C++ Header Files V1.20 $ // $Release Date: July 27, 2009 $ //########################################################################### #include "DSP281x_Device.h" // DSP281x Headerfile Include File #include "DSP281x_Examples.h" // DSP281x Examples Include File

// Prototype statements for functions found within this file. void init_eva(void);

// Global counts used in this example

void main(void)
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{ // Step 1. Initialize System Control: // PLL, WatchDog, enable Peripheral Clocks // This example function is found in the DSP281x_SysCtrl.c file. InitSysCtrl(); // Step 2. Initalize GPIO: // This example function is found in the DSP281x_Gpio.c file and // illustrates how to set the GPIO to it's default state. // InitGpio(); // Skipped for this program. // Initialize only GPAMUX and GPBMUX for this test EALLOW; // Enable PWM pins GpioMuxRegs.GPAMUX.all = 0x00FF; // EVA PWM 1-6 pins EDIS; // Step 3. Clear all interrupts and initialize PIE vector table: // Disable CPU interrupts DINT; // Initialize PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the DSP281x_PieCtrl.c file. InitPieCtrl(); // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000; // Initialize the PIE vector table with pointers to the shell Interrupt // Service Routines (ISR). // This will populate the entire table, even if the interrupt // is not used in this program. This is useful for debug purposes. // The shell ISR routines are found in DSP281x_DefaultIsr.c. // This function is found in DSP281x_PieVect.c. InitPieVectTable(); // Step 4. Initialize all the Device Peripherals: // This function is found in DSP281x_InitPeripherals.c // InitPeripherals(); // Not required for this example init_eva();

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// Step 5. User specific code, enable interrupts: // Just sit and loop forever: // PWM pins can be observed with a scope. for(;;); } void init_eva() { // EVA Configure T1PWM // Initalize the timer // Initalize EVA Timer1 EvaRegs.T1PR = 0x05DC; // Timer1 period for 50 kHz frequency EvaRegs.T1CMPR = 0x0546; // Timer1 compare for 90% duty cycle EvaRegs.T1CNT = 0x0000; // Timer1 counter // TMODE = continuous up/down // Timer enable // Timer compare enable EvaRegs.T1CON.all = 0x1042; // Setup T1PWM // Drive T1 PWM by compare logic EvaRegs.GPTCONA.bit.TCMPOE = 1; // Polarity of GP Timer 1 Compare = Active low EvaRegs.GPTCONA.bit.T1PIN = 1;

// Enable compare for PWM1-PWM6 EvaRegs.CMPR1 = 0x546;

// Compare action control. Action that takes place // on a cmpare event // output pin 1 CMPR1 - active high // output pin 2 CMPR1 - active low // output pin 3 CMPR2 - active high // output pin 4 CMPR2 - active low // output pin 5 CMPR3 - active high // output pin 6 CMPR3 - active low EvaRegs.ACTRA.all = 0x0666; EvaRegs.DBTCONA.all = 0x0000; // Disable deadband EvaRegs.COMCONA.all = 0xA600; } // No ISR's used in this program

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APPENDIX-B CODE COMPOSER STUDIO (CCS)

Code Composer Studio is an integrated development environment for developing applications for Texas Instruments embedded processors. Texas Instruments embedded processors include DSPs, ARM based devices and other processors such as MSP430. Code Composer Studio includes a real time operating system called DSP/BIOS or SYS/BIOS. Code Composer Studio or CCS includes support for OS level application debug as well as low-level JTAG based development. CCS is based on the Eclipse open source software framework. CCStudios easy to use IDE allows DSP designers of all experience levels to move quickly through each phase of the application development process including design, code and build, debug, analyze and tune. The familiar tools and interfaces allow users to get started faster and become productive immediately. The IDE includes DSP/BIOS support, real-time analysis capabilities, debugger and optimization tools, C/C++ Compiler, Assembler, Linker, integrated CodeWright editor, visual project manager and a variety of simulators and emulation drivers. The CCStudio IDE provides easy to use tooling that spans the entire development process. The feature set is both rich and deep so That developer can take advantage of time saving, stress relieving productivity tools that get their applications to market quicker and take advantage of sophisticated debug tooling allowing them to find and fix real time issues. The tuning and optimization features enable developers to produce highly efficient applications taking full advantage of the device capabilities expected extension of a source
file is .ASM for assembly and .C for C programs. The concept of COFF tools is to allow modular development of software independent of hardware concerns. An individual assembly language file is written to perform a single task and may be linked with several other tasks to achieve a more complex total system. Writing code in modular form permits code to be developed by several people working in parallel so the development cycle is shortened. Debugging and upgrading code is faster, since components of the system, rather than the entire system, is being operated upon. Also, new systems may be developed more rapidly if previously developed modules can be used in them. Code developed independently of hardware concerns increases the benefits of modularity by allowing the programmer to focus on the code and not waste time managing memory and moving code as other code components grow or shrink. A linker is invoked to allocate systems hardware to the modules desired to build a system. Changes in any or all modules, when re-linked, create a new hardware allocation, avoiding the possibility of memory resource conflicts.

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OPEN A PROJECT :

BUILD A PROGRAM :

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CONNECTING TO DSP:

LOADING A PROGRAM:

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RUN A PROGRAM:

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APPENDIX-C EAGLE
EAGLE is an EDA program by CadSoft for creating printed circuit boards. The name is an acronym formed from Easy Applicable Graphical Layout Editor. CadSoft Eagle and the company in September 2009, Premier Farnellsells, a supplier of electronic components. The software consists of several components: Layout Editor, Schematic Editor, Auto router and an extensible component database. It is available for the platforms Microsoft Windows, Linux and Mac OSX. It exists for non-commercial use; a free version on a schematic sheet, half Euro card mm 80 mm and two signal layers is limited to 100. The schematic editor can be used by a special component library for programming a Microsps.

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APPENDIX-D DATASHEETS:

Extremely high dv/dt capability 100% avalanche tested Very low intrinsic capacitances Gate charge minimized

DESCRIPTION
This power MOSFET is designed using the companys consolidated striplayout -based MESHOVERLAYTMprocess. This technology matches TO-220and improves the performances compared with Standard parts from various sources.

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APPLICATIONS
High current switching uninterruptible power supply(UPS) Internal schematic diagram DC /D C converters for telecom, industrial and lightining equipment

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Transistor invereter Inverter for air conditionor IGBT gate driver Power MOSFET gate drive The TOSHIBA TLP250 consists of a GaAlAs light emitting diode and a integrated photodetector This unit is 8-lead DIP package. TLP250 is suitable for gate driving circuit of IGBT or power MOS FET.

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Input threshold current: I=5mA(max.) Supply current (ICC): 11mA(max.) Supply voltage (VCC): 10-35V Output current (IO): 1.5A (max.) Switching time (t pLH/tpHL): 1.5s(max.) Isolation voltage: 2500Vrms(min.) UL recognized: UL1577, file No.E67349 Option (D4) type VDE approved: DIN VDE0884/06.92,certificate No.76823 Maximum operating insulation voltage: 630VPK Highest permissible over voltage: 4000VPK (Note) When a VDE0884 approved type is needed, please designate the "option (D4)" Creepage distance: 6.4mm(min.) Clearance: 6.4mm(min.)

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