HAMCOP MICROPROCESSOR COMPANION CHIP WATCH-DOG TIMER

9 WATCH-DOG TIMER

OVERVIEW

The HAMCOP watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions
such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service. The
watchdog timer generates the reset signal for 128 GCLK cycles.

FEATURES

— Normal interval timer mode with interrupt request

— Internal reset signal is activated for 128 GCLK cycles when the timer count value reaches 0(time-out).

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WATCH-DOG TIMER HAMCOP MICROPROCESSOR COMPANION CHIP

WATCH-DOG TIMER OPERATION

The functional block diagram of the watchdog timer is shown in Figure 9-1. The watchdog timer uses GCLK as its
only source clock. To generate the corresponding watchdog timer clock, the GCLK frequency is prescaled first, and
the resulting frequency is divided again.

WTDAT
MUX
1/16 Interrupt

1/32
WTCNT
PCLK 8-bit Prescaler Reset Signal Generator RESET
1/64 (Down Counter)

1/128

WTCON[15:8] WTCON[4:3] WTCON[2] WTCON[0]

Figure 9-1. Watch-Dog Timer Block Diagram

The prescaler value and the frequency division factor are specified in the watchdog timer control register, WTCON.
The valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64, or 128.

Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock
cycle:

t_watchdog = 1/( GCLK / (Prescaler value + 1) / Division_factor )

WTDAT & WTCNT

When the watchdog timer is enabled first, the value of WTDAT (watchdog timer data register) cannot be
automatically reloaded into the WTCNT (timer counter). For this reason, an initial value must be written to the
watchdog timer count register, WTCNT, before the watchdog timer starts.

CONSIDERATION OF DEBUGGING ENVIRONMENT

When HAMCOP is in debug mode using Embedded ICE, the watch-dog timer must not operate.

The watch-dog timer can determine whether or not the current mode is the debug mode from the CPU core signal
(DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watch-dog timer is not activated
when the watchdog timer is expired.

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HAMCOP MICROPROCESSOR COMPANION CHIP WATCH-DOG TIMER

WATCH-DOG TIMER SPECIAL REGISTERS

WATCH-DOG TIMER CONTROL REGISTER (WTCON)

Using the Watch-Dog Timer Control register, WTCON, you can enable/disable the watch-dog timer, select the clock
signal from 4 different sources, enable/disable interrupts, and enable/disable the watch-dog timer output.
The Watch-dog timer is used to resume the HAMCOP restart on mal-function after power-on; if controller restart is
not desired, the Watch-dog timer should be disabled.

If the user wants to use the normal timer provided by the Watch-dog timer, please enable the interrupt and disable
the Watch-dog timer.

Register Address R/W Description Reset Value

WTCON 0x0006000 R/W Watch-dog timer control Register 0x8021

WTCON Bit Description Initial State

Prescaler value [15:8] the prescaler value 0x80
The valid range is from 0 to (28-1)
Reserved [7:6] Reserved. 00
These two bits must be 00 in normal operation.
Watch-dog timer [5] Enable or disable bit of Watch-dog timer. 1
enable/disable 0 = Disable Watch-dog timer
1 = Enable Watch-dog timer
Clock select [4:3] This two bits determines the clock division factor 00
00: 16 01: 32
10: 64 11: 128
Interrupt [2] Enable or disable bit of the interrupt. 0
enable/disable 0 = Disable interrupt generation
1 = Enable interrupt generation
Reserved [1] Reserved. 0
This bit must be 0 in normal operation
Reset enable/disable [0] Enable or disable bit of Watch-dog timer output for reset 1
signal
1: asserts reset signal of the HAMCOP at watch-dog time-
out
0: disables the reset function of the watch-dog timer.

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WATCH-DOG TIMER HAMCOP MICROPROCESSOR COMPANION CHIP

WATCH-DOG TIMER DATA REGISTER (WTDAT)

The watchdog timer data register, WTDAT is used to specify the time-out duration. The content of WTDAT can not
be automatically loaded into the timer counter at initial watchdog timer operation. However, the first time-out occurs
by using 0x8000(initial value), after then the value of WTDAT will be automatically reloaded into WTCNT.

Register Address R/W Description Reset Value

WTDAT 0x0006004 R/W Watch-dog timer data Register 0x8000

WTDAT Bit Description Initial State

count reload value [15:0] Watch-dog timer count value for reload. 0x8000

WATCH-DOG TIMER COUNT REGISTER (WTCNT)

The watchdog timer count register, WTCNT, contains the current count values for the watchdog timer during normal
operation. Note that the content of the watchdog timer data register cannot be automatically loaded into the timer
count register when the watchdog timer is enabled initially, so the watchdog timer count register must be set to an
initial value before enabling it.

Register Address R/W Description Reset Value

WTCNT 0x0006008 R/W Watch-dog timer count Register 0x8000

WTCNT Bit Description Initial State

Count value [15:0] The current count value of the watch-dog timer 0x8000

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