SCALABLE ENCYPTION ALGORITHM (SEA) USING CONTENT ADDRESSABLE MEMORY (CAM)

A PROJECT REPORT Submitted by

HARISH H MANIMARAN S NAVEEN R NAVEENKUMAR G

in partial fulfillment for the award of the degree of

BACHELOR OF ENGINEERING
IN

ELECTRONICS AND COMMUNICATION ENGINEERING

MAAMALLAN INSTITUTE OF TECHNOLOGY, SRIPERUMBUDUR. ANNA UNIVERSITY: CHENNAI 600 025

APRIL 2012

ANNA UNIVERSITY: CHENNAI 600 025

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BONAFIDE CERTIFICATE
Certified that this project report .SCALABLE ENCRYPTION ALGORITHM (SEA) USING CONTENT ADDRESSABLE MEMORY (CAM). is the bonafide work of .HARISH H, MANIMARAN S, NAVEEN R, NAVEENKUMAR G. who carried out the project work under my supervision.

SIGNATURE Mr.M.AYYADURAI. M.E. HEAD OF THE DEPARTMENT DEPARTMANT OF E.C.E., MAAMALLAN INSTITUTE OF TECHNOLOGY, SRIPERUMBUDUR.

SIGNATURE Mr.T.HEMANAND. M.E. SUPERVISOR ASSISTANT PROFESSOR, DEPARTMENT OF E.C.E., MAAMALAAN INSTITUTE OF TECHNOLOGY, SRIPERUMBUDUR.

INTERNAL EXAMINER

EXTERNAL EXAMINER

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ACKNOWLEDGMENT

We sincerely thank Dr. JEPPIAAR M.A, B.L, PhD, Our Honourable Founder and Chairman, for his endeavour in educating us in this premier institution. We would like to thank & express our heart full gratitude to Our Principal Dr. ABBAS MOHAIDHEN M.E, PhD, who gave us many thoughts for the completion of this project. We would like to express our sincere thanks to Our Head of the Department Mr. M.AYYADURAI M.E. for his constant supervision. We would like to express our special thanks to our Internal Guide and Project Coordinator Mr. T.HEMANAND M.E. Assistant Professor, Electronics and Communication Department for his valuable guidance towards the completion of our project. We would like to express our gratitude to all the Faculty Members of Electronics and Communication Department for their continuous support and we thank our PARENTS who gave us the encouragement to complete this project successfully. HARISH H MANIMARAN S NAVEEN R NAVEENKUMAR G
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ABSTRACT
SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards or processors. In this letter, we investigate its performances in recent field-programmable gate array (FPGA) devices using content addressable memory called CAM. Most memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required to find an item stored in memory can be reduced considerably if the item can be identified for access by its content rather than by its address. A memory that is accessed in this way is called contentaddressable memory (CAM). Scalable encryption algorithm (SEA) was initially designed as a low-cost encryption/ authentication routine (i.e., with small code size and memory) targeted for processors with a limited instruction set (i.e., AND, OR, XOR gates, word rotation, and modular addition). In addition to the performance evaluation, we show that the algorithms scalability can be turned into a fully generic VHDL design, so that any text, key, and bus size can be straightforwardly reimplemented without any modification of the hardware description language, with standard synthesis and implementation tools.

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TABLE OF CONTENTS

CHAPTER NO.

TITLE ABSTRACT LIST OF FIGURES LIST OF ABBREVIATIONS

PAGE NO. iv ix x 1 2 3 4 4

1.

INTRODUCTION TO VLSI 1.1 INTRODUCTION 1.2 MICRON TECHNOLOGY 1.3 VLSI FEATURES 1.4 TYPICAL IC DESIGN FLOW

2.

VERILOG-HARDWARE DESCRIPTION LANGUAGE 2.1 INTRODUCTION 2.1.1 History 2.2 CAPABILITIES 2.3 HARDWARE ABSTRACTION 2.4 BASIC TERMINOLOGY 2.4.1 Entity Declaration 2.4.2 Architecture 2.4.3 Configuration Declaration 2.4.4 Package Declaration 2.4.5 Package Body 2.5 STRUCTURAL STYLE OF MODELING 2.5.1 Dataflow Style of Modeling 2.5.2 Behavioral Style of Modeling 2.5.3 Mixed Style of Modeling 2.5.4 Model Analysis 2.5.5 Simulation 2.6 COMPILATION 2.7 SIMULATION 2.8 XILINIX v

5 6 7 7 9 9 9 10 10 10 10 11 12 12 12 13 13 14 15 15

CHAPTER NO.

TITLE 2.8.1 Design Entry 2.8.2 Implementation 2.8.3 Device Download and Program File Formatting

PAGE NO. 16 16 17

3.

SCALABLE ENCRYPTION ALGORITHM

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3.1 INTRODUCTION 3.2 SPECIFICATION 3.2.1 Parameters and Definitions 3.2.2 Basic Operation 3.2.2.1 Bitwise XOR 3.2.2.2 Substitution Box S 3.2.2.3 Word Rotation R 3.2.2.4 3.2.2.5 Bit Rotation r Addition mod2b

19 20 20 21 21 22 22 22 23 23 24 25 25 26 26 27 27 27 27

3.2.2.6 The Round and Key Round 3.2.3 The Complete Cipher 3.3 DESIGN PROPERTIES OF THE COMPONENTS 3.3.1 Substitution Box S 3.3.2 Bit and Word Rotation (r and R): 3.3.3 Addition mod2b 3.4 OVERALL STRUCTURE 3.5 SECURITY ANALYSIS 3.5.1 Resistance against Known Attacks 3.5.1.1 Linear and Differential Cryptanalysis 3.5.1.2 Extensions of Linear and Differential Cryptanalysis 3.5.1.3 3.5.1.4 Square Attacks Truncated and Impossible Differentials vi

28

30 31

CHAPTER NO.

TITLE 3.5.1.5 Interpolation Attacks 3.5.1.6 Slide Attacks 3.5.1.7 Related Key Attacks 3.5.1.8 Complementation Properties 3.5.1.9 Algebraic Attacks 3.5.2 3.6 Suggested Number of Rounds

PAGE NO. 31 31 31 32 32 33 33

PERFORMANCE ANALYSIS

4.

CONTENT ADDRESSABLE MEMORY 4.1 INTRODUCTION 4.2 PACKET FORWARDING USING CAM 4.3 CAM BASICS 4.4 CORE CELLS 4.4.1 4.4.2 NOR Cells NAND Cells

36 37 38 40 42 42 43

5.

SEA ARCHITECTURE

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5.1 BLOCK DIAGRAM 5.2 KEY GENERATION 5.2.1 Cryptography 5.3 ENCRYPTION 5.3.1 Block Diagram of Encryption 5.3.2 Operation of Encryption

46 47 48 49 50 50 51 53 54

5.4 DECRYPTION 5.4.1 Block Diagram of Encryption 5.4.2 Operation of Encryption

6.

SIMULATION RESULTS 6.1 6.2 KEY GENERATION RESULTS ENCRYPTION RESULTS vii

55 56 57

CHAPTER NO.

TITLE 6.3 DECRYPTION RESULTS

PAGE NO. 58

7.

SYNTHESIS REPORTS 7.1 KEY GENERATION 7.1.1 7.1.2 RTL Schematic Gate Level Diagram of Key Generation 7.1.3 Synthesis Report

59 60 60 61

62 64 65 66 66 67

7.1.4 Translation Report 7.1.5 7.2 Mapping Report

ENCRYPTION 7.2.1 7.2.2 RTL Schematic Gate Level Diagram of Encryption 7.2.3 Synthesis Report

68 70 70 71

7.3

DECRYPTION 7.3.1 7.3.2 RTL Schematic Gate Level Diagram Of Decryption 7.3.3 Synthesis Report

72 75 76 76

8.

ADVANTAGES AND APPLICATIONS 8.1 8.2 Advantages Applications

9.

CONCLUSION References

77 80

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LIST OF FIGURES
FIG NO. 1.1 1.2 3.1 4.1 4.2 4.3 4.4 5.1 5.2 5.3 5.4 5.5 5.6 6.1 6.2 6.3 7.1 7.2 7.3 7.4 7.5 7.6 TITLE Features of VLSI Typical IC Design Flow Encrypt/Decrypt Round And Key Round Block Diagram of Content Addressable Memory Address lookup of CAM Simple Schematic Of A Model CAM CAM core cells for (a) 10-T NOR-type CAM (b) 9-T NAND-type CAM Block Diagram of SEA Architecture Block Diagram of Key Generation Block Diagram of Encryption Encryption Operation Block Diagram of Decryption Decryption Operation Key Generation Results Encryption Results Decryption Results RTL Schematic of Key Generation Gate Level of Key Generation RTL Schematic of Encryption Gate Level of Encryption RTL Schematic of Decryption Gate Level of Decryption PAGE NO. 4 4 24 38 40 41 43 46 48 50 50 53 54 56 57 58 60 61 66 67 70 71

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LIST OF ABBREVIATIONS
1. CAD 2. CAE 3. CMOS 4. DES 5. DOD 6. DSM 7. EDIF 8. FPGA 9. HDL 10. IC 11. IP 12. LSI 13. MLSA 14. MSI 15. PAR 16. RAM 17. RSA 18. SEA 19. SM 20. SSI 21. VDSM 22. VHDL 23. VHSI 24. VLSI Computer Aided Design Computer Aided Engineering Complementary Metal Oxide Semi-Conductor Data Encryption Standard Department Of Defense Deep Sub Micron Technology Electronic Design Interchange Format Field Programmable Gate Array Hardware Description Language Integrated Circuits Internet Protocol Large Scale Integration Match Line Sensing Amplifier Medium Scale Integration Place And Route Read Access Memory Rivest Shamir Adlemen Scalable Encryption Algorithm Sub Micron Small Scale Integration Very Deep Sub Micron Verilog Hardware Description Language Very High Speed Integrated Circuit Very Large Scale Integration