Name: Laysico, Nikko Angelo A.

Rating :________________
Date Perfomed: 04-28-14_____ Date Submitted: 04-28-14_
Section: EC42FB1____________
Introduction to Digital IC Design(ECE 132)
DESIGN A INVERTER WITH NMOS ENHANCEMENT LOAD
Activity No. 6

I.Intended Learning Outcome

1. Familiarize ourselves in modeling an NMOSFET using T-Spice
2. Learn how to build a NETLIST in editing parameters of a NMOSFET
3. Understand on how to troubleshoot errors of a NETLIST using T-Spice
4. Build an output waveform of an INVERETR with NMOS enhancement load characteristics
using W-Edit


II.Background Information

NMOS Structure























Substrate contact--to reverse bias the pn junction. Connect to most negative supply voltage in most
circuits.

Source: the terminal that provides charge carriers.
(electrons in NMOS)
Drain: the terminal that collects charge carriers.

NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter

Once the operation and characterization of an inverter circuits are thoroughly understood, the results
can be extended to the design of the logic gates and other more complex circuits.

MOSFET Digital Circuits


N-Channel MOSFET FORMULA


NMOS Inverter
For any IC technology used in digital circuit design, the basic circuit element is the logic inverter

Once the operation and characterization of an inverter circuits are thoroughly understood, the results
can be extended to the design of the logic gates and other more complex circuits.

NMOS INVERTER WITH ENHANCEMENT LOAD
This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the
resister loaded inverter, which is thousands of times larger than a MOSFET.



N-CHANNEL MOSFET CONNECTED AS SATURATED LOAD DEVICE
An n-channel enhancement-mode MOSFET with the gate connected to the drain can be used as load
device in an NMOS inverter.
Since the gate and drain of the transistor are connected, we have
VGS=VDS
When
VGS=VDS>VTN,
a non-zero drain current is induced in the transistor and thus the transistor operates in saturation only.
And following condition is satisfied.

VDS>(VGS-VTN)
VDS(sat)= (VDS-VTN) because

VGS=VDS or VDS(sat)= (VGS-VTN)

In the saturation region the drain current is

iD=Kn(VGS-VTN)2= Kn(VDS-VTN)2


NMOS INVERTER WITH ENHANCEMENT LOAD/SATURATED

In the saturation region the load drain current is

iDL=KL(VGSL-VTNL)2= KL(VDSL-VTNL)2

For VGSD<VTN ( driver transistor )transistor is in cutoff mode and
does not conduct drain current

0= iDL=KL(VGSL-VTNL)2= KL(VDSL-VTNL)2VGSL=VTNL
or VDSL=VTNL
As a result the output high voltage VO is degraded by the threshold voltage or VO,, max= VOH=VDD-VTNL












III.Learning Activities

1. Open T-Spice Then click File>New


2. After clicking the new, a new block will appear then select SPICE netlist to build the netlist of the
NMOS transistor.


3. After choosing the spice netlist you can now copy the said parameters of the NMOSFET.


4. Paste the said NELTIST of the opened tab
* enhancement load inverter
C1 N2 Gnd 10pF
M2 Vdd Vdd N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N2 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v4 N5 Gnd 5.0
Vdd Vdd Gnd 5v
.op
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml1_typ.md"
.dc v4 0 5.0 0.1
.tf v(N2) v4
.print v(N2)
.end

Before you run this netlist you should add an existing list to line 2

.model N1 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u VTO=1 KP=200U LAMBDA=0.01
LEVEL=1
.model N2 NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u VTO=1 KP=200U LAMBDA=0.01
LEVEL=1






5. After copying the said NETLIST you can now Run and BUILD the NETLIST in order to view the
proper output or waveform. Click play button




After clicking the play button, T-Spice will automatically execute the output waveform of the I-V
characteristic using W-Edit and the correct result will be





6. Now observe what happens when you change the parameters.


IV.Questions

1. What is the use of an n-Channel enhancement-mode MOSFET with the gate connected to the
drain?
-It simply says that it can be used as a load device in an NMOS inveter.

2. What status of a transistor is having if For VGSD<VTN?
-it is just the transistor is in cutoff mode and does not conduct drain current.

3. How can you relate the aspect ratio to the parameters of the transistor?
-the ratio Kd/Kl is related to the width to length parameters of the transistor and load transistor.



V.CONCLUSION

I therefore conclude that as the input voltage becomes greater than VIt, the driver transistor Q- point continues
to move up the load curve and the driver becomes biased in the non-saturation region. And As the VI=>VTND, A
non-zero drain current is induced in the transistor and thus the drive transistor operates in saturation only.