RANJAN KUMAR

Mob: +91-9886276740 Room No: 16, Sri Sai PG, Marathahalli

ranjankumargnit@gmail.com Bangalore-560337


To work for a progressive company wherein my skills will be best utilized by the organization
for its growth and wherein I can gain invaluable experience and become a successful
professional.


Graduate technical intern in DTS team at Intel India Pvt Ltd.
Final year M.Tech candidate with strong academic background.
Motivated team player and individual contributor with excellent interpersonal and
communication skills.


Course/Degree Name of the
Institute
University
/Board
Year of
Passing
CGPA/Pe
rcentage
Class
M.TECH in
VLSI System
Design
(Pursuing)
National Institute Of
Technology,
Warangal

NITW

2014

8.68

First class

B.TECH in
ECE
Guru Nanak Institute
Of Technology,
Kolkata
WBUT,
Kolkata

2011

8.72

First class

AISSCE(12
th
)
D.A.V. Public
School

C.B.S.E.

2007

86.60

Distinction

AISSE(10
th
)
D.A.V. Public
School

C.B.S.E.

2005

86.00

Distinction




OBJECTIVE
ACADEMIC QUALIFICATIONS
SUMMARY


Programming
Language
C, PERL, Python, TCL
EDA Tools Tanner, Xilinx ISE, VCS, Aceplorer, Primetime PX
Hardware Description
Language
VHDL, Verilog

:
Intel Corporation Bangalore, India [May2013 May2014]
Graduate Technical Intern
Projecting Pre-Si Power at IP, SoC and Platform Levels.
- Developed and owned architecture level power models to roll-up IP power to SoC
and Platform levels.
- Co-designed methodologies involving an external vendor tool (Aceplorer) and an
internal DTS-owned SPAN power database infrastructure.
Impact: Work during internship enabled providing PnP targets over 150 Key Performance
Indicators (KPIs) for phone and tablet platforms to various customers.
Tools and Environment: Cadence Virtuoso, Aceplorer, Primetime PX, Python API, Perl.
Intel Platforms: Moorefield, Merrifield, Baytrail, Client SoCs.


Analog Design - Fully compensated OP-AMP with temperature independent biasing
CAD Tool and Environment: Cadence Virtuoso, 180nm Technology
- Specs: Gain 100dB, UGB 10MHz, Phase Margin 87
Analog Design Low voltage Low power comparator
CAD Tool and Environment: Cadence Virtuoso, 180nm Technology
- Specs: Sampling freq 900MHz, Resolving capability 10uV, Pmax 7mW.
- Positive feedback along with zero quiescent current technique.
Analog Design - Design of high gain comparator
CAD Tool and Environment: Tanner, 2um Technology
- Specs: Sampling freq 200MHz, Resolving capability 0.2mV.
SKILL SET
WORK EXPERIENCE
ACADEMIC PROJECTS
FPGA Design 32-bit single cycle MIPS Processor
CAD Tool and Environment: Xilinx ISE, Spartan FPGA
- Implemented a subset of the MIPS instruction set (R-type, Load, Store and Branch).
- Mapped the functional design to Spartan FPGA hardware.
System Design: Design of Asynchronous FIFO
CAD Tool: Verilog, VCS
- RTL design of the FIFO.
Gesture controlled vehicle
- Designed a three-wheel robo-car which will be driven by taking human hand gestures
as inputs.
- Pulses needed for vehicle motion generated by optical sensors.


Digital IC
design
Analog IC
design
VLSI DSP
architectures
Device
Modeling
Low power
VLSI design
Mixed-signal
design
VLSI Design
Automation
Testing and
Testability


Secured GATE rank of 559 with 99.68 percentile.
Spontaneous recognition awards at Intel for result orientation and quality.
Consistently placed top 1% of the class.


Coordinator for annual symposium at undergraduate college.
Part of winning team in several cricket tournaments 2007, 2012.


1) Mrs. V Bharathi
Engineering Manager, Intel India
Mob: +91 - 9900578711
2) Mr. Arun Janarthanan
Low Power SoC DA, Intel India
Mob: +91 9611354477
ACADEMIC COURSEWORK
ACADEMIC/OTHER ACHIEVEMENTS
EXTRA CURICULLAR ACTIVITIES
REFERENCES