TN 203 0.6 PDF

Copyright 2012 Microsemi Page 1
Rev. 0.6, Nov 2012 Analog Mixed Signal Group

One Enterprise Aliso Viejo, CA 92656 USA
PRELIMINARY/ CONFIDENTIAL
Technical Note TN-203
Sanjaya Maniktala, 2012
Voltage-Mode, Current-Mode
(and Hysteretic Control)

Introduction
Switching regulators have been with us for many years. They were considered tricky to design and still are. In 1976 Silicon
eneral !later "in#inity$ then %icrosemi&$ introduced the first monolithic !I'(based& switching controller$ the S1)*+ ,-ulse
.idth Integrated 'ircuit/. 0 little later$ this chi1 was im1roved and became the ,S2)*+/ historic industry workhorse. 0nd very
soon thereafter$ it was available from multi1le chi1 vendors. 3ee1 in mind that switching stages based on discrete designs were
already gaining ground$ 1articularly in military a11lications. In fact$ some resourceful engineers had even made ,switch(mode
1ower su11lies/ by adding related circuitry around one of the highest(selling chi1s in history4 the ,))) timer/ !sometimes called
the ,I' Time %achine/&$ introduced in 1971 by Signetics !later -hili1s$ then 56-&. The S1)*+ was however the first I' in which
all the re7uired control functionality was 1resent on a single chi18die. .ith the ra1idly escalating concurrent interest in
switching 1ower su11lies at the time$ it is no sur1rise that as early as 1977 the very first book on the sub9ect$ written by the late
0braham -ressman$ a11eared on the scene. Together$ these events s1urred interest in an area well beyond most 1eo1le:s
e;1ectations$ and ushered in the world of switching 1ower conversion as we know it today.

The S1)*+82)*+ drove a 1air of !bi1olar& switching transistors with a ,duty cycle (ratio of switch ON-time to the total time
period) which was proportional to the control voltage. <y using switching transistors to switch the in1ut voltage source =5 and
=## into an "' low 1ass filter$ a relatively efficient voltage regulator was 1roduced. 0t the heart of this regulator was the PWM
(pulse width modulator) comparator. The out1ut 1ulse(train to drive the transistors with was a result of a11lying a !relatively&
smooth control voltage on one of this com1arator:s in1ut terminals$ along with a ,sawtooth/ or a ,-.% ram1/ generated from
the cloc$ on its other in1ut. See !igure ". This techni7ue is known as >voltage(mode 1rogramming/$ or ,voltage(mode control/
!,?%'/& since the duty cycle is 1ro1ortional to the control voltage. The control voltage is in effect the difference between the
actual out1ut voltage and the ,reference/ value !the value we want to fi; the out1ut at$ i.e. the ,set1oint/&. .e will discuss this
figure in more detail shortly.

0nother well(known techni7ue today$ which has also been around since the @As$ senses the 1eak current in the 1ower switch or
inductor$ and turns the switch =## at a 1rogrammed level of current. This techni7ue is called current(mode control !,'%'/&.
3ee1 in mind it was not ,brand(new/ at the time. In fact it had been discovered years ago$ but few had realiBed its significance till
Cnitrode 'or1. !now Te;as Instruments& came along. It received a huge boost in 1o1ularity in the form of the world:s first
current(mode control !'%'& chi1$ the #lyback controller C'1@+* from Cnitrode. In '%'$ there is in effect a !fast(acting& ,inner/
current loo1 along with the ,outer/ !slower& ,voltage loo1/ which carries out the out1ut regulation. See the note on ram1
generation within !igure "$ indicating how this 1articular as1ect is different between ?%' and '%'. -rima facie$ '%' seems to #e
#etter. ,-ulse(by(1ulse/ became synonymous with '%'. It was once even thought to be the silver bullet$ or magic wand$ to fi;
everything that voltage-mode control was not. The C'1@+* was later im1roved to C'2@+*$ and shortly thereafter$ following the
success story of the S2)*+$ the C'2@+* was soon available from innumerable chi1 vendors. <ut a few years into this success
story$ e$pectations got somewhat #lunted.

The disadvantages of '%' surfaced slowly. That growing realiBation was succinctly summed u1 in a well(known Design 5ote
D5(6* from Cnitrode$ which said4 ,there is no single topology which is optimum for all applications% Moreover& voltage-mode
control ' (f updated with modern circuit and process developments ' has much to offer designers of today)s high-performance
supplies and is a via#le contender for the power supply designer)s attention%/ It also says4 ,it is reasona#le to e$pect some confusion
to #e generated with the introduction of the *++,-./ ' a new voltage-mode controller introduced almost "/ years after we told the
world that current-mode was such a superior approach%/

To 1ut things in 1ers1ective$ the above(mentioned design note was written by ,the father of the -.% controller I' industry$/
<ob %ammano$ who develo1ed the first voltage(mode control I'$ the S1)*+. "ater$ as Staff Technologist in the -ower I'
division of Cnitrode !a division that he had 9ointly created with two others from Silicon eneral&$ %ammano led the develo1ment
of the first current(mode control I'$ the C'1@+*.


N
P
:N
S
+
-
VCOMP
EA-output
{{
VO
{
VIN
POWER STAGE
C
O
N
T
R
O
L

S
E
C
T
I
O
N
T
r
a
n
s
fo
r
m
e
r

(
o
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io
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a
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)
Feedback trace
D
r
iv
e
r

n
o
t
s
h
o
w
n
+
-
VREF
VFB
EA-input
ERROR
AMP
{
Divider
(Sensor)
{
o
p
to
c
o
u
p
le
r

(
o
p
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io
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CONTROL
OUTPUT
LINE
REFERENCE
Rf2
Rf1
C
o
n
t
r
o
l
v
o
l
t
a
g
e
OUTPUT
INPUT
(LINE)
REFERENCE
-
+
FB pin
CONTROL
EA OUT/
Control Voltage/
COMP pin
Divider Error Amp
PWM
Comparator Switch LC Post Filter
Equivalent
PLANT
FEEDBACK
PLANT
FEEDBACK
Rf2
Rf1
VIN
In Current Mode Control, the RAMP is
generated from the Inductor Current
RAMP RAMP
!s&
E!s&
PLANT
FEEDBACK (COMPENSATOR)

Figure 1: Voltage and Current Mode Regulators with their shared Functional Blocks

Building Blocks of Switching Regulators and Stabilit
In !igure "$ we see the building blocks of a ty1ical switching regulator. There is a ,1ower stage/$ consisting of switch8diode$
inductor8transformer$ and in1ut8out1ut ca1s. The in1ut ,?I5/ comes into this block and gets converted into the out1ut$ ?=.
0round this block is the ,control section/ block$ consisting essentially of a voltage divider$ an error am1lifier$ and a -.%
com1arator. In classic voltage mode control$ the voltage ram1 to the -.% com1arator is fi;ed$ and is artificially generated from
the clock. In current mode control$ this ram1 is the sensed inductor8switch current ma11ed into a 1ro1ortional voltage ram1
that is a11lied to the -.% com1arator. 3ee1 in mind that in both ?%' and '%' there is a clock$ and its basic function is to
determine the moment the switch turns ON in every cycle. The moment at which the switch turns O!! within each cycle is
determined by the ,feedback loo1/. <y using a clock$ we ensure a constant re1etition rate$ or constant switching fre0uency$
something that is considered desirable for switching regulators$ 1articularly for com1lying with F%I limits.

!ote" ,Eysteretic controllers/$ discussed later$ ty1ically dis1ense with the error am1lifier and the clock !and though they retain
something 7uite similar to the -.% com1arator$ they im1lement it in a very different manner&. Therefore$ trying to kee1 a
constant switching fre7uency in that case becomes a ma9or design challenge.

=n the right side of !igure "$ we show how the switching regulator can be mentally 1artitioned and visualiBed when discussing
loop sta#ility. 5otice the terminology in use. .e see that the -.% com1arator is considered 1art of the ,-lant/$ along with the
1ower stage$ and the rest falls into the ,#eedback/ section also called the ,'om1ensator/. Their res1ective transfer functions are
denoted as !s& and E!s& res1ectively.

In the mathematical treatment of loo1 stability$ we define a ,transfer function/$ which is basically the out1ut of a given block
divided by its in1ut. The out1ut and in1ut do not have to be voltages$ or currents$ or even similar 1arameters. #or e;am1le$ the
out1ut of the -.% com1arator is the ,duty cycle/ whereas its in1ut is the ,control voltage/ !out1ut of the error am1lifier&. The
magnitude of this transfer function is called its ,gain/ and its argument is its ,1hase/. Sometimes$ the transfer function itself is
9ust called the !com1le;& ,gain/.


#b$ecti%es and Challenges of &oo' (esign
The entire 1ur1ose of loo1 stability consists of two tasks. !irst is to discover what !s& !the 1lant transfer function& is$ i.e. its
ain(-hase 1lot with all its inherent ,1oles/ and ,Beros/. The second is to design the com1ensator !feedback section& accordingly$
such that its 1oles and Beros are ,correctly located/ with res1ect to those from the 1lant. .hat does ,correct location/ meanG The
criterion for that is based on what we want the ,o1en(loo1 gain/ to look like. In !igure "$ the overall gain going once fully around
in a loo1$ 1assing though the 1lant and feedback blocks$ is called the o1en(loo1 gain. 'learly$ it is the 1roduct of two gain blocks
in succession$ or the 1roduct ,!s& H E!s&/. =nce we know what !s& is$ we can design E!s& such that !s&HE!s& !the combined
gain& is very close to a straight line of slope -" !1AI fall in gain every 1AI increase in fre7uency&. That is the basic sim1lified
criterion or design target for stabiliBing the loo1 of any switching converter$ whether it is '%' or ?%'. The difference is that in
'%' the 1lant transfer function !s& is very different from the 1lant transfer function based on ?%'. <ut the final result$ the
sha1e of !s&HE!s&$ is intended to be the same !(1 slo1e&. .hat unfortunately ha11ens is that as line and load variations occur&
1(s) can change 0uite a lot in one control method compared to the other% So we may set the loo1 correctly at some ,sweet s1ot/
only to find it changing a lot$ usually undesirably$ as line and load change. 0nd that is indeed where the real differences between
'%' and ?%' become more a11arent. This is discussed ne;t$ and highlights the challenges to com1ensator design using '%' or
?%'.

!ote" 0 slo1e of ,(1/ is a straight line on a ,log ain/ versus ,log #re7uency/ 1lot$ with a slo1e such that the gain decreases by a
factor of 1A !or ,*A decibels/& every decade !1AI& increase in the fre7uency. 0lternatively 1ut$ that is a decrease of 6 decibels !a
factor of *& every octave !*I& increase in fre7uency.

!ote" The 1roduct ,HE/ is called the ,o1en(loo1 gain/ even though the loo1 itself is closed. Eowever$ for that reason it is
sometimes erroneously called the ,closed loo1 gain/$ which is actually a different term in loo1 theory.

)re*uenc (omain Analsis
#or the feedback loo1Js most generaliBed analysis$ and the overall res1onse to an arbitrary stimulus or disturbance$ a transfer
function is usually written out in the com1le;(fre7uency 1lane$ or ,s(1lane/. This is done because it actually sim1lifies the
analysis significantly$ com1ared to trying to do the same thing as a function of time. See !igure 2. The former is called fre7uency
domain analysis$ the latter is time domain analysis. <ut eventually$ the entire conce1t of the fre7uency domain is actually 9ust a
mathematical construct$ not even necessarily intuitive$ considering we now even have negative fre7uencies to integrate over. So
eventually$ we do need to ma1 the res1onses from this ,fre7uency domain/ back into the ,time domain/$ and that is what is
eventually o#serva#le to us.


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s-+lane analysis ($a+lace Trans,or-)
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)igure +" .orking in the #re7uency Domain versus in the Time Domain

!ote" .e define ,s K LM9N/. Eere$ ,L/ is a number that mathematically s1eaking 9ust hel1s functions converge when we carry out
integration$ but is also ultimately res1onsible for im1arting to any real(world res1onse a real(world e;1onential decay with
res1ect to time$ based on the function e
Lt
. ,9/ is the usual imaginary number O!(1& and NK*Pf$ where f is the fre7uency. Together
these are res1onsible for the oscillatory 1art of the res1onse$ based on the function e
(9Nt
. 3ee1 in mind that all this is 9ust a more
generaliBed e;tension of what we learned in high school4 any re1etitive !>1eriodic>& waveform of an almost arbitrary sha1e can
be decom1osed into a sum of several sine !and cosine& waveforms of fre7uencies. That is what #ourier series analysis is. In
#ourier series$ though we do get an infinite series of terms$ the series is a sim1le summation consisting of terms com1osed of
discrete fre7uencies !the harmonics&. .hen we deal with more arbitrary wave sha1es$ including those that are not necessarily
1eriodic$ we need a continuum of fre7uencies to decom1ose any waveform$ and then understandably the summation of #ourier
series terms becomes an integration over fre7uency. That is$ how the #ourier series evolved into the >#ourier transform$> and
from there on to the "a1lace transform !mathematics in the s(1lane&. In general$ decom1osing an a11lied stimulus !waveform&
into its fre7uency com1onents$ and understanding how the system res1onds to each fre7uency com1onent$ is called >fre7uency
domain analysis.> The ,s(1lane/ is in effect a com1le; fre7uency 1lane$ and "a1lace transform is the way to conduct the most
generaliBed form of fre7uency domain analysis. Fventually$ though$ we should not get carried away$ for the fre7uency domain is
9ust a mathematical construct ((( not even intuitive anymore$ considering we now integrate over negative fre7uencies !what is a
negative fre7uencyG&. So eventually$ we do need to ma1 the calculated res1onses from the ,fre7uency domain/ back into the
,time domain/$ and that is what is eventually o#serva#le to us$ and is literally ,real/.

!ote" If we are talking about steady repetitive waveforms$ we can set s K 9N$ and we will get back the well(known #ourier series
decom1osition.

Plant ,ransfer )unctions
This is often called the ,control to out1ut/ transfer function$ since it is in effect the out1ut voltage divided by the control voltage.
It is a 1roduct of three successive !inde1endent& gain blocks4 the -.% com1arator$ the switching 1ower section$ and the out1ut
"' filter. 5ote that only in the <uck$ do we have an actual "' 1ost filter. In the case of a <oost or a <uck(<oost$ there is something
!the switch& connected between the " and the ' !out1ut ca1&. So strictly s1eaking$ we cannot consider it as a se1arate


!inde1endent& "' gain block and 9ust multi1ly all the successive gain blocks. Eowever$ using the ,canonical model/$ it can be
shown that an effective "' 1ost(filter !a se1arate gain block& can be visualiBed for non-3uc topologies too$ 1rovided we use the
effective inductance " K "8!1(D&
*
. The im1ortant 1oint to note is that this effective inductance varies with in1ut voltage !for a
given out1ut& since D decreases as in1ut raises$ causing a higher effective inductance and thereby tending to make the loo1
res1onses more sluggish. In general$ large inductors and ca1acitors need several more cycles to reach their new steady(state
energy(levels$ after a line or a load transient. This sluggishness$ based on larger effective "$ is of greater im1act with ?%'$
because as we will see very shortly$ when using '%'$ the inductance is not even 1art of the 1lant transfer function to start with.
.ith ?%' it is.

.e will go through several figures ne;t$ to sum u1 the -lant transfer functions for ?%' and '%'.

)igure -" This is a <uck with classic ?%'. The D' gain !gain at low fre7uencies& changes as a function of ?I5 in classical ?%'$
because ?Q0%- the am1litude of the sawtooth a11lied to the -.% com1arator is traditionally fi;ed. This causes a change in
loo1 res1onse characteristics with res1ect to in1ut. #urthermore$ the line re4ection is not good under suddenly changing
conditions. The reason is that a sudden change in line is not ,felt/ by the -.% com1arator directly$ and so it continues with the
same duty cycle for a while. <ut any change in in1ut voltage ultimately re7uires a change in the steady(state duty cycle !as 1er
the steady D' transfer function e7uation of the converter4 DK?=8?I5&. So not changing the duty cycle 7uickly enough leads to an
out1ut overshoot or undershoot. The system has to ,wait/ for the out1ut error to be sensed by the error am1lifier$ and that
information to be communicated to the -.% com1arator as a change in the a11lied ,control voltage/. That eventually corrects
the duty cycle and the out1ut too$ but not before some swinging back and forth !ringing& around the settling value. Eowever$ if
we could 9ust change the ram1 voltage directly and instantaneously with res1ect to the in1ut voltage$ we would not need to wait
for the information to return via the control voltage terminal. Then the line re9ection would be almost instantaneous$ and
furthermore$ the D' gain in
!igure - would not change with in1ut voltage.

To im1lement the above$ we would need to do the following4
I5
Q0%- I5
Q0%-
?
? ? $ so Kconstant
?

This is called ,"ine #eedforward/. .e will see that '%' has similar 1ro1erties very naturally$ which was one of the reasons for
its 1erceived su1eriority for a long time. -ure ?%'$ on its own$ is certainly im1aired$ es1ecially in this res1ect. <ut 5M+ with 6ine
!eedforward (when implemented in a 3uc) actually offers superior line re4ection to the one coming naturally from +M+%

)igure ." This is a <oost with ?%'. 5ote that "ine #eedforward is not 1ractical here considering the com1le;ity of the terms. .e
would need to somehow set ?Q0%- 1ro1ortional to ?I5H!1(D&
*
$ based on the D' gain of !s&. 0lso note the a11earance of the Qight
Ealf -lane !QE-& Bero. It also a11ears in the <uck(<oost. It is 1resent for any duty cycle and for either ?%' or '%'. In a ,well(
behaved/ !left half 1lane& Bero$ the gain rises !or changes& by the amount ,M1/ at the location of the Bero$ and its 1hase increases
correspondingly. .ith an QE- Bero$ the 1hase falls even though the gain rises$ making this 1articular Bero very difficult to
com1ensate or deal with.

The e;istence of the QE- Bero in the <oost and <uck(<oost can be traced back to the fact that these are the only to1ologies
where an actual "' 1ost(filter doesn)t e;ist on the out1ut. So even though we created an ,effective/ "' 1ost(filter by using the
canonical modeling techni7ue$ in reality there is a switch8diode connected between the actual " and ' of the to1ology$ and that
is what is ultimately res1onsible for creating the QE- Bero. The QE- Bero is often e;1lained intuitively as follows !in the earliest
Cnitrode 011 5otes&4 if we suddenly increase the load the out1ut di1s slightly. This causes the converter to increase its duty

cycle in an effort to restore the out1ut. Cnfortunately$ for both the <oost and the <uck(<oost$ energy is delivered to the load only
during the switch(=## time. So$ an increase in the duty cycle decreases the =## time$ and unfortunately there is now a smaller
interval available for the stored inductor energy to get transferred to the out1ut. Therefore$ the out1ut voltage di1s even further

for a few cycles$ instead of increasing as we were ho1ing. This is the QE- Bero in action. Fventually$ the current in the inductor
does manage to ram1 u1 over several successive switching cycles to the new level$ consistent with the increased energy demand$
and so this strange counter(1roductive situation gets corrected. =f course 1rovided full instability has not already occurredR 0s
mentioned$ the QE- Bero can occur at any duty cycle. 5ote that its location moves to a lower fre7uency as D a11roaches 1 !i. e.$ at
lower in1ut voltages&. It also moves to a lower fre7uency if 6 is increased. That is one reason why bigger inductances are not
1referred in <oost and <uck(<oost to1ologies.

The usual method to deal with the QE- Bero is literally >1ushing it out> to higher fre7uencies where it canJt significantly affect
the overall loo1. F7uivalently$ we need to reduce the bandwidth of the o1en(loo1 gain 1lot to a fre7uency low enough that it 9ust
doesnJt >see> this Bero. In other words$ the crossover fre7uency must be set much lower than the location of the QE- Bero. In
effect$ the #andwidth and loop response suffers on account of the 78P 9ero.

)igure /" This is a <uck(<oost with ?%'. 0s for the <oost$ "ine #eedforward is not a 1ractical goal here. The QE- Bero is also
1resent here$ though its location is a little different as com1ared to a <oost.

)igure 0" This is a <uck with '%'. .e see the differences com1ared to ?%'. The D' gain is not a function of in1ut voltage !at
least to a first a11ro;imation&. The reason is that the -.% ram1 is derived from the current ram1$ and we know that the current
ram1 swing !SI& is a function of the voltage across the inductor during the =5(time$ i.e. it de1ends on ?I5(?= T ?I5. So in effect$
there is pseudo(line(feedforward not as 1erfect as we can im1lement by choice in ?%'. 5evertheless$ '%' does offer good line
re9ection$ which was historically one of the key reasons for its wide 1o1ularity. Eowever$ we can see that the D' gain is a
function of ,Q/ the load resistance. This causes a change in the loo1 characteristics with changes in load. <ut there is an
interesting 1ro1erty shown in the diagram because the location of the 1ole also varies with load. Therefore the #andwidth
remains unchanged with load !and line&. That is actually the same as in ?%' with "ine #eedforward im1lemented.

.e do see that '%' has a ,single 1ole/ at the resonant fre7uency of the load resistor and the out1ut ca1. In contrast$ we saw in
!igure - that ?%' has a double !two single& 1oles at the resonant fre7uency of the inductor and out1ut ca1. That by itself is not
really an issue$ because what it eventually means is that we need two Beros from the com1ensator to cancel out the double 1ole
in ?%'$ but only one Bero to cancel out the single 1ole of '%'. So the com1ensator can be simpler for '%' than for ?%'.
Ty1ically that means we can use a Ty1e * com1ensator !often based around a sim1le transconductance error am1& for '%'$
whereas we usually need a more com1licated Ty1e 2 com1ensator for ?%'. =ther than that$ what is the differenceG The
difference is that des1ite ,cancelation/ of the double 1ole arising from ?%'$ there can be a huge residual phase shift !rather$ a
huge back and forth 1hase swing& in the region around the cancelation fre7uency. This can lead to conditional stability issues$
es1ecially under non(linear !large& line8load disturbances. So '%' has somewhat more 1redictable and acce1table res1onses in
general.

)igure 1" This is a <oost with '%'. It also has the troublesome QE- Bero.

)igure 2" This is a <uck(<oost with '%'. It also has the troublesome QE- Bero.

This almost sums u1 our overview of the key differences between '%' and ?%'. There is one last issue as discussed ne;t. 5ote
that all along we have restricted ourselves to continuous conduction mode !''%&$ mainly for sim1licity sake. In any case$
discontinuous conduction mode !D'%& is encountered only for much lighter loads$ and further$ in many modern synchronous

to1ologies$ we may continue to stay by choice in ''% down to Bero load !that is called ,#''%/ or forced continuous conduction
mode&.

+ +

=

+ + +

ESR ESR IN IN
2 2
RAMP RAMP
0 0 0
s s

! !
"#s$
! !
s s s

%
Buck
3Plant 4ain, 43s5 in 6MC5
&ESR ' (##ESR$HC$
&0'()#LC$
&0%'R(L
FSQ Bero
"' double 1ole
' is the out1ut ca1$ with FSQ
Q is the load resistance
" is the inductance of the inductor
&*
&ESR
*A log
!?I58?Q0%-&
*A log
!fre7uency&
:his ;+ gain of plant varies
with input voltage in
conventional voltage mode
control% <o& loop response
changes with input --- unless
57=MP is made proportional to
5(N (line feedforward feature)
><7 9ero? :he ><7 of a cap has
wide tolerance@spread& and
can vary with fre0uency and
time (aging)% 3ut it can #e
roughly canceled with a pole
from the compensator% With
very low-><7 caps& lie
multilayer ceramics& this 9ero
moves out to a very high
fre0uency and then is of
almost no concern anyway
:he dou#le 6+ pole occurs
here% :here can #e severe
peaing in the gain plot right
here& #ecause of high Auality
factor BAC7(C/L)]. This is also
accompanied by a sudden 180
degrees phase shif ha can
lead o insabiliy or (ringing.
a
i
n
-eaking of "' 1ole
++M

)igure -" -lant Transfer #unction for a <uck$ Csing ?%'

Boost
&ESR ' (##ESR$HC$
&0'()#LC$
&0%'R(L
FSQ Bero
"' double 1ole
divided by !1(D&
*
&*
&ESR
*A log
!?I58U?Q0%- !1(D&
*
V
*A log
!fre7uency&
changes with input --- line
feedforward feature too
complicated to implement)
><7 Dero? :he ><7 of a cap has
a
i
n
-eaking of "' 1ole
( ) ( )

+ +

=

+ + +

R+P R+P
2
ESR ESR IN IN
2 2
RAMP RAMP
0
2
0 0
s s

D
s s
D

! !
"#s$
! !
s s s

%
&R+P'R(L Qight Ealf -lane Bero
&R+P
78P Dero? Needs to #e canceled
or moved out to a very high
fre0uency so it will #ecome
irrelevant (very difficult to cancel
out& may need to reduce
#andwidth significantly)%
+ompare with 3uc? +hanges are in 7>;
++M

)igure ." -lant Transfer #unction for a <oost$ Csing ?%'

Buck7Boost
&ESR ' (##ESR$HC$
&0'()#LC$
&0%'R(L
FSQ Bero
"' double 1ole
divided by !1(D&
*
&*
&ESR
*A log
!?I58U?Q0%- !1(D&
*
V
*A log
!fre7uency&
changes with input --- line
feedforward feature too
complicated to implement)
><7 Dero? :he ><7 of a cap has
a
i
n
-eaking of "' 1ole
( ) ( )

+ +

=

+ + +

R+P R+P
2
ESR ESR IN IN
2 2
RAMP RAMP
0
2
0 0
s s

D
s s
D

! !
"#s$
! !
s s s

%
&R+P'R(#DHL$ Qight Ealf -lane Bero
&R+P
78P Dero? Needs to #e canceled
or moved out to a very high
fre0uency so it will #ecome
irrelevant (very difficult to cancel
out& may need to reduce
#andwidth significantly)%
+ompare with 3oost? +hange is in BLUE
+ompare with 3uc? +hanges are in 7>;
++M

)igure /" -lant Transfer #unction for a <uck(<oost$ Csing ?%'

+

=
ESR
MAP
o
s
"
R
R
#s$
Buck
3Plant 4ain, 43s5 in CMC5
&ESR ' (##ESR$HC$
&0'(#RC$
FSQ Bero
=ut1ut "oad 1ole
&*
&ESR
*A log
!Q8Q%0-&
*A log
!fre7uency& :his ;+ gain of plant does not vary
with input voltage in current mode
control% <o& loop response is steady
with respect to input. (t is also
proportional to 7& i%e% inversely
proportional to load current%
*nfortunately& DC gain does tend to
fall at high load currents.
time (aging)% (n +M+ however&
it must #e either canceled (#y
a pole in the compensator)& or
moved out to a very high
fre0uency& so that it #ecomes
irrelevant
Output load pole% Single pole&
no peaking. (ts location is
inversely proportional to 7& so
it is proportional to load
current % ;+ gain is inversely
<o crossover frequency
!andwidth" is unchanged as
load changes dashed line"
a
i
n
=t light
loads
RMAP is the tra,sresista,ce ---- the
PWM ramp volta.e divided /0 the
correspo,di,. se,sed c1rre,t
++M
+ompare with 5M+? +hanges in BLUE
Sim1lified4 Subharmonic Instability8-ole not shown !for ''% and DW)AX&

)igure 0" -lant Transfer #unction for a <uck$ Csing '%'


( )

+

MAP
o
R R+P ES
s
R
R s
D
2
s
"#s$
Boost
&ESR ' (##ESR$HC$
&0'2(#RC$
FSQ Bero
=ut1ut "oad 1ole
&*
&ESR
*A log
!Q!1(D&8*Q%0-&
*A log
!fre7uency&
irrelevant
<o crossover fre0uency
(#andwidth) is unchanged as
load changes (dashed line)
a
i
n
=t light
loads
RMAP is the tra,sresista,ce ---- the
++M
+ompare with 3*+E? +hanges in 7>;
&
R+P
'R(L Qight Ealf -lane Bero
divided by !1(D&
*
.(HP
78P Dero? 5ery hard
to cancel% May need
to reduce #andwidth
to eep 78P 9ero at
very high fre0uency&
to mae it irrelevant
:his ;+ gain of plant does vary with
input voltage% <o& loop response is not
steady with respect to input. (t is
also proportional to 7& i%e% inversely

)igure 1" -lant Transfer #unction for a <oost$ Csing '%'
( )

+

+
+

=
ESR
o
P
MAP
R+
s
"#s
R D
R s
s
$
# D$
Buck7Boost
&ESR ' (##ESR$HC$
&0'(/0%)(#RC$
FSQ Bero
=ut1ut "oad 1ole
&*
&ESR
*A log
!fre7uency&
irrelevant
<o crossover fre0uency
(#andwidth) is unchanged as
load changes (dashed line)
a
i
n
=t light
loads
R
MAP
is the tra,sresista,ce ---- the
++M
+ompare with 3*+E? +hanges in 7>;
&
R+P
'R(#%HL$ Qight Ealf -lane Bero
divided by !1(D&
*
+ompare with 3OO<:? +hanges in #$EE%
.(HP
78P Dero? 5ery hard
to cancel% May need
to reduce #andwidth
to eep 78P 9ero at
very high fre0uency&
to mae it irrelevant
*A log
!Q!1(D&
8U389(5Q%0-&V
:his ;+ gain of plant does vary with
input voltage% <o& loop response is
not steady with respect to input. (t
is also proportional to 7& i%e% inversely

)igure 2" -lant Transfer #unction for a <uck(<oost$ Csing '%'


Subharmonic Instabilit in CMC
The model we used for the '%' figures was very sim1lified. .e ignored something that is actually very relevant to
understanding the practical limits of '%'. The 1henomena of su#harmonic insta#ility in '%' is well(known and re1resents one
of the most ma9or drawbacks of '%'$ one that can easily force us into setting a much lower bandwidth for '%' than we had
thought initially !based on incom1lete models or by reading very early$ and rather o1timistic$ Cnitrode 011 5otes&.
0 converter already in the midst of this 1articular !subharmonic& instability will usually show no outwardly sym1toms of
anything amiss at all$ es1ecially in steady state. <ut under sudden line or load disturbances$ we will notice highly im1aired and
sluggish loo1 res1onse. The <ode 1lot will not look com1rehensible. If we connect a sco1e to the switching node$ we will see a
1attern of one wide 1ulse !almost ma; duty cycle& followed by a very thin 1ulse !almost min duty cycle&. 5ow$ the re1etition
fre7uency of this 1attern is not the switching fre7uency$ but half the switching fre7uency !two 1ulses in every re1eating
1attern&. Therefore$ subharmonic instability is often called ,half(switching fre7uency !or fsw8*& instability/.

!ote" 0ll cases of one wide 1ulse followed by one narrow 1ulse are not necessarily related to subharmonic instability of the ty1e
under discussion here. The same 1attern can be caused by a leading edge noise s1ike$ causing early termination of one 1ulse
which is then automatically followed u1 by the loo1 as one !or two& wider ,make(u1/ 1ulses.

!ote" Qe1eating 1atterns of three !or more& 1ulses are most likely noise artifacts or traditional instability$ not subharmonic
instability.

.ell before a system actually enters this irrecoverable subharmonic instability state$ we can ask what are the symptoms$ or
signs$ of impending subharmonic instabilityG <ecause if we recogniBe that$ 1erha1s we can avoid subharmonic instability #efore
it ha11ens.

To answer that$ first of all we must remember that subharmonic instability is entered only in continuous conduction mode
!''%& at duty cycles greater than A.)$ and of course only when using current(mode control !'%'&.

<eing forever ,1ractical/$ letJs su11ose we take the <ode 1lot of any current mode controlled converter one that has not yet
entered this wide(narrow(wide(narrow state. .e will discover a mysterious peaing in the gain 1lot at e;actly half the switching
fre0uency !very similar to the gain 1eaking for ?%' at the "' double 1ole$ see
!igure -&. This is the ,source/ or origin of future subharmonic instability. Subharmonic instability is therefore nowadays
modeled as a comple$ pole at half the switching fre0uency. Yuite like the "' double 1ole of ?%'$ it too has a certain Y !Yuality
#actor&$ or ,1eaking/ that we need to limit.
5ote that based on sam1ling theory$ we never try to set the crossover fre7uency !loo1 bandwidth& higher than half the switching
fre7uency. So in effect$ this subharmonic 1ole will always occur at a fre7uency greater than the crossover fre7uency. <ut it could
in fact be uncomforta#ly close to the crossover fre7uency$ es1ecially if we try to 1ush the crossover fre7uency !bandwidth&
higher and higher$ going from$ say$ 186
th
to 182
rd
the switching fre7uency. This half(switching fre7uency 1ole is ominous because
of the fact that if it 1eaks too much it can end up causing the gain 1lot to intersect the Ad< a;is once again$ 9ust 1ast its actual
!first& crossover 1oint. Fven though this is an unintended crossover$ any 1hase reinforcement at any crossover 1oint can
1rovoke full instability. 0 system will then 7uickly transgress and settle down into an irrecovera#le alternate pulsing !fsw8*&
1attern. <ut if we are not so aggressive in our bandwidth goals$ we are much better 1oised to see only minimum effects coming
from this fsw8* 1ole. 3ee1 in mind however$ that the effect of this 1ole on the phase angle may start at a much lower fre0uency.
The subharmonic instability 1ole has a certain ,Y/ that we can calculate.$ It has been shown by actual e;1eriments that a Y of less
than 2 usually allows stable conditions. 0 Y of 1 is 1referred by conservative designers$ and though that choice does 7uell

subharmonic instability even more firmly than YK*$ it does lead to a #igger inductor$ and often to a rather non(o1timum inductor
current ri11le ratio !SI8I& ((( of less than Z*AX. 0lternatively$ we need to a11ly greater ,slo1e com1ensation/. <ut too much

slo1e com1ensation is akin to making the system more and more like ?%'$ and 1retty soon$ es1ecially at light loads$ the double
"' 1ole of voltage mode control will rea11ear 1otentially causing instability of its own !since we didn:t 1lan for it&.
To kee1 the Y of this subharmonic 1ole to less than *$ we need to set the inductance of the converter to higher than a minimum
value. The e7uations for that are

+ IN
A( s
D 0234
L ! #51c6$
Slope Comp

+ *
A( s
D 0234
L ! #5oost$
Slope Comp

( )
+
+ IN *
A( s
D 0234
L ! ! #51c6-5oost$
Slope Comp

So basically$ with '%'$ we may need to do one or more of the following4

a& 0dd slo1e com1ensation !but not so much that we 9ust get un1lanned(for ?%'&
b& Increase the Inductance !1er the limits 1resented above&
c& Qeduce loo1 bandwidth !almost down to the conservative e;1ectations for ?%'&

Conclusions on CMC %ersus 6MC
We have reali9ed that when we tae a closer loo& +M+ and 5M+ are 4ust alternative ways of achieving loop sta#ility% :he type of
compensation scheme we need may #e simpler for +M+ (:ype 2) than for 5M+ (:ype ,)% 3ut then& +M+ also needs slope
compensation& and so on% Pros and +ons as usual%

'%' also suffers from high -'< sensitivity$ since we usually de1end on a small sensed current to generate the voltage ram1
a11lied to the -.% com1arator. Since a lot of noise is generated when the switch turns =5$ we usually need to introduce a
,blanking time/ to avoid triggering the com1arator for at least )A(*AAns after the switch turns =5. This unfortunately leads to
indirectly establishing a minimum =5(time 1ulse width of also )A(*AAns$ and the corres1onding minimum duty cycle can 1lay
havoc with high(voltage to very low(voltage down(conversion ratios$ es1ecially with high switching fre7uencies. In com1arison$
?%' is inherently more robust and noise(resistant.

= modern preference seems to #e in the direction of 5M+ with 6ine !eedforward& 4ust as 3o# Mammano implicitly predicted in ;N-
F2% 3ut another recently emerging ma4or thrust is actually heading towards hysteretic control& as we will shortly see%
In closing$ we 1resent an overview of com1ensator design strategies in
!igure :.


V
REF
V
O
V
REF
V
O
V
REF
V
O
Type 3
Type 2
Type 1
+
-
+
-
+
-
Set both at
LC pole
Set at ESR
zero
Typically set to
fsw/2, fsw, fcross
or 10x fcross
Set at LC
pole
Current Mode
Control : Set
at ESR zero
!i-+li,ied Trans,er &unction +lots o, &eed1ac2 !tages (Co-+ensators)
Voltage Mode Control :
Typically set to fsw/2,
fsw, fcross or 10x fcross
#ll ha3e a Pole at 4ero (Integrator)
2 Poles 0 2 4eros
/ Pole 0 / 4ero
G
a
i
n

(
d
b
)
Frequency (log scale)
G
a
i
n

(
d
b
)
G
a
i
n

(
d
b
)
!
C*N7
!
C*N7
!
C*N7


)igure :" =verview of 'om1ensator Design for ?%' and '%'

;steretic Control" <nerg on (emand
"ooking at !igure " again$ we see that the basic way a -.% com1arator works is by creating =5(=## 1ulses from the
intersection of two voltage 1rofiles at its in1ut terminals4 one steady voltage level !the control voltage&$ and another sawtooth
voltage 1rofile !ram1ing u1 and down&. .e can well ask why not a11lying the reference voltage directly as the ,smooth/ voltage
level !instead of the error voltage& on the other terminal$ and use a sawtooth based on the inductor current !as in '%'&G This is
shown in !igure "/ and in
!igure 88% 5ote that as shown in
!igure 8+$ this is not really a ,-.% com1arator/ anymore$ at least not in the sense we were used to so far. It is now a ,hysteretic
com1arator/ that terminates the =5(1ulse if the ram1 voltage e;ceeds the reference voltage by a certain amount Sv !,SE[S8*/&$
and turns the switch back =5 when the ram1 falls below a certain threshold slightly lower than the reference voltage !(Sv&. It is
therefore often called a ,bang(bang/ regulator. If there is a sudden line or load transient$ it can react by either turning =##
com1letely for several 1ulses in succession$ or by turning =5 fully. Therefore its transient res1onse is e;cellent ,Fnergy on
Demand/ in effect. =r ,Fnergie vom #a\/ as the ermans would 1erha1s like to call it.

Farly forms of bang(bang regulators have e;isted for decades$ based on S'Qs !silicon controlled rectifiers& or bi1olar transistors$
but without inductors. This ancient techni7ue has been literally re(invented in modern switching 1ower conversion$ and offers
tremendous advantages as can be confirmed on the bench. The bandwidth of the loo1 res1onse is close to the switching
fre7uency itself. There is no feedback or com1ensator to design$ nor 1oles and Beros to mani1ulate. <ut the mathematical models
of hysteretic controllers are still very com1licated and 9ust evolving. This however has not sto11ed designers from trying to eke
out the full commercial advantage of hysteretic control. =ne of the biggest advantages is that because there is no clock and no
error am1lifier$ nor any com1ensation circuitry$ the 7uiescent current !IY$ Bero load$ but still switching&$ is very low !ty1ically
less than 1AA]0&. This makes the hysteretic converter very suitable for modern battery(1owered a11lications in 1articular. In
the world of cell 1hones and tablets$ hysteretic has started leading the way.

Eysteretic control does have its limitations. <ecause there is no formal clock$ it is hard to assure constant fre7uency. There can
also be a lot of erratic 1ulsing$ usually accom1anied by unacce1table audio noise !s7uealing&$ and also un1redictable F%I !and
audio&. The way to avoid erratic 1ulsing is to ensure the ram1 waveform a11lied to the hysteretic com1arator is an e;act re1lica
of the actual inductor current. This way we get a chicken and egg situation where the duty cycle created #y the comparator is
e$actly what the system naturally demands under the given line and load conditions. Then there are no missed 1ulses accom1anied
by audible low(fre7uency harmonics. The way to ad9ust the fre7uency to an acce1table constant level is by symmetrical variation
of the com1arator thresholds$ as indicated in
!igure 8+. If we do not do this ,symmetrically/$ there will be a resultant D' offset$ causing a drift or off(centering in the out1ut
voltage.

0nother way to try obtaining hysteretic control with almost constant fre7uency is to use a ,'=T/ !constant =5(time controller&.
.e know that !for a <uck&4

=5 =
=5
I5
T ?
D T f
T ?
= = =
Therefore

( )
=
I5 =5
?
f
? T
=

In other words$ if we fi; the =5(time of the hysteretic converter$ but also make that =5(time inversely 1ro1ortional to the in1ut$
we will get a constant ,f/. That is the underlying 1rinci1le of the '=T !<uck& converter. 5ote that the '=T converter has a 1re(

ordained =5(time$ so there is no u11er com1arator threshold re7uired anymore. <ut for the same reason$ we can ger some D'
offset here.

In the case of a very(high(voltage to low(voltage conversion !like +@? to 2.2?&$ we know that in traditional converters we get
rather limited by the minimum !1ractical& 1ulse width of the converter$ es1ecially in the case of '%' !due to the blanking time
issue as discussed earlier&. <ut in the '=T <uck$ by fi;ing the minimum =5(time$ we in effect not only lower the fre7uency$ but
also achieve smooth down(conversion without any une;1ected overshoots during line and load transients as in traditional
control methods.

In a similar manner it can be shown that a constant O!!(time will give a constant fre7uency when a11lied to a 3oost. .eJll
remind ourselves once more of the intuitive reason for the QE- Bero4 under a sudden load demand the out1ut di1s momentarily
and therefore the duty cycle increases. <ut in the 1rocess$ the =##(time decreases. Since in a <oost !and <uck(<oost& energy is
delivered to the out1ut only during the =##(time$ a smaller =##(time leaves less time for the new energy re7uirement to be met$
which tem1orarily causes the out1ut to di1 even further before things get back to normal. So we intuitively realiBe that fi;ing a
certain minimum =##(time will hel1 in this case. 0nd that is in fact true4 the 78P 9ero is not present when operating the 3oost in
constant off-time mode. 0nd we can get constant(fre7uency o1eration too$ by setting T=## ?I5.

#or a <uck(<oost$ the relationshi1 for achieving constant fre7uency is too com1licated to im1lement easily$ without sacrificing
the key advantages of hysteretic controllers4 sim1licity and low IY. So we will go 1ast this roadblock.

Autotuning

5owadays$ system houses want the fle;ibility$ not only of voltage margining via I
*
' control$ but also the ability to change
switching fre7uencies$ say$ over a ty1ical Z)AX range. The idea is to be able to avoid certain fre7uencies after a 1re(release
F%I8audio scan. In general$ beat fre7uencies also need to be avoided in cases of multi1le free(running regulators switching at a
fre7uency fairly close to each other. It may be too late to return to the drawing board and start changing com1onents only to find
that line8load transient res1onse has been affected. So the conce1t of autotuning is gaining ground. Design houses are s1ending
a lot of time starting out with '%' or ?%' and learning to re(1osition the 1oles and Beros automatically in case the fre7uency is
changed. Eysteretic control$ in 1articular '=T$ offers the advantage of having no traditional loo1 com1ensation com1onents.
<eing ,energy on demand/$ it has inherent autotuning ca1abilities. %icrosemi:s future hysteretic controllers are thus being
designed to 1rovide effective su11ort for autotuning features. In contrast$ digital methods tend to create a large IY and silicon
area re7uirement.

Microsemi Pro'rietar ;steretic Control

%icrosemi has a 1ro1rietary hysteretic engine that creates an artificial ramp that mimics the inductor current$ to hel1 overcome
-'< layout sensitivity issues. It also changes the hysteretic thresholds symmetrically to achieve constant fre0uency with no ;+
offset. In !igure ", we have 1resented the %icrosemi hysteretic 1arts currently available$ or in the 1rocess. -lease contact your
s1ecific region:s %icrosemi sales re1resentative for more information.


&his concludes a !rief summary of the pros and cons of hysteretic control. See &a!le ' for a summary of pros and cons of
the various control methods.

SWITCH
{{
VO
FILTER
{
VIN
POWER STAGE
Feedback trace
D
r
i
v
e
r

n
o
t

s
h
o
w
n
VREF
Divider
(Sensor)
{
OUTPUT
LINE
REFERENCE
Rf2
Rf1
Hysteretic
Comparator
OUTPUT
INPUT
(LINE)
FB pin
EA OUT/
Control Voltage /
COMP pin
Divider
+0steretic
Comparator Switch LC Post Filter
Equivalent
Rf2
Rf1
VIN
-
+
-
+
VREF
REFERENCE
;=S,<R<,IC C#!,R#&" !# )#RMA& P&A!,, !# C#MP<!SA,#R
C
O
N
T
R
O
L

S
E
C
T
I
O
N

)igure 8>" #unctional <locks of the Eysteretic 'onverter

V
IN
VREF
-
+
+
-
VIN
RAMP
'ontrol ?oltage =ut1ut Qi11le V
O
V
O
VREF
+
-
,raditional 6MC ;steretic

)igure 88" <asic 'hanges to 0chieve Eysteretic 'ontrol


+
-
!re8
Io
9I(2
9I(2
Vre,
!
o
l
t
a
.
e

o
,

F
e
e
d
/
a
c
6

P
i
,
time
9+:S(2
9+:S(2
Vre,
!
o
l
t
a
.
e

o
,

F
e
e
d
/
a
c
6

P
i
,
time
59+:S(2
9+:S(2 5
C+AN"E 5*7+ +:S7ERESIS
7+RES+*LDS S:MME7RICALL:
Fre;1e,c0 ca, /e cha,.ed<
I
,
d
1
c
t
o
r

C
1
r
r
e
,
t
time
F5
00pF
+
-
=>6
+
-
323,F
222?F
With low-ESR caps@
add a 8eed-8orward
capacitor o8 t0picall0
00pF to i,crease
the volta.e ripple o,
the 8eed/ac6 pi,2
Ca, com/i,e with
a/ove tech,i;1e2
Arti8iciall0 .e,erate
a, AESR rampB /0 the
same method 1sed
8or DCR se,si,.@ a,d
AC co1ple this ripple
o, top o8 the DC
8eed/ac6 level@ a,d
appl0 that to
8eed/ac6 pi,2
Techni6ues to 'nhance (i++le
+
-
C
With low-ESR caps@
add t0picall0 C
resistor to i,crease
volta.e ripple2 Ca,
com/i,e with
tech,i;1e
immediatel0 /elow2
Hysteretic 7uc2 '8+lained

)igure 8+" Eysteretic 'ontrol F;1lained in a Sim1lified manner


)igure 8-" Eysteretic Switcher offerings from %icrosemi


Summar of Pros and Cons of the (ifferent Control ,echni*ues
CMC 6MC ;steretic
7e4ection of 6ine
;istur#ances
(;ynamic 6ine
response)
ood !Inherent& ?ery ood !with
"ine #eedforward
F;cellent
!Inherent&
7e4ection of 6oad
;istur#ances
(;ynamic 6oad
response)
ood !'onstant
<andwidth&

ood F;cellent
!Inherent&
+onstant
!re0uency
F;cellent F;cellent -oor$ need to vary
hysteresis band$ =Q use
'onstant =5(time
!<uck&$ =Q use 'onstant
=##(time !<oost&
Predicta#le >M(
F;cellent F;cellent =3 !with above '=T
techni7ues&
=udi#le Noise
<uppression
F;cellent F;cellent =3 !with above '=T
techni7ues&
>$treme ;own
+onversion
(3uc)
-oor ood F;cellent$ with '=T
techni7ues
(nsensitivity to
P+3 6ayout
-oor F;cellent ood$ with 0rtificial
Qam1 eneration$
otherwise 1oor
>$cellent <ta#ility
of 6oop 7esponses
(:olerances and
6ong-term ;rifts)
F;cellent ood #air
<implicity of
+ompensation
ood -oor F;cellent
(A (Auiescent
+urrent)
ood -oor F;cellent
6oop <ta#ility
with use of
Output +eramic
+aps
F;cellent
!with Ty1e 2
com1ensation&
?ery ood ood$ with 0rtificial
Qam1 eneration$
otherwise 1oor
=utotuning
'om1le; ?ery 'om1le; Inherent

Table 1: Summary (Voltage Mode versus Current Mode versus Hysteretic Control)


(e3ision History

Revisio, Level (
Date
Para2 A88ected Descriptio,
023 ( 0D-E1l0-202 -
024(D-E1l0-202 Added Fi.1re 3 Descriptio, o8 A1tot1,i,. a,d Microsemi
+0steretic ICs
02>(2D-E1l0-202 A1tot1,i,.(7a/le 7a/le has a, added row
02=(2D-Nove-202 New Format New Format

9 20/2 Microse-i Cor+:
#ll rights reser3ed:

For s1pport co,tact< sales;#M!"<-icrose-i:co-
!isit o1r we/ site at< ===:-icrose-i:co- Catalogue Nu-1er< %C%C;TN;203

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Rev. 0.6, Nov 2012 Analog Mixed Signal Group

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