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800 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO.

L PROCESSING, VOL. 45, NO. 7, JULY 1998

A Low-Voltage Low-Power Wide-Range


CMOS Variable Gain Amplifier
Ali Motamed, Changku Hwang, Senior Member, IEEE, and Mohammed Ismail, Fellow, IEEE

Abstract—In this paper, a compact low-power (LP) low-voltage is mainly due to the square-root dependency of the differential
(LV) metal–oxide–semiconductor-only (MOS-only) variable gain pair transconductance on the bias current. For instance, in
amplifier (VGA) is introduced. This amplifier based on comple- order to achieve a 30-dB gain variation, the differential-
mentary MOS (CMOS) transistors operating in strong inversion
is composed of a pseudo-exponential current-to-voltage converter, pair bias current must be varied in the range of 1x–1000x.
analog multiplier, and output stage. The gain of the ampli- Some designs attempt to avoid large-bias current variation
fier is controlled exponentially by a novel wide-range pseudo- by using two or more differential pairs in cascade; resulting
exponential current-to-voltage converter implemented with two in smaller required gain variation range per stage. A more
back-to-back connected current mirrors exhibiting superb expo- serious drawback of the differential pair is its rather limited
nential characteristic. Also, a new LV/LP composite transistor is
introduced to increase the input dynamic range of the multiplier. input voltage range. Unfortunately, cascading differential pairs
The amplifier is fabricated using a 2-m MOSIS n-well process, has an adverse effect in that the subsequent differential pairs
and its simulation and measurement results are shown in detail. may have to experience increasing levels of signal amplitudes.
It can be shown that the maximum-input differential voltage
which can be applied to an nMOS or pMOS differential pair
I. INTRODUCTION
without severe distortion is limited to a few tenths of a volt

A LTHOUGH lower supply voltage directly translates to


lower power consumption in digital circuits, a similar
conclusion cannot necessarily be drawn for analog circuits.
and is given by [7]

(1)
Therefore, low-power (LP) analog design raises its own chal-
lenges that should be met under the constraints of low-voltage
(LV) design. Furthermore, in the era of mixed-mode integrated where is the differential-pair bias current. Alternatively,
circuits, the design of analog circuits should be carried out and as we will see in this paper, an analog multiplier can
in the presence of noisy digital circuits with a technology be designed to circumvent the above problems and operate
optimized not for analog, but for digital circuits [1]–[3]. as a LV ( 3) VGA with a much larger input voltage range
This is one reason why analog integrated circuits with wide and a large gain control range achieved at significantly lower
dynamic range have gained so much attention in recent years, power consumption levels. In general, the output current of a
particularly for LV LP applications [4]–[6]. four-quadrant analog multiplier can be expressed as
In this paper, we introduce a compact LV and LP variable
gain amplifier (VGA) with wide dynamic range, which can (2)
be found in numerous applications in communication systems
where is a constant with units [A/V ]. If required, a resistor
and audio/video analog signal-processing circuits. The voltage
or a transresistor element can be used at the output to convert
gain or the transconductance of the VGA can be varied by a
the output current signal into a voltage signal.
control voltage or current. In most existing strong-inversion
A VGA with an exponential-gain control characteristic
metal–oxide–semiconductor (MOS) designs, a variable gain
is desired in applications where wide-gain control range is
is achieved by controlling the bias current of a differential
required; i.e., the gain should increase monotonically on a
pair. However, this approach is not well suited for applications
decibel scale with linear increments in gain control signal (i.e.,
where wide-gain variation is required at LV and LP levels. This
decibel linear). To fulfill this need, a new complementary-
Manuscript received June 17, 1997. This paper was supported by the Video MOS-only (CMOS-only) pseudo-exponential voltage genera-
Camera LSI Section, the Bipolar/CCD Division of Sony Corporation, Atsugi, tor is designed to map the input gain control signal (which
Japan, and by Micrys Inc., Columbus, OH. This paper was recommended by could be current or voltage) into a corresponding exponential
Associate Editor N. Nguyen.
A. Motamed was with the Analog VLSI Laboratory, Ohio State University, voltage. Section II describes such a voltage generator. Fig. 1
Columbus, OH 43210 USA. He is now with Exar Corporation, Fremont, CA shows how an analog multiplier can be used as a VGA.
94538 USA. The input signal is differentially applied to one pair of input
C. Hwang was with the Analog VLSI Laboratory, Ohio State University,
Columbus, OH 43210 USA. He is now with the Communication Systems terminals, labeled and , and the exponential voltage is
Research Department, Hitachi Central Research Laboratory, Tokyo 185, Japan. applied to the second pair of terminals, labeled and . The
M. Ismail is with the Analog VLSI Laboratory, Solid-State Microelectronics output current of the multiplier, which is proportional to the
Laboratory, Department of Electrical Engineering, Ohio State University,
Columbus, OH 43210 USA. product of the two input differential voltages, i.e.
Publisher Item Identifier S 1057-7130(98)05056-3. and , can subsequently be converted into a
1057–7130/98$10.00  1998 IEEE

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MOTAMED et al.: LV LP WIDE-RANGE CMOS VGA 801

(a)

Fig. 1. Block diagram of a VGA with exponential-gain control using an


analog multiplier.

voltage using a simple resistive load or a gain stage with


proper transresistance. A key feature here in achieving very
low power is the fact that the dc-bias current is fixed, i.e., not
used in gain control.
However, the input voltage range is often limited in analog
multiplier circuits, particularly under low-supply conditions.
To further extend the input voltage range, a new LV composite
transistor is introduced in Section III and used in the design
of the multiplier and VGA in Section IV. This new VGA can
achieve wide-input voltage range and LP consumption as well
as LV operation (3 V or less depending on bias current levels
and the VLSI technology used). Minimum supply levels are
discussed. Noise analysis of the VGA is also given in the
Appendix. (b)
Fig. 2. (a) Back-to-back connection of two 1:1 current mirrors. (b)
II. EXPONENTIAL CURRENT-TO-VOLTAGE CONVERTER exp(2ny ) with n = 1 and n = 2 and f (y ) with n = 1 and 2 as a
function of y . This figure also shows the regions where the error is less than
In this section, the design of a new current-to-voltage 2% and 5% when n = 2.
converter with exponential characteristics [8], [9] is described.
This converter, as shown in the block diagram of Fig. 1, is Substituting (4) into (3) yields
responsible for generating an exponential voltage to control
the gain of the VGA. Here, the input control signal is assumed
to be a current. However, as we will see shortly, due to
the constant input resistance of the converter, a voltage-gain (5)
control signal can be used as well.
There is no intrinsic logarithmic device in strong inversion
CMOS technology. One possibility is to generate the required
(6)
exponential characteristic using parasitic bipolar devices [10].
Alternatively, a new pseudo-exponential voltage generator is The ratio of the two currents and can be written as
introduced in this section. This very compact and power-
efficient sub-circuit offers a superb exponential characteristic. (7)
Let us examine the circuit shown in Fig. 2(a), which is
a back-to-back connection of two current mirrors. The gain where , , and .
control signal is a bidirectional current with positive The function is a close approximation of the expo-
direction chosen to be outward. Assuming nential function . Fig. 2(b) shows with
, we have [11] and and with and on
semilogarithmic coordinates, and defines the range where the
(3) approximation with holds within less than 2% and 5%
error. Note that a larger yields a larger control range for .
Using the fact that , we obtain Fig. 3(a) shows the simulated currents and in Fig. 2(a)
as a function of the control current . As stated previously,
(4) can assume both positive and negative values. Fig. 3(b)
depicts the ratio as is varied from 30 to 30 A.

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802 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 7, JULY 1998

close to 30-dB control voltage range. This figure also depicts


variations of the output voltage with temperature. In the
(a) temperature range of 25 C–75 C, the output exhibits about
1.7-dB maximum variation from the nominal value at 25
C. Note that the minimum supply voltage under which the
circuit operates properly is . Device sizes of the
input current mirrors should be large enough to accommodate
(b) voltage variations caused by changes in the control current .

III. LV CMOS COMPOSITE TRANSISTOR


The high equivalent threshold voltage
of the simple square-law CMOS-pair composite transistor [12],
(c) [13], shown in Fig. 7(a), can limit its application in LV analog
circuit design. This section introduces a new LV (low- )
square-law composite transistor with improved input voltage
range. While capable of operating at lower supply voltages,
Fig. 3. (a) Simulated currents I1 and I2 of the circuit of Fig. 2(a) with the new device shares the most important feature of the
= =
Kn Kp 71 (A/V2 ). (b) The ratio I1 =I2 . (c) The ratio I1 =I2 expressed simple composite transistor, i.e., offering two high-impedance
in decibels.
terminals to control the current through the device.
A folded structure is used to decrease the required turn-on
The accuracy of the approximation is shown more clearly by voltage of the composite transistor. This concept is depicted in
plotting the graph on a semilogarithmic scale, as depicted in Fig. 7(b). A simple level shifter is added between the sources
Fig. 3(c), which shows a control range of 40 dB. of the two transistors. The voltage gain of the level shifter
The two current mirrors of Fig. 2(a) have another interesting is ideally assumed to be one. If the level shifter shifts the
characteristic, as revealed by (4), which is a constant linear voltage by , then the new composite device operates when
resistance at the input terminal. The resistance can simply be and thereby extends the operating
found by examining (4) and can be expressed as region of the composite transistor by the same amount. The
nMOS and pMOS transistors in the composite CMOS pair
(8) [see Fig. 7(a)] share the same current. To reconstruct the same
condition, a current mirror is added to redirect the drain current
The negative sign in (4) appears because the positive direction of the nMOS transistor to the source of the pMOS transistor
of is chosen to be outward, as shown in Fig. 2(a). A and guarantees equal currents flowing through the nMOS and
constant input resistance implies that the circuit is responsive pMOS transistors, maintaining the operation of the original
to a gain control voltage as well as a gain control composite transistor of Fig. 7(a).
current. This property is useful if the gain control signal is The circuit implementation of the modified composite tran-
in voltage form. Fig. 4(a) shows the simulated input volt- sistor, suitable for LV applications, is shown in Fig. 7(c). A
age–current characteristics of this circuit where the slope of simple-source follower stage with a current source load is used
the line represents the input conductance. Note that should to shift the voltage at the source of by almost and
vary from almost 1.2 to 1.9 V in order to obtain the same feeds it to the source of . A more rigorous analysis of the
effect as sweeping from 30 to 30 A. The measured circuit is given below.
voltage–current characteristic is shown in Fig. 4(b).
Fig. 5 shows the complete circuit diagram of the pseudo-
A. Analysis of the LV Composite Transistor
exponential voltage generator. The current mirror – is
used to direct the current to the drains of and .A Using the square-law model of a MOS transistor, the
constant resistance, similar to in (8), is seen at the common currents through , shown in Fig. 7(c), are written as
drain node of the two diode connected transistors and ,
which is also the gate of . It converts the current to a (10)
voltage , which can be expressed by (4) with replaced
by . Transistor operates in the triode region and acts as (11)
a voltage-controlled resistor. For small drain–source voltages,
the resistance exhibited by is given by (12)

(9) Equations (10)–(12) can be rewritten in the form of

Hence, flows through and generates a drain–source (13)


voltage proportional to . Fig. 6 shows
the simulated and measured drain–source voltage of using (14)
both linear and logarithmic scales versus , which shows

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MOTAMED et al.: LV LP WIDE-RANGE CMOS VGA 803

(a) (b)
Fig. 4. Input voltage–current characteristic of the circuit shown in Fig. 2(a). (a) Simulation. (b) Measurement.

Fig. 5. The complete circuit diagram of the pseudo-exponential voltage generator.

(a)

(b)

Fig. 6. The simulated output voltage Vds of the pseudo-exponential voltage generator. (a) Linear scale. (b) Logarithmic scale.

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804 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 7, JULY 1998

(a) (b)

(a)

(c)
Fig. 7. The modified low-VT square-law composite transistor. (a) Composite
square-law CMOS [12] transistor pair. (b) Design concept of the modified tran-
sistor. (c) Circuit implementation of the new low-VT square-law composite
transistor.

(b)
Fig. 8. Drain current of the LV composite transistor as a function of the
(15) gate–source voltage. (a) Simulation. (b) Measurement.

Using the fact that and ,


of (17) are shown in Fig. 9(a). This figure further justifies
we can write
the assumption made in driving (17). Fig. 9(b) shows the
frequency characteristic of the drain current for four different
(16) values of gate-to-source voltage.

where . In the case where , IV. THE VGA


the above equation can be simplified and written in the In Section III, a new LV square-law composite transistor
conventional form of was introduced. A well-known technique for designing CMOS
four-quadrant analog multipliers is based on the square-law
(17) characteristics of a MOS transistor. One possibility is to use
four cross-coupled square-law MOS transistors to build the
with the equivalent threshold voltage defined as multiplier [14], [15] with an output current given by (2). In this
. section, we use four LV composite transistors to implement a
Note that can be reduced by increasing , i.e., multiplier, as shown in Fig. 10(a), where and act as
at the expense of increased dc power consumption. The input terminals of the VGA and and are connected to
conditions for operation in the saturation region are of Fig. 5 and are acting as the gain control terminals of
and , the VGA. The output current of the VGA ( ) is obtained by
where and denote saturation voltages of evaluating and follows (2) with .
the current source and , respectively. Fig. 8(a) shows the Fig. 10(b) shows the die photograph of the VGA implemented
simulated drain current of the new LV composite transistor as in a 2- m CMOS MOSIS process.
a function of gate and source voltages, while Fig. 8(b) shows Fig. 11(a) shows the input voltage range of the multiplier
the measured results. in three dimensions, with its top view shown in (b). For a
The measured drain current of the LV composite transistor symmetric operation, i.e., , the common
along with simulated drain current and numerical evaluations mode voltage of , and , is set to 2.5 and 0.5 V,

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MOTAMED et al.: LV LP WIDE-RANGE CMOS VGA 805

varied in such a way as to maintain at a certain constant


level (usually at maximum) as the input voltage changes.
Therefore, we can write
(19)
and
(20)

combining (19) and (20) yields


(21)

This shows that as the input voltage decreases, increases.


This situation can also be interpreted as follows: a large control
voltage (large gain) implies a small input voltage and vice
versa. This observation leads to the tapered region of operation
shown in Fig. 13.
Comparison of Fig. 11(b) with Fig. 13 reveals that this
characteristic of the VGA allows more efficient utilization
of the operating region and can enhance the maximum input
differential voltage range. In fact, an input differential voltage
as high as 2 V is attainable.
(a) Fig. 14(a) shows the overall transconductance of the VGA
defined as as a function of the gain control current .
The transconductance of the VGA can vary by as much as
30 dB as varies between 30 and 30 A. The measured
transconductance of the VGA is shown in Fig. 14(b).
The maximum required input voltage determines the
minimum supply voltage under which the multiplier functions
properly. This can be determined as follows:

(22)
and
(23)

using the equal sign in (22) and (23), we write

(24)
and
(25)

Subtracting (24) and (25), we get


(b) (26)
Fig. 9. Drain current of the LV composite transistor as a function of: (a)
Vgs and (b) frequency. The output stage of the VGA raises certain challenges which
are different from those encountered in the design of output
stages in the operational amplifier (Op Amp). This is because
respectively, for 3-V supply voltage. This corresponds to the overall closed-loop gain of an Op-Amp circuit is usually
a maximum differential input of 1 V for both and set by the external feedback loop. The situation for the VGA
. Fig. 12 depicts the dc transfer characteristics for this output stage is totally different. The VGA output stage should
symmetric operation. possess high and precise transresistance without compromising
Although symmetric operation might be required for analog the frequency response. A very high impedance node at the
multipliers, it is usually possible to relax this requirement in output stage can severely limit the frequency response of the
the design of VGA’s. To see this, we rewrite (2) as VGA. Moreover, high levels of impedance cause a dc voltage
(18) at the output that shows a strong dependency on the gain
control current and the input common mode voltage. At the
where and are differential input voltages. In a typical same time, the output stage should handle large voltage swings
gain control loop [11], the gain control voltage is usually with low signal distortion.

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806 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 7, JULY 1998

(a)

(b)
Fig. 10. CMOS implementation of the VGA, including the pseudo-exponential voltage generator and the multiplier built with four LV composite transistors.
(a) Circuit implementation. (b) Die photograph.

Fig. 15 shows a possible implementation of an output The device sizes used in the design of the VGA are given in
stage. Current mirror – generates the current Table I.
. The first gain stage includes the cascode Fig. 16 depicts the output voltage signal of the VGA at
stage – and the current source simulated using maximum gain (29 dB) in response to a 1-kHz signal with
a current mirror driven by a current source. The feedback a total harmonic distortion (THD) of 0.9%. The overall VGA
resistor sets the gain of this stage. The second-gain stage gain as a function of the control current is shown in Fig. 17(a),
includes transistors – and – . The common where the input is kept constant at 80 mV and control current
gate transistors and are used to improve the fre- is swept from 30 to 30 A. In order to investigate the
quency response and also extend the output voltage swing. The large-signal behavior, the gain of the VGA is simulated while
load resistor is required to set the gain of the second stage. keeping the output voltage swing at its maximum (2 V ) and
Ideal voltage sources and are used in the simulations. for different values of . This was achieved by changing the

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MOTAMED et al.: LV LP WIDE-RANGE CMOS VGA 807

(a)

Fig. 13. Region of operation of the VGA with exponential gain control.

(b)
Fig. 11. Region of operation of Fig. 11. (a) Three-dimensional view. (b)
Top view of (a) showing Vcm12 and Vcm34 for symmetric operation where
v12;max =v34;max . (a)

(b)
Fig. 14. The VGA transconductance as a function of control current. (a)
Fig. 12. DC transfer characteristics of the multiplier using the new LV Simulation (b) Measurement.
composite transistors.

large- and small-signal gains [see Fig. 17(a) and (b)] illustrates
input at each gain setting such that the output is constant at 2 the excellent linearity and minimal large-signal distortion of
V . The result is shown in Fig. 17(b). The similarity between the circuit.

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808 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 7, JULY 1998

Fig. 15. The VGA output stage.

TABLE I
DEVICE SIZES OF THE VGA

Fig. 16. The VGA output when an 80-mVPP sinusoidal signal at 1 kHz is
applied at the input and gain is set to 29 dB.

multiplier, and output stage. The gain of the amplifier is


controlled exponentially by the novel pseudo-exponential
current (voltage, if needed) to voltage generator. Also, a
Fig. 18 shows the THD of the VGA at 1 kHz and the new LV/LP composite transistor is introduced to maximize
maximum output voltage swing of 2 V as the gain control the input voltage range with low-supply voltage under a
current is swept from 30 to 30 A. The input voltage gets limited power budget.
closer to a maximum level at lower values of control current The new sub-circuits developed could considerably help to
causing higher levels of THD. This can also be explained simplify the design procedure of LV/LP VGA, particularly in
by noting that the drain current in a composite transistor the context of using a VLSI-cell library containing exponential
increases with the input voltage and, as a result, the condition I–V generator, multiplier, current mirror, and output stage. For
associated with (16) may not hold well, causing an completeness, a noise analysis of the VGA is given in the
increase in THD. Fig. 19 shows the variation of the dc output Appendix, which should be useful in estimating signal-to-noise
voltage when the input terminals are shorted and is swept ratio.
from 30 to 30 A. Fig. 20 shows the small-signal frequency APPENDIX
response of the VGA for three different values of , and NOISE ANALYSIS
Table II summarizes the simulated parameters of the VGA.
This section briefly discusses the thermal noise characteris-
tics of both simple and LV composite transistors. In general,
V. CONCLUSION the thermal noise in the drain–source channel of an MOS
In this paper, we introduce an LP LV metal– transistor can be written as [16], [17]
oxide–semiconductor-only (MOS-only) VGA. This amplifier
is composed of an exponential voltage generator, analog (27)

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MOTAMED et al.: LV LP WIDE-RANGE CMOS VGA 809

(a)
Fig. 19. The variation of the VGA output dc voltage when Vin = 0 and IC
0
is changed from 30 to 30 A.

(b)
Fig. 17. The VGA gain as a function of control current IC : (a) when the
input is kept constant at 80 mVPP and (b) when the output is kept constant
at 2 VPP . Fig. 20. Small-signal frequency response of the VGA for IC = 30, 0, and
0 30 A.

written as

(28)

The equivalent transconductance of the LV composite tran-


sistor, shown in Fig. 7(c), can be obtained as

(29)

Neglecting the noise contribution of the p-type current mirror,


the input noise voltage can be expressed as

(30)

Fig. 18. The THD of the VGA as a function of the gain control current at and the noise current is given by
1 kHz and Vout =
2 VPP .
(31)

where is the Boltzmann constant and is the absolute The term in the above equation represents the
temperature. The input thermal noise voltage can be simply noise contributed by the level shifter . Including the noise

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810 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 7, JULY 1998

TABLE II and
SIMULATED PARAMETERS OF THE VGA
(37)
(38)
and the small-signal output current is given by
(39)
Comparing (27) with (33) shows that the LV composite
transistor has higher noise current than a simple composite
transistor. This is the price paid for a larger input voltage
range achievable only by the LV composite transistor.

REFERENCES
[1] E. A. Vittoz, “The design of high performance analog circuits on digital
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[2] E. Sano, T. Tsukahara, and A. Iwata, “Performance limits of mixed
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[3] J. Y. Michel, “High performance analog cells in mixed signal VLSI:
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[4] W. Serdijn, A. C. van der Woerd, and J. C. Kuenen, Eds., “Special
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[5] L. M. Terman and R.-H. Yan, Eds., “Special issue on low power
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[6] A. Rodriguez-Vazquez and E. Sanchez-Sinencio, Eds., “Special issue
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systems,” IEEE Trans. Circuits Syst. I, vol. 42, Nov. 1995.
[7] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. New
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[8] A. Motamed, C. Hwang, and M. Ismail, “CMOS exponential current-
to-voltage converter,” Electron. Lett., vol. 23, pp. 998–1000, June 1997.
[9] A. Motamed, “Low-voltage VLSI circuits and signal processing,” Ph.D.
Dissertation, Dept. Elect. Eng., Ohio State Univ., Columbus, 1996.
contribution of the p-type current mirror, the noise current [10] T. W. Pan and A. Abidi, “A 50-MHz variable gain amplifier for magnetic
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assumes the form Aug. 1989.
[11] R. Harjani, “A 50-MHz variable gain amplifier for magnetic data storage
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[12] E. Seevinck and R. F. Wassenaar, “A versatile CMOS linear
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[13] M. Ismail and T. Fiez, Analog VLSI Signal and Information Processing.
where is the transconductance of New York: McGraw-Hill, 1994.
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transconductance can be increased so that the term [15] H. Wallinga and K. Bult, “Design and analysis of CMOS analog signal
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[16] T. Shiimoto, Private communication, Aug. 1996.
[17] C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System
(33) Design. New York: Wiley, 1993.

The output noise current of the VGA, shown in Fig. 10(a),


can be written as Ali Motamed received the B.S. degree from Iran
University of Science, Tehran, Iran, in 1985, the
M.S. degree from Tehran University, Tehran, Iran,
in 1988, and the Ph.D degree from Ohio State
University, Columbus, in 1996, all in electrical
(34) engineering.
In 1985, he was a Consultant, developing soft-
ware and hardware. He was with the Analog VLSI
where Laboratory, Ohio State University, where he was an
Instructor in the Solid-State Microelectronics Lab-
oratory. He is currently a Senior Design Engineer
(35) at Exar Corporation, Fremont, CA. From 1992 to 1994, he was engaged in
research involving finite-element analysis of semiconductor devices. Since
1994, he has conducted research in several areas, including LV LP CMOS
(36) mixed analog/digital integrated circuits, analog signal processing, and high-
speed data converters. He holds one U.S. patent.

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MOTAMED et al.: LV LP WIDE-RANGE CMOS VGA 811

Changku Hwang (SM’97) received the B.S. degree Mohammed Ismail (S’80–M’82–SM’84–F’97) re-
in electronics engineering from Hanyang University, ceived the B.S. and M.S. degrees in electronics and
Seoul, Korea, in 1985, and the M.S. and Ph.D. telecommunications engineering from Cairo Uni-
degrees in electrical engineering from Ohio State versity, Cairo, Egypt, in 1974 and 1978, and the
University, Columbus, in 1992 and 1996, respec- Ph.D. degree in electrical engineering from the
tively. University of Manitoba, Winnipeg, Man., Canada,
From 1985 to 1990, he was with the Semiconduc- in 1983.
tor Division, SamSung Electronics, Korea, where he He is currently a Professor in the Department
was a Process Development Engineer. From 1990 of Electrical Engineering, Ohio State University,
to 1995, he was a Research Assistant at Ohio State Columbus. He co-founded Micrys Inc. (formerly
University. From 1995 to 1997, he was a Senior ChipWorks, Inc.), Columbus, OH, a commercial
Manager in the VLSI Division, Micrys Inc., Columbus, OH (a commercial VLSI design company specializing in analog and mixed-signal ASIC’s. He has
VLSI design company), where he directed projects in LP CMOS mixed- previously held several positions in both industry and academia and has served
signal video interface circuits and data converters. From 1996 to 1997, he as a Corporate Consultant for nearly 20 companies in the U.S. and abroad.
was a Post-Doctoral Researcher with the Analog VLSI Laboratory, Solid- He held visiting appointments at the Norwegian Institute of Technology,
State Microelectronics Laboratory, Ohio State University, Columbus. He University of Oslo, University of Twente, Tokyo Institute of Technology, and
is currently a Visiting Senior Researcher in the Communication Systems Helsinki University of Technology. He has authored numerous publications
Research Department, Hitachi Central Research Laboratory, Tokyo, Japan. on VLSI circuit design and signal processing, and has been awarded several
His research areas include design of LV LP VLSI circuits and RF circuits patents in the area of analog VLSI. He has co-edited and co-authored several
for communications applications. He has published three book chapters, six books, including Analog VLSI Signal and Information Processing, (New York:
journal papers, and 20 conference papers. He holds one U.S. patent. McGraw-Hill, 1994). His current interests include LV LP VLSI circuits, RF
circuits for wireless communications, statistical computer-aided design, and
optimization for yield enhancement and VLSI information processing. He has
advised the work of 13 Ph.D. students, 17 visiting scholars, and 46 M.S.
students. He is the founder of the International Journal of Analog Integrated
Circuits and Signal Processing and serves as the Journal’s North American
Editor-In-Chief.
Dr. Ismail has been the recipient of several awards, including the IEEE
Outstanding Teacher Award (1984), the NSF Presidential Young Investigator
Award (1985), the OSU Lumley Research Award (1993 and 1997), the
SRC Inventor Recognition Awards (1992 and 1993), and a Fulbright/Nokia
Foundation Award (1995). He has served the IEEE in many editorial and
administrative capacities, including general chair of the 29th Midwest Sym-
posium on Circuits and Systems (CAS), chair of the CAS Analog Signal-
Processing Technical Committee, member of the CAS Society’s Board of
Governors, the CAS Society’s editor of the IEEE Circuits and Devices
Magazine and Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND
SYSTEMS, IEEE TRANSACTIONS ON NEURAL NETWORKS, and IEEE TRANSACTION
S ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS. He is also a regular
columnist of the IEEE Circuits and Devices Magazine.

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