Experiment No.

01
Clippers
Aim:
1. To design and conduct an experiment on clipping circuits for the given transfer
characteristics.
2. To Design a Positive clipper using Diode.
3. To Design a Negative clipper using Diode.
4. To Design a Combinational clipper using Diode.
. To Design a !ndependent level clipper using Diode.
". #ire Clipper circuit $ Test %or&ing.
'. (ecord (eading $ compare %ith design values give conclusion.

Components Required:
1. Diode )*+ 12' , !N4--'. /1 No.
2. (esistor )Carbon0 1,4#0 1-1. 2 Nos.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No.
3. Dual Po%er 3uppl9 )-/3-:0 2;0 <12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. Patch Cards , #ires /1-Nos.
". Probes 2 3 Nos.
(a) Typical Positie Clipper C!T:
Select input voltage V
in
=10V
P-P
1KHZ Sine Wave
"esi#n Procedure:
To find the valve of Resistor
(r > (everse resistance 1-6?0 (f > 4or%ard resistance 1-?0
R= RrRf $ 10!%
@et the voltage to clip sa9 2 :olts i.e.0 :
=
)max. > 2:
*9 appl9ing A:@ /:o B :ref B:r > -
@et :r )diode drop voltage. > -." volts
:ref > :o 2 :r
:ref > 2 2 -."
&re' $ 1.( olts.
)or*in# Procedure:
1. 6a&e the connection as sho%n in the circuit.
2. 3et the input signal from the signal generator as per design
3. 3et :
ref
:oltage from the po%er suppl9 as designed.
4. =bserve the output %aveform on the C(= and record 9our observation.
. =bserve the transfer characteristics on C(= b9 selecting C/+ mode.
(+) Typical Ne#atie Clipper C!T
"esi#n Procedure:
@et the voltage to clip sa9 2 2 :olts i.e. :o )min. > / 2:
*9 appl9ing A:@ /:o 2:ref 2 :r > -
@et :r )diode drop voltage. > -." volts
:ref > /:o / :r
:ref > 2 2 -."
&re' $ 1.( olts
)or*in# Procedure: Sae as Positive !lipper
(C) Typical Com+inational Clippin# C!T
"esi#n Procedure:
@et :
ref1 >
:
ref2
> :
ref
>

4:
@et the voltage to clip sa9 4 :olts i.e. :o )max. > 4: :o)min. > /4:
,y applyin# !&- .&o / &re' / &r $ 0
@et :r )diode drop voltage. > -." volts
:ref > :o 2 :r
:ref > 4 2 -."
:ref > 3.4 volts.
)or*in# Procedure: Sae as Positive !lipper
(d) Typical 0ndependent leel clippin# C!T
Fig. (5) Circuit Diagram Input output Waveforms Transfer Characteristic
"esi#n Procedure:
To clipping the signal belo% 2 :olt and above 4 :olt levels

@et :
(1
D :
(2

1E :
o max
> 4 :
;ppl9 A:@ >D
/:
o max
B :
(1
B :
r
> -
:
(1
> :
o max
2 :
r
> 4 2 -."



2E :
o min
> 2 :
;ppl9 A:@ >D
/:
o min
B :
(2
2 :
r
> -
:
(2
> :
o min
B :
r
> 2 B -."

&
R1
$ 1.2 &
)or*in# Procedure: 3ame as Positie Clipper
Type o' Clipper
tested
"esi#ned &alue Practical 4easured alue Remar*s
Positive Clipper
Negative Clipper
Combinational
Clipper
!ndependent Clipper
Conclusion:
Experiment No. 01
&
R1
$ 5.( &
Clampin# Circuits
Aim:
1. Design and conduct an experiment on Positive, Negative Clamping circuit for a given
reference voltage.
2. To Design a positive clamping using Diode.
3. To Design a Negative clamping using Diode.
4. #ire Clamping CAT $ test %or&ing.
. (ecord (eading $ compare %ith designed values give conclusion.
Components Required:
1. Diode )*+ 12' , !N4--'. 2 1 No.
2. Capacitor )Ceramic Dis&. 2 1 Nos.
Equipments Required:
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No.
3. Dual Po%er 3uppl9 )-/3-:02;0 <12:. /1 No.
4. Dual Channel C(= )2-678. /1 No.
. Patch Cards , #ires /1-Nos.
". Probes / 3 Nos.
Positie Clamper: &o $ &
i
/ &
m
4or :
i
> - :
o
> :
m
4or :
i
> :
m
:
o
> 2:
m
4or :
i
> /:
m
:o > -
Ne#atie Clamper: &o $ &
i
6 &
m
4or :
i
> - :
o
> /:
m
4or :
i
> :
m
:
o
> -
4or :
i
> /:
m
:o > /2:
m
"esi#n Procedure:
(C

DD T0 (C

DD 2- ms )sa9.
(DD
[
2-ms
-. 1Ff
]
( G
2-- K
i.e. ( >
2-- K
3elect C $
-.1Ff
7 R $
2-- K
)or*in# Procedure:
1. 6a&e the connection as sho%n in the circuit.
2. 3et the input signal from the signal generator as per design.
3. 3et :
ref
:oltage from the po%er suppl9 as per design.
4. =bserve the output %aveform on the C(= and record 9our observation.
Conclusion:
Experiment No 05
3eries and Parallel Resonance Circuits
A04:
1. To obtain the freHuenc9 response of (@C series and parallel circuit and hence to
Determine.
2. To Design a (esonance freHuenc9 f
-.

3. To Design a *and %idth0 upper and lo%er half po%er freHuencies.
4. I factor.
Components Required:
1. (esistor )Carbon0 1,4#0 1-1. 2 1 Nos.
2. Capacitor )Ceramic Dis&. 2 1 Nos.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator 2 )2 678. /1 No.
3. Dual Channel C(= )2-678./1 No.
4. Connecting #ires /1-Nos.
. Probes 2 3 Nos.
(a)Typical Circuit dia#ram: 3eries resonance
"esi#n Procedure:
Theoretical resonance freHuenc9
f=
1
2J

LC
eq
88888.. (1)
3elect '$ 1!9: and C $
-.1Ff
3o from eHuation )1. %e get -$0.1;59 3elect R $
1--
Tabular ColumnK 3elect :in > 1-:
P/P
3ine #ave

4reHuenc9 )78. :oltage )v.
Current)m;.
! > :,(
1--
2--
.
.
.
.
2A78
4reHuenc9 (esponse
*and #idth > f
2
/f
1
I 4actor > fo , *and #idth
)<R!0N= PR<CE">RE: 3ER0E3 RE3<NANCE C0RC>0T
1. 6a&e the circuit connections as sho%n in fig.
2. ;C suppl9 is s%itched on and oscillator output voltage is adLusted to 1- volts pea& to
Pea&.
3. The freHuenc9 is graduall9 varied from 1-- hert8 and for different values of MfN current
!s noted do%n. The results are tabulated in the tabular column.
4. Plot the graph of freHuenc9 versus current.
. 4rom the graph0 (esonant freHuenc9 MfoN is noted do%n at %hich O current is
6aximumP i.e. !o.
". @o%er half po%er freHuenc9 M f1 M and upper half po%er freHuenc9 M f2 M are noted.
Corresponding to a current !o,Q2. *and%idth > f2 2 f1 > RRRRR.78.
'. The I factor > fo , )f2 2 f1.
RE3>-T: fo > RRRRR.780 f1 > RRR780 f2 > RRR780 *#> RRR78 and I >
(+) Typical Parallel Resonance Circuit
"esi#n Procedure: 3ame as series resonance Circuit
Tabular ColumnK 3elect :in > 1-:
P/P
3ine #ave
4reHuenc9
)78.
:oltage
)v.
Current)m;.
! > :,(
1--
2--
.
.
.
2A78
)<R!0N= PR<CE">RE: 3ame as series resonance Circuit
4reHuenc9 (esponse
RE3>-T:

fo > RRRRR. 78 0 f1 > RRRR780 f2 > RRRR780 *# > RRR..78 and I >
Experiment No 0(
&eri'ication o' net?or* t@eoremAs 'or "C Circuits
A04: :erification of ThevininNs $ 6aximum Po%er Transfer theorems for DC circuits.
Components Required:
1. (esistor )Carbon0 1,4#0 1-1. 2 3 Nos.
Equipments Required
1. 3pring *oard 2 1 No.
2. Dual Po%er 3uppl9 )-/3-:0 2;0 12:./1 No.
3. ;mmeter )-/2-m; /analog. /1 No.
4. :oltmeter )-/2-: 2 analog. 2 1 No.
. D(* )1? / 1--A?. 2 1 No.
". Connecting #ires /1-Nos.
'. Probes 2 3 Nos.
Typical Circuit dia#ram:

To 'ind Current 01





To 'ind T@eeninAs &olta#e B&t@C


To 'ind T@eininAs Equialent Resistance R
t@

To 'ind Current 0
t@
)or*in# Procedure:
1. Connect the circuit as sho%n in the circuit diagram.
1. 4ind out current !
1
4rom the ammeter as sho%n in fig.
5. 4ind :
th
)ThevininNs voltage. b9 removing load at Point ; $ *.
(. 4ind ThevininNs resistor (
th
b9 shorting source as sho%n in fig.
;. 4ind out current !
2
b9 connecting po%er suppl9 )i.e. :
th
. as sho%n in Circuit.
2. &eri'y 0
1
$

0t@ (T@eorem is eri'ied).
RE3>-T:
1. ThevininNs :oltage > RRRR :.
2. ThevininNs (esistance > RRRR.. =hm.
3. ThevininNs Current > RRRRRRR m;.
(+) 4aximum Po?er Trans'er T@eorem: The maximum po%er %ill transfer to the load
%hen the load resistor value is eHual to the source resistor value
)@en R
-
$ R
3
t@en ?e ?ill #et maximum Po?er
Ta+ular Column:

3elect R
3
$ 1! o@ms.

:
volts
!
m;
P > :S! )#atts. (
@
1--
2--
R
.
.
.
2A78
Nature of Graph
)<R!0N= PR<CE">RE:
1. 6a&e the circuit connections as sho%n in fig.
2. 3uppl9 voltage : is set to 1- volts. The potentiometer (
@
is &ept at maximum.
3. The readings of voltmeter ):. and ammeter )!. are noted do%n in tabular column.
4. (
@
is decreased in steps and at each step : and ! are tabulated.
. ; graph (
@
versus po%er is plotted. The po%er maximum Pmax > RRRR %atts.
;nd (
@
> RRR.. ohm.

RE3>-T:
1. @oad resistance (@ > RR.. ohms
2. 6aximum po%er Pmax > RRRR %atts.
Experiment No 0;
R. C Coupled Ampli'ier
Aim:
1. To design and conduct the experiment on (C Coupled amplifier using *ipolar Tunction
Transistor )*TT. and hence0
2. Plot the freHuenc9 response.
3. Determine its band%idth.
4. 4ind input and output impedance.
Components Required:
1. Transistor )3@1--./1 No.
2. (esistor )Carbon0 1,4#0 1-1. 2 Nos.
3. Capacitor )Ceramic Dis&. 2 2 Nos.
4. Capacitor )Ulectrol9tic. 2 1 Nos.
. D(* )1? / 1--A?. /1 No.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No
3. Dual Po%er 3uppl9 )-/3-:0 2;0 <12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. D(* )1? / 1--A?. 2 1 No.
". Patch Cards , #ires /1-Nos.
'. Probes 2 3 Nos.
Typical Circuit dia#ram:
*iasing Circuit
"esi#n Procedure:
@et :
CC
> 12 :
0
!C > 4. m;0 V > 1--)for 3@ 1--.
Choose :
U
> :
CC ,
1- > 12,1- > 1.2 :
:
U
> !
U
(
U
> 1.2 :
(
U
> 1.2,!
c
> 1.2,4.m; > -.2"' AW )!
U
X !
C
.
R
C
: Choose :
CU
> :
CC
,2 12,2 > ":
;ppl9 A:@ in CU loopK
:
CC
2 !
C
(
C
2 :
CU
2 :
(U
> -
12 2 4.(c 2 " 2 1.2 > -
(
C
> 1.o' AW
3elect
R
1
and R
1
: :
*
> :
*U
B :
U
> -.' B 1.2 > 1.Y :
#e &no%
V
B
=Vcc
R
2
R
1
+R
2



1. Y=12
R
2
R
1
+R
2

R
2
R
1
+R
2
=
1. Y
12
=-. 1Z
(
2
> -.1Z(
1
B -.1Z(
2
-.Z41"(
2
> -.1Z(
2
-et us assume R
1
$ (.D!E

(
1
> 2 AW
C@oose R
1
$ 1D!E

,y pass capacitor C
E
:
-et
X
CE
=
R
E
1-

R
E
$ 1D0 E
R
C
$ 1!E
At ' $ 100 9FG
1
2J fce
=
R
E
1-


C
E
=
1-
2J1--2'-
=Y F
C@oose C
E
$ (D HI (electrolytic)
Cc1 and C
C1
: Assume C
C1
$ C
C1
$0.1 HI (ceramic)
R1 $ 1D!%7 R1 $ (.D!%7 R
E
$ 1D0%7 R
C
$ 1 !%
C
E
$ (DHI (Electrolytic)7 C
C
$ 0.1HI (Ceramic)
Irequency Response cure
TA,>-AR C<->4N:

:
in
> - m:
3@
N=
4(UI[UNC+
in 78
:
o)p/p.
in :olts
;
v
>:
o
,:
i
:oltage 5;!N in d* > 2- log):
o
,:
i
.
)or*in# Procedure:
1. Connect the circuit as sho%n in the circuit diagram.
2. 3et the input -mv sine %ave signal from the signal generator.
3. :ar9 the freHuenc9 from 1--78 to 1678 and note do%n : )p/p. on the C(=.
4. Tabulate the reading\ dra% the freHuenc9 v,s gain b9 using semi log graph.
. 4ind the band %idth f
2
2 f
1
as sho%n in the freHuenc9 response curve.
T< 4EA3>RE :i:
)or*in#
Procedure:
1. Connect the circuit as sho%n in the circuit diagram.
2. 3et the D(* to the minimum value.
3. 3et the signal generator )voltage. to -m: pea& to pea& and freHuenc9 to 1- A78.
4. !ncrease the D(* till :o

becomes half of the :o
.

. Corresponding D(* value %ill give the input impedance.
T< 4EA3>RE :o:

)or*in#
Procedure:
1. Connect the circuit as sho%n in the circuit diagram.
2. 3et the D(* to the maximum value.
3. 3et the signal generator )voltage. to -m: pea& to pea& and freHuenc9 to 1- A78.
4. Decrease the D(* value till :o

becomes half of the :o
.

. Corresponding D(* value %ill give output impedance.
Result:
1. *and %idth>RRRRRRR
2. !nput impedance>RRRRR
3. =utput impedance>RRRRR.
4. I Point (0
c
7 &
CE
. > RRRRR
Experiment No 02
<scillators
Aim:
1. Design and Testing of 7artle9 and Colpitts =scillator for given freHuenc9 of 1-- A7]
using *TT.
Components Required:
1. Transistor )3@1--./1 No.
1. (esistor )Carbon0 1,4#0 1-1. 2 Nos.
5. Potentiometer )-/1A?. .1 No.
(. Capacitor )Ceramic Dis&. 2 2 Nos.
;. Capacitor )Ulectrol9tic. 2 1 Nos.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No.
3. Dual Po%er 3uppl9 )-/3-:02;0 12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. D!* )-^7/ 1-7. / 2 Nos.
". DC* )1---pfd 2 1-^fd. 2 2 Nos.
'. Patch Cards , #ires /1-Nos.
Z. Probes 2 3 Nos.
Requirements 'or an oscillator
1. ;n oscillator circuit containing (/@/C to produce electrical oscillations.
2. ;n amplifier i.e. transistor to suppl9 the losses that occur in the oscillator9 circuit.
3. ; feedbac& circuit to suppl9 the energ9 to the oscillator9 circuit in correct phase and
magnitude.
4. 4eedbac& should be positive.
IEE",AC!: The process or returning a part of the output signal of an amplifier bac& to the
input circuit is called as feedbac&.
9ART-EJ <3C0--AT<R
!t uses t%o inductor @
1
and @
2
placed across a common capacitor C0 The freHuenc9 of oscillators is
determined b9 the values of @
1 0
@
2
and C0 %hich is given b9\
Typical Circuit dia#ram:
"esi#n Procedure:
Ior +iasin# circuit: 3ame as RC Coupled Ampli'ier
R1 $ 1D!%7 R1 $ (.D!%7 R
E
$ 1D0%7 R
C
$ 1 !%
C
E
$ (DHI (Electrolytic)7 C
C
$ 0.1HI (Ceramic)

Ior Tan* circuit:
-et ' $ 100!9: and C $ 1000pI
L=
1
4_
2
f
2
C
$ 1.;5m9 )@ere -$ -1 / -1 3elect -1 K -1
C<-P0TTA3 <3C0--AT<R
!t uses t%o inductor C1

and C
2
placed across a common inductor @0 The freHuenc9 of oscillators is
determined b9 the values of C
1 0
C
2
and @0 %hich is given b9\
f=
1
2J

LC
eq
#here
C=
C
1
C
2
C
1
+C
2
Circuit dia#ramK
"esi#n Procedure:
Ior +iasin# circuit: 3ame as RC Coupled Ampli'ier
R1 $ 1D!%7 R1 $ (.D!%7 R
E
$ 1D0%7 R
C
$ 1 !%
C
E
$ (DHI (Electrolytic)7 C
C
$ 0.1HI (Ceramic)

Ior Tan* Circuit:
<scillation 'requency f > 1-- A78

f=
1
2J

LC
eq

#here
C=
C
1
C
2
C
1
+C
2
Assume C1$ 1000 pI and C1 $ 1100 pI

C=
1---22--1-
24
1---22--1-
12


C=
1---22--1-
12
1---22--
="Z'. pF

L=
1
4J
2
f
2
C
- $ 5.2m9
)or*in# Procedure:
1. Connect the circuit as sho%n in 4ig.
2. 3%itch on the D.C. po%er suppl9.
3. :ar9 Pot connected in series %ith (
U
to get clear sine %ave.
4. =bserve the output %aveform on C(= screen.
. 6easure the freHuenc9 of the output %aveform.
". Compare the measured freHuenc9 %ith theoretical value.
Result: 9artley L colpitts <scillators are desi#ned L tested 'or a 'requency o'
100!9: usin# ,MT.
Experiment No 0D
R.C P@ase 3@i't <scillator
A04:
1. Design and Testing of (/C Phase 3hift =scillator for given freHuenc9 of 1!9:.
Components Required:
1. Transistor )3@1--./1 No.
2. (esistor )Carbon0 1,4#0 1-1. 2 4 Nos.
3. Capacitor )Ceramic Dis&. 2 Nos.
4. Capacitor )Ulectrol9tic. 2 1 Nos.
. Potentiometer )-/1A?./1 No.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No.
3. Dual Po%er 3uppl9 )-/3-:02;0 <12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. Patch Cards , #ires /1-Nos.
". Probes 2 3 Nos.
Typical Circuit dia#ram:
"esi#n Procedure:
Ior +iasin# circuit: 3ame as RC Coupled Ampli'ier
R1 $ 1D!%7 R1 $ (.D!%7 R
E
$ 1D0%7 R
C
$ 1 !%
C
E
$ (DHI (Electrolytic)7 C
C
$ 0.1HI (Ceramic)


P@ase s@i'tin# net?or* desi#n:

The freHuenc9 of oscillations is determined b9 phase shifting net%or&.

The oscillating freHuenc9 for the above circuit is given b9

f=
1
2J RC"
------ (1)
-et '$ ; !9: and c@oose C

$ 0.01HI
So from equation (1) e i!! get R=1.2 !%
)or*in# Procedure:
1. Connect the circuit as sho%n in 4ig.
2. 3%itch on the D.C. po%er suppl9.
3. =bserve the o,p :o on C(=.The1-A pot is adLusted to get a stable output on the C(=.
4. 6easure the freHuenc9 of the output %ave.
. Compare the measured freHuenc9 %ith theoretical value.
Result: Irequency o' <scillation$ 888..9F
Experiment No 0N
Crystal oscillator
A04:
1. To design and test the performance of a cr9stal =scillator
Components Required:
1. Transistor )3@1--./1 No.
2. Cr9stal /1 No.
3. (esistor )Carbon0 1,4#0 1-1. 2 4 Nos.
4. Capacitor )Ceramic Dis&. 2 2 Nos.
. Capacitor )Ulectrol9tic. 2 1 Nos.
". Potentiometer )-/1A?./1 No.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No.
3. Dual Po%er 3uppl9 )-/3-:0 2;0 <12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. DC* )1---pfd 2 1-^fd. /1 No.
". Patch Cards , #ires /1-Nos.
'. Probes 2 3 Nos.
Typical Circuit dia#ram:
"esi#n Procedure: 3ame as RC Coupled Ampli'ier
R1 $ 1D!%7 R1 $ (.D!%7 R
E
$ 1D0%7 R
C
$ 1 !%
C
E
$ (DHI (Electrolytic)7 C
C
$ 0.1HI (Ceramic)

)or*in# Procedure:
1. Connect the circuit as sho%n in 4ig.
2. 3%itch on the D.C. po%er suppl9.
3. =bserve the o,p :o on C(=.The1-A pot is adLusted to get a stable output on the C(=.
4. 6easure the freHuenc9 of the output %ave.
. Compare the measured freHuenc9 %ith theoretical value.
Result:
Irequency o' <scillation$ 8889F.
EOPER04ENT N<. 0P
&<-TA=E 3ER0E3 IEE",AC! A4P-0I0ER
A04:
1. To determine the freHuenc9 response of a t%o stage ( C/ Coupled ;mplifier %ith and
%ithout feedbac&.
2. To measure the 5ain and input impedance )]
i
. and output impedance )]
o
. for %ith and
%ithout feedbac&.
Components Required:
1. Transistor )3@1--./2 No.
2. (esistor )Carbon0 1,4#0 1-1. 2 Y Nos.
3. Capacitor )Ceramic Dis&. 2 3 Nos.
4. Capacitor )Ulectrol9tic. 2 1 Nos.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator /2 678 /1 No.
3. Dual Po%er 3uppl9 )-/3-:0 2;0 <12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. D(* 2)1? / 1--A?. / 1 No.
". Patch Cards , #ires /1-Nos.
'. Probes 2 3 Nos.
Typical Circuit dia#ram:
C c 1
C E
R c 1
R 2 R 4
C c 2
V o
R E 2
R E
R c 2
R E 1
V i =
5 0 m V
Q 1 Q 2
C c 3
R 1 R 3
V C C = 1 2 V
Ii#: )it@out 'eed+ac*
C c 1
C E
R c 1
R 2 R 4
C c 2
R F
V o
R E 2
R E
R c 2
R E 1
V i =
5 0 m V
Q 1 Q 2
C c 3
R 1 R 3
V C C = 1 2 V
Ii#: )it@ 'eed+ac*
"esi#n Procedure: 3ame as RC Coupled ampli'ier
R1 $ 1D!%7 R1 $ (.D!%7 R
E
$ 1D0%7 R
C
$ 1 !%
C
E
$ (DHI (Electrolytic)7 C
C
$ 0.1HI (Ceramic)
4or ! stage split (
U
into t%o parts.

R
E
$ 100 % / 1D0 %
Design of second stage is same as that of first stage. >se R
E $
1D0%
The feedbac& factor
=
R
1
E
R
f
+R
1
E
R
1
E
=33- %
The feedbac& resistor (
f
should be much greater than (
C
.

3hould be bet%een -.-1 to -.1.

@et R
' $
10 !% then
=
33-
33-1-, ---
=-. -32
7ence

is %ithin the usual chosen values -.-1 to -.10 so choose R

' $
10 !%
TA,>-AR C<->4N:

:
in
> - m:)p/p.
4reH..
in 78
:
o)p/p.
in :olts
%ithout
feedbac&
:
o)p/p.
in :olts
%ith
feedbac&
;
v
>:
o
,:
i
;
v fb
>:
o
,:
i
5
d*
>2- log):
o
,:
i
.
5
fb d*
>2- log):
o
,:
i
.


To measure :i and :o: Procedure is similar to RC coupled ampli'ier.
RE3>-T:
*and%idth %ithout 4eedbac& K ````````````````````````
*and%idth %ith 4eedbac& K ````````````````````````
!nput !mpedance %ithout 4eedbac& K ````````````````````````
!nput !mpedance %ith 4eedbac& K ````````````````````````
=utput !mpedance %ithout 4eedbac&K ````````````````` ``````
=utput !mpedance %ith 4eedbac& K ````````````````` ```````
EOPER04ENT N<: 10
RECT0I0ER3
A04:
1. To eri'y 9al' ?ae7 Iull ?ae and ,rid#e recti'iers
Components Required:
1. Diode )*+ 12' , !N4--'. / 4 No.
2. (esistor )Carbon0 1,4#0 1-1. 2 1 Nos.
3. Capacitor )Ulectrol9tic. 2 1 Nos.
Equipments Required
1. Transformer )3tep do%n0 23-,':/-/':. 2 1 No.
2. 3pring *oard 2 1 No.
3. Dual Channel C(= )2-678. 2 1 No.
4. D(* 2 )1? / 1--A?. / 1 No.
. Patch Cards , #ires /1-Nos.
". Probes 2 3 Nos.
"esi#n Procedure:
(a) 9al' )ae recti'ier ?it@out L ?it@ 'ilter
Calculations:
:in )ac. >D rms value of input )secondar9 of the transformer.
:o )dc. >D ;verage value of dc output
:o)ac. >D rms value of ac component of the output voltage
(ipple factor >rms value of ac component , value of dc component > :o )ac.,:o )dc.
1 Ufficienc9>output po%er , input po%er > a:
o
)dc.,:
in
)ac.E
2
x 1--
1 (egulation> a:o)dc.N@ / :o)dc.4@E , :o)dc. 4@ x 1--

"esi#n Procedure: 9)R )it@out 'ilter
@et :o)dc. >":
4or 7#( :m > :o)dc. x b >1Z.Z:
:in)ac. >:
m
, Q2>13.3: ) Note K [se 12K-K12 or 1K-K1 Transformer.
@et !
dc
>1-m;0 (@>:o)dc. , !
dc
>": , 1-m;>"--?
9)R )it@ Iilter :
4or 7#( ripple factor is given b9 c > 1 , )2Q3xCxfx(@.
#here f > -78 (@ > "--?
!f c > 21 or -.-2 then C > 4'-^4
!f c > 11 or -.-1 then C > 1---^4
Typical Circuit dia#ram: 9)R (Connect suita+le C 'or ?it@ 'ilter circuit)
Ta+ular Column : 9)R ?it@out 'ilter
:in )ac. > RRRRR :o)dc. N@> RRR. :o)dc. 4@ > RRRR.. 1 ( > RRRR
(@ :o)dc. :o)ac. d>a:o)dc.,:in)ac.E
2
x 1-- c >a:o)ac. , :o)dc.E x 1--
"--?
1-A?
9)R ?it@ 'ilter
:in)ac. >RRRR C>RRR..
(@ :o)dc. :o)ac. c> a:o)ac. , :o)dc.E x 1--
"--?
(+) Iull ?ae Recti'ier: )it@out 'ilter
@et :o)dc. >12:
:m>:o)dc.x )J , 2.>1Z.Z
:in)ac.>:m , Q2 > 13.3 )3elect 12K-K12 or 1K-K1 Transformer.
@et !dc >1-m;0 (@>:o)dc. ,!dc >12: , 1-m;>1.2&?
)it@ 'ilter :
c >1 , )4Q3xfxCx(@.
!f c >11 or -.-1 3elect C>2--^4
!f c >-.1 or -.-- then select C>4'- ^4
Typical circuit dia#ram: Center tap I)R
4igK Center tap 4#( )Connect suitable C for %ith filter circuit.
Ta+ular Column: Center tap I)R )it@out 'ilter
:in )ac. > RRR
(@ :o)dc. :o)ac. 1 d
c 1
1.2&?
1- &?
Center tap I)R )it@ Iilter
:in)ac.>RRR.. C>RRR..

(@ :o)dc. :o)ac. 1 (ipple 4actor
1.2&?
1- &?
(c) ,rid#e recti'ier: "esi#n is similar to Center tap I)R.
Typical circuit dia#ram:
4igK 4ull %ave *ridge rectifier circuit )connect suitable C for %ith filter circuit.
Ta+ular column: ,rid#e recti'ier ()it@out Iilter)
:in )ac. > RRRR
(@ :o)dc. :o)ac. 1 d c 1
1.2&?
1- &?
#ith 4ilterK :in )ac. > RRR.. C > RRR.
(@ :o)dc. :o)ac. c 1
1.2&?
#aveforms for 4#( K
(esult K
Experiment No 11
Components Required:
1. Transistor )3@1--./2 No.
2. (esistor )Carbon0 1,4#0 1-1. 2 Y Nos.
3. Capacitor )Ceramic Dis&. 2 3 Nos.
4. Capacitor )Ulectrol9tic. 2 1 Nos.
Equipments Required
1. 3pring *oard 2 1 No.
2. 4unction 5enerator )2 678. /1 No.
3. Dual Po%er 3uppl9 )-/3-:0 2;0 <12:./1 No.
4. Dual Channel C(= )2-678./1 No.
. D(* 2 )1? / 1--A?. / 1 No.
". Patch Cards , #ires /1-Nos.
'. Probes 2 3 Nos.
Assume &cc $ 11&7 0C Q 0C1 $ ;mA7 R $ 100 (3-100)
4rom biasing circuit to find (U0 (1 and (2
:*1 > 2:*U B :(U :(U > :cc,2 > ":
> 2S-.' B " !U2 x (U > ": )!U2 X !c2.
> '.4: (U > " , m; > 1.2AW
To find !*20 !*1
!*2 > !c2 , V !*1 > !c1 , V
> m; , 1-- > -.-m; > !*2 , V > -.-m; , 1--
> -.---m;
;ssuming 1- !*1 flo%s through (1
(1 > ):cc 2 :*1. , 1-!*1 (2 > :*1 , Y!*1 > 1."6W X 1.6W
> )12 2 '.4. , 1-S-.---m;
> -.Y26W X 16W
Choose the coupling capacitors Cc1 > Cc2 > -.1^4
Tabular ColumnK


T<
4EA3>RE :i:
:
in
> 1: )p/p.
3@
N=
4reHuenc9
in 78
:
o)p/p.
in :olts
;v>:
o
,:
i
:oltage gain
in d*> 2-log1- ;v
1
2
3
.
.
.
.
.
1--
.
.
.
.
.
.
1678

)or*in# ProcedureK
1.
Connect the circuit as sho%n in the circuit diagram.
2.
3et the D(* to the minimum value.
3.
3et the signal generator )voltage. to 1: pea& to pea& and freHuenc9 to 1- Ah
].
4.
!ncrease the D(* value till :o

becomes half of the :o
.
.
Corresponding D(* value %ill give the input impedance.
T< 4EA3>RE :
o
:
Procedure:
1.
Connect the circuit as sho%n in the circuit diagram.
2.
3et the D(* to the maximum value.
3.
3et the signal generator )voltage. to 1: pea& to pea& and freHuenc9 to 1- A
7].
4.
Decrease the D(* value till :o

becomes half of the :
o.
.
Corresponding D(* value %ill give the output impedance.
Result:
1. *and %idth ////////////////////////////
2. !nput impedance //////////////////////
3. =utput impedance/////////////////////
4. I Point /////////////////////////////////
&ia &oice
Component Testin#