Xilinx Verilog and Cadence

1
Vi INSTITUTE OF TECHNOLOGY

VLSI DESIGN LAB MANUAL

NAME:

SIXTH SEMESTER
DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING
2013-2014
2

EC 2357: VLSI DESIGN LAB

ANNA UNIVERSITY SYLLABUS

1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers, address
decoders, multiplexers), Test bench creation, functional verification, and concepts of concurrent and
sequential execution to be highlighted.

2. Design Entry and simulation of sequential logic circuits (counters, PRBS generators, accumulators). Test
bench creation, functional verification, and concepts of concurrent and sequential execution to be
highlighted.

3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt. No. 1 and No. 2
given above. Concepts of FPGA floor plan, critical path, design gate count, I/O configuration and pin
assignment to be taught in this experiment.

4. Generation of configuration/fuse files for all the blocks/codes developed as part of Expt.1. and Expt. 2.
FPGA devices must be configured and hardware tested for the blocks/codes developed as part of Expt. 1.
and Expt. 2. The correctness of the inputs and outputs for each of the blocks must be demonstrated at least
on oscilloscopes (logic analyzer preferred).

5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of gain, bandwidth,
output impedance and CMRR.

6. Layout of a simple CMOS inverter, parasitic extraction and simulation.

7. Design of a 10 bit number controlled oscillator using standard cell approach, simulation followed by
study of synthesis reports.

8. Automatic layout generation followed by post layout extraction and simulation of the circuit studied in
Expt. No.7

Note 1. For Expt. 1 to 4 can be carried out using Altera (Quartus) / Xilinx (Alliance) / ACTEL (Libero)
tools.
Note 2. For expt. 5-8 introduce the student to basics of IC design. These have to be carried out using atleast
0.5u CMOS technology libraries. The S/W tools needed Cadence / MAGMA / Tanner.

@ViIT

For Expt. 1 to 4

Xilinx 13.1 (Alliance) Tool

For Expt. 5 to 8

Cadence Tool

3

STUDY OF VERILOG HDL AND SPARTAN-3E FPGA BOARD
EXP NO DATE VIVA ASSIGNMENT REMARKS

Aim:

To study Verilog HDL, Spartan-3E FPGA board and the related software.

Software used:
Xilinx 13.1

Device used:
Spartan-3E FPGA 250S

Theory:

Introduction to Verilog HDL:

Verilog HDL is one of the Hardware Description Languages (HDL) used to describe a
digital system. VHDL is the other one. Verilog HDL allows a hardware designer to describe
designs at a high level of abstraction such as an the architectural or behavioral level as a set of
modules. Modules can either be specified behaviorally or structurally (for a combination of two).
A behavioral specification defines the behavior of a digital system (module) using traditional
programming language constructs. E.g. if assignment statements. A structural specification
expresses the behavior of a digital system (module) as a hierarchical interconnection of sub
modules. At the bottom of the hierarchy the components must be primitives or specified
behaviorally. Verilog provides the following gate level primitives:

And/nand - logical AND/NAND
or/nor - logical OR/NOR
xor/xnor - logical XOR/XNOR
buf/not - buffer/inverter
bufif0/notif0 - tristate with low enable
bufif1/notif1 - tristate with high enable

The structure of a module is the following:

Module <module name> (<port list>);
<(declares)>
<module items>
End module.

The <module name> is an identifier that uniquely names the module. The <port list> is a list of
input, in-out and output ports which are used to connect to other modules. The <declares> section
specifies data objects as registers, memories and wires as well as procedural constructs such as
functions and tasks. The <module items> may be initial constructs, always constructs, continuous
assignments or instances of modules.
4

OPERATORS:

Bitwise operators: ~(not), &(and), |(or) and ^(xor)
Arithmetic: +, -, *, /
Unary reduction: &, &&, |, ~|, ^, ~ ^
Logical: !, &&, ||
Equality: ==, != (0,1)
Identity: ===, !== (0,1,x,z)
Relational: <,>,<=,>=
Logical shift :<<, >>
Conditional: ?:
Concatenate: {}
Replicate: {{}}

DESIGN FLOW:

Fig. Flow chart of VLSI design flow

DESIGN ENTRY: The designed circuit is specified either by means of a schematic diagram or
by using a hardware description language, such as Verilog or VHDL.
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SYNTHESIS: The entered design is synthesized into a circuit that consists of the logic elements
(LEs) provided in the FPGA board.

FUNCTIONAL SIMULATION: The synthesized circuit is tested to verify its functional
correctness. This simulation does not take into account any
timing issues. A test bench is HDL code that allows you to
provide a repeatable set of stimuli with clock and input dat for
error checking, file input and output and conditional testing.

FITTING: The CAD filter told determines the placement of LEs defined in the netlist into the
LEs in the actual FPGA chip. It also chooses routing wires in the chip to make the
required connections between specific LEs.

TIMING ANALYSIS: Propagation delays along the various paths in the fitted circuit are
analyzed to provide an indication of the expected performance of the
circuit.

TIMING SIMULATION: The fitted circuit is tested to verify both its functional correctness and
timing.

PROGRAMMING AND CONFIGURATION: The designed circuit is implemented in a physical
FPGA chip by programming the configuration
switches that configure the LEs and established
the required wiring connections.

SPARTAN-3E FPGA BOARD:

Fig. Functional block diagram
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FPGA device used: XC3S500E

The Features of the XC3S500E FPGA board are the following:
No. of Logic Blocks: 1564
No. of Macrocells: 10476
Family Type: Spartan-3E
Logic Case Style: QFP
No. of Pins: 208
No. of Speed Grades: 4
Total RAM Bits: 368640
No. of I/O's: 158
Clock Management: DLL
Core Supply Voltage Min: 1.14V
Core Supply Voltage Max: 1.26V
Operating Frequency Max: 240MHz
MSL: MSL 3 - 168 hours
SVHC: No SVHC (19-Dec-2012)
Core Supply Voltage Range: 1.14V to 1.26V
Frequency: 572MHz
I/O Interface Standard: HSTL, LVCMOS, LVTTL, SSTL
I/O Output Drive: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V
Logic IC Base Number: 3S500
Logic IC Function: FPGA
No. of Gates: 500000
Operating Temperature Max: 85C
Operating Temperature Min: -40C
Operating Temperature Range: -40C to +85C
Programmable Logic Type: FPGA
Termination Type: SMD

POCEDURE OF XILINX 13.1 SOFTWARE:

1. Start Xilinx ISE 13.1, click on CREATE A NEW PROJECT and then click on Next.
2. Select youre working directory, give the name of the project, then click on NEXT.
3. Select the device family (Spartan 3E), Device (XC3S250E), package (PQ208), Speed grade
(4), Synthesis tool (XST [VHDL/VERILOG]), simulator (ISim) and preferred language
(Verilog) from the available device list, and then click NEXT and click FINISH.
4. Write the HDL code and be careful to give the entity name the same as project name. After
writing the code save the file and click on Synthesis XST.
5. If the HDL code is error free a green check mark will be shown on the synthesis XST.
6. Select simulation then double click on Simulate Behavioral Model (here we can change
the level of abstraction. i.e. structural/behavioral/dataflow/switch level)
7. If there is zero error a new window will be shown. Apply the desired input as 1s and 0s
and check whether the outputs are correct or not in the output waveform.
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8. Expand the user constraints n the processes for source window and double click Assign
package pins (with ISE 13.1 web pack is called I/O floor plan presynthesis). This is where
you tell Xilinx which pins on Spartan 3E will be used.
9. In the Design object list I/O pins window type the pin numbers in the following pin
assignments under the heading LOC. This action will create a .UCF file for the
top_level_struct file and will contain the pin assignments for the Spartan-3E.
10. Make sure that the top_level_struct file is selected in the sources window.
11. Expand the Synthesis-XST in the Processes window and then double click it. This action
will check the syntax of the source code for top_level_struct and convert the source code
into a netlist of gates. A synthesis report will also be produced. When the synthesis is
finished, green check marks should be displayed indicating that top_level_struct has
compiled successfully.
12. Expand the Implement design process and double click on it. This is where the netlist is
translated, mapped, placed and routed for the logic circuits of the Spartan-3E FPGA. After
this process has been run, green check mark should be displayed.
13. Expand the Generate Programming file process and double click it. This process creates
A bit file that is used to program the Spartan-3E chip. Again, after this process is finished,
green check mark should be shown.
14. Expand the Implement design and double click on Generate programming file.
15. Right click on the depiction of the Spartan-3E chip and select program. If the download
was successful, the message Program succeeded will be displayed.

RESULT:

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SIMULATION AND SYTHESIS OF HALF ADDER AND FULL ADDER
EXP. NO. DATE VIVA ASSIGNMENT REMARKS

Aim:
To simulate and synthesis of half adder and full adder in behavior and structural model of
Verilog HDL and to perform timing and power analysis.

Software used:]

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program:

Half adder in Behavioral model:

module ha_behav (a, b, sum, cout);
Input a, b;
Output sum, cout;
Assign sum = a ^ b;
Assign cout = a & b;
endmodule

Half adder in Structural model:

module ha_struct (x, y, sum, co);
Input x, y;
Output sum, co;
xor (sum, x, y);
and (co, x, y)

Full adder in Behavioral model:

module fa_behav (a, b, cin, sum, cout);
Input a, b, cin;
output sum, cout;
Assign sum = a ^ b ^ c;
Assign cout = (a & b) | (b & cin) | (a & cin);
Endmodule

Full adder in Structural model:
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module fa_struct (x, y, ci, sum, co);
Input x, y, ci;
Output sum, co;
Wire im1, im2, im3;
xor (sum, x, y, ci);
and (im1, x, y);
and (im2, y, ci);
and (im3, ci, x);
or (co, im1,im2,im3);
endmodule

Observation:

Half adder:

RTL view:

Flow summary:

Total logic elements - 2/33,216 [<1%]
Total combinational functions - 2/33,216 [<1%]
Total pins - 4/475 [<1%]

Classic Timing Analysis:

Worst case tpd - 5.413 ns
Total no.of failed paths Nil

Power analysis:

Total thermal power dissipation - 110.33mw
Core dynamic thermal power dissipation - 0.00mw
Core static thermal power dissipation - 79.92 mw
i/o thermal - 30.41mw
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Simulation waveform:

Full adder:

RTL View:

Flow summary:

Total logic elements - 2/33,216 [<1%]
Total combinational functions - 2/33,216 [<1%]
Total pins - 5/475 [<1%]

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Classic Timing Analysis:

Worst case tpd - 9.265 ns
Total no.of failed paths Nil

Power analysis:

Total thermal power dissipation - 110.44mw
Core dynamic thermal power dissipation - 0.00mw
Core static thermal power dissipation - 79.92 mw
i/o thermal - 30.52mw

Simulation waveform:

Result:

12

SIMULATION AND SYNTHESIS OF 8-BIT RIPPLE CARRY ADDER

Aim:

To simulate and synthesis of 8-bit ripple carry adder in structural model of Verilog HDL
and to perform timing and power analysis.

Software used:

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Logic diagram:

Program of 8-bit ripple carry adder:

module ripmod (a, b, cin, sum, cout);
input [7:0] a;
input [7:0] b;
input cin;
output [7:0] sum;
output cout;
wire [6:0] c
fulladd a1 (a[0], b[0], cin, sum[0], c[0]);
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fulladd a2 (a[1], b[1], c[0], sum[1], c[1]);
fulladd a1 (a[7], b[7], c[6], sum[7], cout);
endmodule.

//Full adder

module fulladd (a, b, cin, sum, cout);
Input a, b, cin;
output sum, cout;
Assign sum = a ^ b ^ c;
Assign cout = (a & b) | (b & cin) | (a & cin);
Endmodule

Result:

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SIMULATION AND SYNTHESIS OF 8-BIT ADDER SUBTRACTOR

Aim:
To simulate and synthesis of 16-bit adder subtractor using Verilog HDL and to perform
timing and power analysis.

Software used:]

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program of 16-bit adder subtractor:

Module ass (a, b, cin, sum, cout);
input [15:0] a, b;
input cin;
output cout;
wire [15:0] c, d;
output [15:0] sum;
assign d[0] = b[0] ^ cin;
rip r1 (a[7]), d[7:0], cin, sum[7:0], c[7:0]);
rip 21 (a[15:8]), d[15:8], c[7:0], sum[15:8], cout);
endmodule

// Ripple adder

module rip (a, b, cin, sum, cout);
input [7:0] a;
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input [7:0] b;
input cin;
output [7:0] sum;
output cout;
wire [6:0] c
fulladd a1 (a[0], b[0], cin, sum[0], c[0]);
fulladd a1 (a[7], b[7], c[6], sum[7], cout);
endmodule.

Result:

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SIMULATION AND SYNTHESIS OF MUX AND PRIORITY ENCODER

Aim:
To simulate and synthesis of 4x1 MUX and 4x2 Priority encoder using Verilog HDL and to
perform timing and power analysis.

Software used:

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program:

Program for 4x1 MUX:

module mux41 (a, b, c, d, s, o);
input a, b, c, d;
input [1:0] s;
output o;
reg o;
always @ *
begin
case (s)
2b00 : o = a;
2b01 : o = b;
2b10 : o = c;
2b11 : o = d;
default : o=a;
end case
end
endmodule;

Program for 4x2 Priority encoder:

module pri (i,out, valid);
input [3:0] i;
output reg [1:0] out;
output reg valid;
always @ *
case (1)
i[3] : begin out = 2b11 ; valid = 1b1;end
default : begin out = 2b00 ; valid = 1b0;
end
endcase
endmodule.

Result:

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SIMULATION AND SYNTHESIS OF D-FLIPFLOP AND T-FLIPFLOP

Aim:
To simulate and synthesis of D Flip-flop and T Flip-Flop using Verilog HDL and to
perform timing and power analysis.

Software used:

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program for D Flip-Flop:

module dff1 (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always @ (posedge clk)
if (reset)
q <= 1b0;
else
q<= data;
endmodule

Program for T Flip-Flop:

module tff1 (t, clk, reset, q);
input t, clk, reset;
output q;
reg q, temp;
always @ (posedge clk)
if (reset)
q <= 1b0;
else
begin
temp <= (t & ~q) | (~t&q);
q<= temp;
endmodule

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SIMULATION AND SYNTHESIS OF 4-BIT RIPPLE COUNTER

Aim:
To simulate and synthesis of 4-bit ripple counter in behavioral model of Verilog HDL and
to perform timing and power analysis.

Software used:

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program:

module rc (a0, a1, a2, a3, cout, reset);
output a0, a1, a2, a3;
input cout, reset;
df f0 (a0, cout, reset);
df f1 (a1, a0, reset);
endmodule

module df (q, clk, reset);
input data, clk, reset;
output q;
reg q;
always @ (negedge clk or posedge reset)
if (reset)
q <= 1b0;
else
q<= (~q);
endmodule

Result:

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SIMULATION AND SYNTHESIS OF SEQUENCE DETECTOR USING MEALY
AND MOORE MODEL

Aim:
To simulate and synthesis Mealy and Moore model in Verilog HDL and to perform timing
and power analysis.

Software used:

Xilinx Spartan-3E

Device used:

XC3S250E FPGA320

Program:
Mealy model:

module mealy (clk, reset, state, nstate, in, out);
input clk, reset, in;
output out;
reg out;
output reg [2:0] state;
output reg [2:0] nstate;
parameter [2:0] S0 = 3b000;
always@(in or state)
case (state)
S0 : begin
if(in)
nstate = S1;
else
nstate = S0;
out=0;
end
S1 : begin
if(in)
nstate = S1;
else
nstate = S2;
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out=0;
end

S2 : begin
if(in)
nstate = S1;
else
nstate = S3;
out=0;
end
S3 : begin
if(in)
nstate = S4;
else
nstate = S0;
out=0;
end

S4 : begin
if(in)
nstate = S1;
else
nstate = S0;
out=1;
end
endcase

always@(posedge clk or posedge reset)
begin
if(reset)
state <= S0;
else
state <=nstate;
end endmodule.

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Moore model:

module moore (clk, reset, state, nstate, in, out);
input clk, reset, in;
output out;
reg out;
output reg [2:0] state;
output reg [2:0] nstate;

always@(in or state)
case (state)
S0 : begin
out=0;
if(in)
nstate = S1;
else
nstate = S0;
end
S1 : begin
out=0;
if(in)
nstate = S1;
else
nstate = S2;
end

S2 : begin
out=0;
if(in)
nstate = S1;
else
nstate = S3;
end
S3 : begin
out=0;
if(in)
nstate = S4;
else
nstate = S0;
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end

S4 : begin
out=0;
if(in)
nstate = S1;
else
nstate = S5;
end
S5 : begin
out=1;
if(in)
nstate = S1;
else
nstate = S0;
end
endcase

always@(posedge clk or posedge reset)
begin
if(reset)
state <= S0;
else
state <=nstate;
end endmodule.

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SIMULATION AND SYNTHESIS OF 8-BIT RADIX 4 BOOTH
MMULTIPLIER

Program:

module bootha (p, a, b);
input [7:0] a, b;
output [15:0] p;
wire [8:0] c;
wire [15:0] p1, p2, p3, p4;
assign {c[8:0]} = b[7:0]*2;
callbooth s1(p1[15:0], a[7:0], c[2:0]);
callbooth s2(p2[15:0], a[7:0], c[4:2]);
callbooth s3(p3[15:0], a[7:0], c[6:4]);
callbooth s4(p4[15:0], a[7:0], c[8:6]);
assign {p[15:0} = p1[15:0] + p2[15:0]*4 +
p3[15:0]*16 + p4[15:0] * 64;
endmodule

module callbooth (prod, a, y);
input [7:0]a;
output reg [15:0]w;
assign w[15:0] = {a[7], a[7], a[7], a[7], a[7],
a[7], a[7], a[7], a};
always @ (y)
begin
if (y== 3b000 || y == 3b111)
begin
prod <= 0;
end
if (y== 3b010 || y == 3b001)
begin
prod <= w;
end

if (y== 3b011)
begin
prod <= w*2;
end
if (y== 3b110 || y == 3b101)
begin
prod <= w*(-1);
end
if (y== 3b100)
begin
prod <= w*(-2);
end
end
endmodule

24

SIMULATION AND SYNTHESIS 4-BIT ALU

Program:

module alu3 (a, b, choi, clk, x,
out, c, z, s, ac, so);
input [3:0] a, b;
output c, z, s,ac,so;
input [3:0] choi;
input clk, x;
output [3:0] out;
reg [3:0] out;
reg[2:0] d;
reg [4:0] e;
integer I;
reg c;
reg ac;
reg z;
reg s;
reg so;
always@(posedge clk)
begin
case (choi)
4b0000 : begin
out = a+b;
e[4:0] = a[3:0] + b[3:0];
if (e[4] == 1)
c=i;
if (e[3:0] == 4b0000)
z=0;
if (e[3] == 1)
s=1;
d[2:0] = a[1:0] + b[1:0];
if (d[2] == 1)
ac=1;
end
4b0001: begin
out<= a-b;
e[4:0] = a[3:0] - b[3:0];
if (e[4] == 1)
if (e[3] == 1)
s=1;
e[2:0] = a[1:0] - b[1:0];
if (d[2] == 1)
ac=1;
end

4b0010: begin
out<= a&b;
c=1;
ac=0;
if (out[3:0] == 4b0000)
z=1;
if (out[3] == 1)
s=1;
end

4b0011: begin
out<= a|b;
c=1;
ac=0;
if (out[3:0] == 4b0000)
c=0;
ac=0;
if (out[3] == 1)
s=1;
end

4b0100: begin
out<= ~(a);
c=0;
ac=0;
if (out[3:0] == 4b0000)
z=1;
if (out[3] == 1)
s=1;
4b0101: begin
out<= a^b;
c=0;
ac=0;
if (out[3:0] == 4b0000)
z=1;
if (out[3] == 1)
s=1;
end

4b0110: begin
out<= (~a) + 1;
c<=(~a) + 1;
c=1;
if (c[3:0] == 4b0000)
z=1;
if (out[3] == 1)
s=1;
d[2:0] = a[1:0] + b[1:0];
if (d(2) ==1)
ac=1;
end

4b0111: begin
reg [3:0] temp;
for (i=0; i<4; i+1)
begin
tmp <= tmp<<1;
tmp [0] <=x;
end
so = tmp [3];
end

25

z=0;

end

4b1000: begin
reg [3:0] temp;
for (i=0; i<4; i+1)
begin
tmp <= tmp>>1;
tmp [3] <=x;
end
so = tmp [0];
end

4b1001: begin
reg [3:0] temp;
for (i=0; i<4; i+1)
begin
tmp [3] <=x;
tmp[2] =tmp [3];
tmp[1] =tmp [2];
tmp[0] =tmp [1];
end
out [3:0] <= tmp;
end

4b1010: begin
reg [3:0] tmp;
begin
tmp <= a;
s = tmp [3];
end

4b1011 : begin
for (i=0; i<4; i=i+1)
begin
out[i] = a[i];
end
end
endcase
end
endmodule

Result:

26

HARDWARE FUSING AND TESTING OF VERILOG CODE USING XILINX
CHOPSCOPE PRO ANALYZER

Aim:
To test the Verilog code for hardware fusing using Xilinx chip scope pro analyzer.

ChipScope Pro system diagram:

Xilinx chip scope pro Analyzer Design flow:

27

Procedure:

1. Click the project menu and then select new source.
2. Select Chip Scope Definition and Connection File and enter the file name, click Next and click
finish.
3. Double click your .cdc File.
4. Now your chip scope pro application will open, and then click next.
5. Mention the Number of Input Trigger Port and Mention the Trigger Width then Click Next.
6. Click Modify Connections and Select your clk_BUFGP then click Make connections.
7. Mention your Trigger input then click Make connections, click OK.
8. Click Return to Project Navigator and then click YES.
9. Right click the Analyze Design Using Chip scope and Click Run.
10. Connect your board using JTAG.
11. Open the Chip scope Pro Analyzer.
12. Click JTAG Chain and select Xilinx Parallel cable, Click Auto Detect Cable Type then click OK.
13. Your IC has been detected then clicks OK. Now Select My Device and click configure.
14. Click Select New File and Select your .bit file and click open.
15. Click Select New File Select your .cdc file and click open and then click OK.
16. Open the UNIT: 0 then Right click the Trigger setup and open the trigger setup.
17. Now the Trigger setup will be appear.
18. Right Click the Waveform and Open Waveform.
19. Right Click the Trigger setup => click trigger run mode =>click Repetitive, click RUN.
20. You can change the input in your board the corresponding output is show in your PC.

28

Result:

SCHEMATIC ENTRY AND SPICE SIMULATION OF MOS DIFFERENTIAL
AMPLIFIER

Aim:
To determine the gain, bandwidth, output impedance and CMRR of a MOS differential
amplifier.

Apparatus required:

Software used: OrCAD-PSpice

Procedure:

1. Select components in the place part
2. Paste the circuit components in the schematic window
3. Enter the values for each component
4. Creating a new simulation profile from the menu bar
5. Place the voltage or level marker in the input and output nodes
6. Then save the circuit
7. Run the program.

Circuit diagram:
29

Fig. MOS Differential Amplifier

Netlist:

Source Differential amplifier
V_V1 N00247 0
+SIN 0v 50mv 4k 0 0 0
Q_Q1 N00256 N00909 N00325 BC548A
Q_Q2 N00291 0 N00325 BC548A
R_R1 N00256 N00265 10k
R_R2 N00291 N00265 10k
R_R3 N00418 N00325 8k
V_V2 N00418 0 -15
V_V3 N00265 0 +15v
R_R4 N00247 N00909 100k

V1
FREQ = 4k
VAMPL = 50mv
VOFF = 0v
Q1
BC548A
Q2
BC548A
R1
10k
R2
10k
R3
8k
V2
-15
V3
+15v
0
0
0
0
R4
100k
V
V
30

Result:

STATIC TIMING ANALYSIS OF CMOS INVERTER USING CADENCE TOOL

Aim:
To design and simulate the CMOS inverter and observe the DC and transient responses
using cadence tool.

Schematic Entry:

Creating a new library:

1. In the library manager, execute File - New library. The new library form appears.
2. In the new library form, type my design lib in the name section.
3. In the field of directory section, verify that the path to the library is set to ~/Database /
Cadence- analog lab bl3 and click ok.
4. In the next technology file for new library form select option attach to an existing tech file
and click ok.
5. In the attach design library to technology file form, select gpdk180 form the cyclic field
and click ok.
6. After creating a new library you can verify it from the library manager.
7. If you right click on the my design lib and select properties, you wil find that gpdk180
library is attached as techlib to my design lib.

Creating a schematic cell view:

31

1. In the CIW or library manager, execute file new cell viw.
2. Setup the new file form as follows, Do not edit the library path file and the above might be
different from the path shown in your form.
3. Click ok when done the above setting. A black schematic window for the inverter design
appears.

Adding components to schematic:

1. In the inverter schematic window, click the instance fixed menu icon to display the add
instance form.
2. Click on the browse button. This opens up a library browser from which you can select
components and the symbol view.
3. After you complete the add instance form move your cursor to the schematic window and
click left to place a component.

4. This is a table of components for building the inverter schematic.

5. After entering components, click cancel in the add instance form or press ESC with your
cursor in the schematic window.

Adding pins to schematic:

1. Click the pin fixed menu icon in the schematic window. You can execute create pin or
press p.
2. Add pin form appears. Type the following in the ADD pin form in the next order leaving
space between the pin.

PIN NAMES DIRECTION
Vin Input
Vout output

LIBRARY NAME CELL NAME PROPERTIES/COMMENTS
gpdk180 PMOS For MO : model name
PMOS1,
W = wp, L =180n
32

3. Select cancel and then the schematic window enter window file or press the f bind key.

Adding wires to schematic:

1. Click the wire (narrow) icon in the schematic window.
2. In the schematic window click on a pin of one of your components as the first point for
your wiring. A diamond shape appears over the starting point of this wire.
3. Follow the prompts at the bottom of design window and click left on the destination point
for your wire. A wire is routed between the source and destination points.
4. Complete the wiring as shown in the figure and when done wiring press ECS key in the
schematic window to cancel wiring.

Saving the design:

Click the check and save icon in the schematic editor window observe CIW output for any
errors.

Building the inverter test design:
Creating the inverter test cell view:

1. In the CIW or library manager, execute file new cell view.
2. Setup the newfile as shown below.
3. Click ok when done. A blank schematic window for the inverter test design appears.
4. Using the components list and properties/ comments in this table build the inverter test
schematic.

LIBRARY NAME CELL VIEW NAME PROPERTIES/COMMENTS
My design lib Inverter Symbol
Analog lib Vpulse V1 = 0, v2 = 1, td = 0,
tr=tf=1ns, ton = 10ns, T=
20ns
Analog lib Vdc, gnd Vdc = 1.8v

5. Add the above components using create instance or by pressing I.
6. Click the wire (narrow) icon and wire your schematic.
7. Click create wirename or press c to name the i/p (vin) and output wires as in below
schematic.
8. Click on the check and save icon to save the design.

Analog simulation with spectra:
gpdk180 NMOS For M1 : model name
NMOS1,
W = 2u, L =180n
33

Starting the simulation environment:

1. In the inverter-test schematic window execute launch ADEL. The variable virtuoso
analog design environment (ADE) simulation window appears.

Choosing a simulator:

1. In the simulation window (ADE) execute setup simulator / directory / host.
2. In the choosing simulator form, set the simulator field to specra and click ok.
3. In the simulation window (ADE) execute the setup model libraries.
To complete, move the cursor and click ok.

Choosing Analysis:

1. Click the choose- Analysis icon in the simulation window (ADE).
2. The choosing analysis form appears.
3. To Setup the transient analysis.
a. In the analysis section select tron.
b. Set the stoptime as 200ns
c. Click at the moderate or enabled button and the bottom and then click apply.
4. To set for DC analysis
a. In the analysis section select DC.
b. Turn on save DC operating point.
c. Turn on the component parameters.
d. Double click the select Vpulse source.
e. Select the DC voltage in the select window parameter and click in the form start and
stop voltages are 0 to 1.8.
f. Select the enable button and click apply and then click ok.

Setting deign variables:

1. Click on the edit variable icon and its corresponding form appears.
2. Click copy from at the bottom of the form. The design is scanned. All variables formed in
the design are listed.In the few moments the wp variable name wp and enter.
Value (ixpr) 2u
3. Click change and notice the update and then click ok or cancel (in the editing design
variable window)

Selecting o/ps for plotting:

1. Execute the o/ps to be plotted -select on sschematic in the simulation window.
2. Follow the prompt at the bottom. Click on the o/p net vout input vin of the inverter. Press
esc with the cursor after selecting.

Running the simulation:

1. Execute the simulation Netlist and run in the simulation window to start the simulation on
the icon. This will create the netlist as well as run the simulation.
34

2. When the simulation finishes the transient DC plots automatically with the log file.

Result:

LAYOUT GENERATION AND PARASITIC EXTRACTION OF CMOS INVERTER
USING CADENCE TOOL

Aim:
To create the layout of CMOS inverter and extract the parasitic values using cadence tool.

Procedure:

Creating layout view of inverter:

1. From the inverter schematic window menu execute Launch lyout XL. A startup option
form appears.
2. Select create new option. This gives a new cell view form.
3. Check the cell name (inverter). Viewname (Layout).
35

4. Click ok from the newcell view form. LSW and a black layout window appears along with
schematic window.

Adding components to layout:

1. Execute connecting Generate All from source or click the icon in the layout editor
window. Generate the layout form appears. Click ok which imports the schematic
components into the layout window automatically.
2. Rearrange the components with in PR Boundary as shown.
3. To rotate a component select the component and execute Edit Properties. Now select the
degree of rotation from the property edit form.
4. Move a component, select the component and execute edit Move command.

Making connection:

1. Execute connectivity Nets show/hide selected incomplete Nets or click the icon in the
layout menu.
2. Move the mouse pointer over the device and click LMB to get the connectivity information
which shows the guide lines for the interconnections of the components.
3. From the layout window, execute create shape path / create wire or create shape
rectangle and select the appropriate layers from the LSW window and vias for making the
interconnections.

Creating contacts/vias:
Execute create-via to place different contacts.

Connection Contact Type
For metal 1 Polyconnection Metal 1 Poly
For metal 1 psubstrate connection Metal 1 psub
For metal 1 nwell connection Metal 1 - nwell

Saving the design:

Save your design by selecting file save to save the layout and layout appears.

Running a DC:

1. Open the inverter layout form the CIW or library manager if you have closed that. Press
shift f in the layout to display all the levels.
36

2. Select Assura Run DRC from layout window. The DRC form appears. The library and
cellname are taken from the current design window, but rule file maybe missing.
3. Seelect the technology as gpdk180. This automatically loads the rule file.
4. Click ok to start DRC.
5. A progress form will appear. You can click on the watch log file to see the log file.
6. When DRC finishes a dialog box asking you if you want to view your DRC results, and
click yes to view results of the run.
7. If there any DRC results in the design view layer window (VLW) and error layer window
(ELW) appears. Also the errors highlight in the design itself.
8. Click view summary in the ELW to find the details of error.
9. You can refer to the run file for info, correct all the DRC error and the Re-run the DRC.
10. If there are no errors in the layout then a dialog bo appears with no DRC errors found
written in it, click on close to terminate the DRC run.

Running LVS:

1. Select Assura Run LVS from the layout window. The Assura Run LVS form appears.
It will automatically load both the schematic and layout view of the cell and click ok.
2. The LVS begins and a progress form appears.
3. If the schematic and layout matches completely, you will get form displaying schematic
and layout match.
4. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this sum.
5. Click yes in the form.
6. In the LVS dialog box you can find the details of mismatches and you need to correct all
those mismatches and Re-Run the LVS.
7. In the filtering tab of the form enter power nets as vdd! , vss! And enter ground nets as gnd!
8. Click ok in the assura parasitic extraction form when done. The RCX progress form
appears, in the progress form click watch log file to see the output log file.
9. When RCX completes, a dialog box appears, informs you that Assura RCX run completed
successfully.
10. You can open the av-extracted view from the library manager and view the parasitic.

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