Input

Device
Output
Device CPU
Memory
3BCA5 Introduction to Microprocessor Unit -1
A microprocessor is an integrated circuit wic as te a!i"ity to mimic te processes
e#ecuted !y te processing unit$ %e integrated circuit accepts data as an input and process it
according to instruction code to generate an in&ormation$
'it te use o& input device( processing unit can get te input and a&ter processing te
input( processor wi"" give te in&ormation to te user wit te e"p o& output device$ %e integrated
circuit was a"so designed wic as an a!i"ity to store te data( instruction code and in&ormation$
%e processing unit reads instruction code &rom tis circuit and act according"y$
%e system wit centra" processing unit( input device( output device and memory can !e
visua"i)ed as sown in te &igure 1$1$ %e processor as an integrated circuit in a very sma"" si)e ence
re&erred Microprocessor
Data Data In&ormation In&ormation
Data Instruction Code
In&ormation
&ig 1$1 B"oc* diagram o& a Computer
Simple Model of Microprocessor
&ig 1$+ ,imp"e mode" o& Microprocessor
&ig 1$+ is a simp"e se-entia" digita" circuit wic consists od . !it counter( + decoders(
registers( switc contro" circuit( contro" unit aritmetic "ogic unit and !us$
Pro&$ Parima" /umar /$0
1.1 Counter
It is a . !it counter( wic starts counting &rom 1 and ends at 15 21111 3 11114$ %e counter is
driven !y te c"oc* signa" and te output is given to Decoder A troug . "ines re&erred as address !us$
1.2 Decoder A
It is a . 5 16 Decoder wic activate its output depending on te status o& inputs$ %e output o& te
decoder is used to se"ect one o& te registers witin te register array$
1.3 Register Array
&ig 1$3 0egister Array wit tri-state switces
%e a!ove &igure sows te register array consists o& si#teen 3 !it registers$ %e output o& a"" te
registers are connected to a common !us troug te Output 7na!"e 2O74 switc
%e output o& te Decoder A is used to active output ena!"e signa"s o& si#teen registers 20
1
- 0
15
4 $
At a time on"y one output o& decoder is activated according to te output signa"( so data o& on"y one
register is avai"a!"e on te common !us$
1.4 Common Bus
&ig 1$. Common Bus
%e 3 !it commin !us is connected to register A( register B and to te register I troug te switc$ I& te
switc is at position A ten te common !us is connected to register A or B register$ Oterwise it is
connected to register I$ %e switc position is contro""ed !y te switc contro" circuit$
1.5 Register
It is used to store data &rom te common !us
1.! Decoder B
It is a 3 5 8 Decoder$ %e input to tis decoder is troug register I$ I& switc is position B( te
instruction is decoded and used to se"ect appropriate contro" circuit &rom te contro" unit as
sown in ta!"e 1$1
D
2
D
1
D
"
Selected Control Circuit
1 1 1 MO9 A( C
1 1 1 MO9 B( C
1 1 1 ADD
1 1 1 ,UB
1 1 1 A:D
1 1 1 O0
1 1 1 ;OAD A
1 1 1 ;OAD B
%a!"e 1$1 Instructions wit teir codes
1.# Control $nit
It consists o& 8 contro" circuits$ %ese contro" circuits are used to generate signa"s wic se"ect te
operation o& A;U and activate input ena!"e signa" o& register A and register B$ At a time on"y one conto"
circuit is activated as se"ected !y decoder B output$ 7igt contro" circuits are
M%& A'C 5 %is contro" circuit generates contro" signa"s wic activate input ena!"e signa" &or register A and
output ena!"e signa" &or register C$ %e data &rom register C is moved to reigister A$
M%& B'C 5 %is contro" circuit generates contro" signa"s wic activate input ena!"e signa" &or register B and
output ena!"e signa" &or register C$ %e data &rom register C is moved to reigister B$
ADD ( %is contro" circuit generated contro" signa"s to per&orm addition operation in A;U$
< A => < B = ? < C =
S$B 5 %is contro" circuit generated contro" signa"s to per&orm su!traction operation in A;U$
< A = - < B = ? < C =
A)D 5 %is contro" circuit generated contro" signa"s to per&orm A:D operation in A;U$
< A = @ < B = ? < C =
%R 5 %is contro" circuit generated contro" signa"s to per&orm O0 operation in A;U$
< A = 9 < B = ? < C =
*%AD A ( %is contro" circuit generates contro" signa"s wic activate input ena!"e signa" &or register A$ It
a"so indicates switc contro" circuit to cange switc position to A$
*%AD B 5 %is contro" circuit generates contro" signa"s wic activate input ena!"e signa" &or register B$ It
a"so indicates switc contro" circuit to cange switc position to B$
1.# A*$
A;U ta*es input &rom register A and register B and processes it according to te operation se"ected !y te
contro" unit$ %e processed resu"t is stored in register C$
1.+ S,itc- Control Circuit
,witc contro" circuit is responsi!"e &or switc position$ It gets te input &rom ;OAD A( ;OAD B contro"
circuits$ I& any o& te input s is activated( it canges switc position to A( oterwise it o"d switc at position
B$
%perations
%e counter starts &rom )ero$ 'en counter output is )ero( decoder A se"ects te &irst register 0
1
&rom te register array and te data &rom te se"ected register 0
1
is avai"a!e on te common !us$
Initia""y switc is at position B ( so te data moves to register I and ten to Instruction decoder
2Decoder B4$ Decoder B decodes te instruction$ According to data( contro" unit se"ects te
operation and A;U per&orms te operation$
%e data se"ected &rom one o& te register decides te type o& te operation$ %e data wic decides te
operation is re&erred as Aoperation codeB or AOpCodeB$ As mentioned in ta!"e 1$1$ eac operation as its
own operationa" code$
In operation MO9 A(C and MO9 B(C te data is trans&erred &rom register C to register A or B respective"y$ In
operation ADD( ,UB( A:D and O0 te processing data is ta*en &rom register A and register B$ In operation
;OAD A and ;OAD B data &rom common !us is direct"y "oaded into register A and register B respective"y$ Cor
"ast + operations switc must !e in position A
A&ter eac operation is couter is incremented !y one( so tat te decoder se"ects te ne#t register$ Again
te data &rom se"ected register is avai"a!"e on te common !us and te process is repeated$
Different p-ases in t-e e.ecution process
Di&&erent pases in te e#ecution process are
1. /etc-
microprocessor p"aces te contents o& te program counter on te address !us and gets te instruction
code( opcode &rom te address memory "ocation$ %e microprocessor ten saves opcode in te instruction
register$
2. Decode
%e instruction &rom te instruction register is decoded wit te e"p o& instruction decoder to generate
appropriate contro" signa"s to e#ecute te instuction$
3. 0.ecute
Microprocessor generates appropriate contro" signa"s and e#ecutes te instruction$
0.ample to Add 2 num1ers.
Pro!"em 5 Add + num!ers 2 5 > +4
Procedure 5 1$ ;oad &irst num!er in register A
+$ ;oad second num!er in register B
3$ Add + num!ers in accumu"ator
,teps 5 1$ ;OAD A
+$ 5
3$ ;OAD B
.$ +
5$ ADD
7-uiva"ent Code in register5
1$ 111
+$ 111
3$ 111
.$ 111
5$ 111
Cirst step is to "oad te num!er in register A$ ,o( te opcode to do tis sou"d !e stored in register 0
1
and
te va"ue &or register A is stored in register array 0
1
$ ,imi"ar"y &or second va"ue$ %e opcode to "oad register
B is in register 0
+
and second va"ue is in register 0
3
$ %e opcode to add is stored in register 0
.
$
S203 1 ( %utput of C%$)20R is " 4""""5
In te !eginning te counter output is 1 211114$ %is output va"ue is given as input to . 5 16 Decoder 2A4
wic se"ects register 0
1
&rom register array$ %e va"ue in register is 111 wic is avai"a!"e in common !us$
%e Instruction decoder 23 5 8 Decoder B4 wi"" use tis data to se"ect te operation $ Data is 111$ ,o( it
se"ects ;OAD A operation$ ;OAD A operation wi"" ena!"e input &or register A and cange te switc position
&rom B to A 2&ig 1$.4$
S203 2 ( %utput of C%$)20R is 1 4"""15
Counter output is 1 211114$ %is output va"ue is given as input to . 5 16 Decoder 2A4 wic se"ects register 0
1
&rom register array$ :ow te va"ue 111 is avai"a!e on te common !us$ %is va"ue is moved direct"y to
register A !ecause switc is positioned at A and input to register A is ena!"ed$ A&ter te data trans&er switc
position is canged &rom position A to position B$
S203 3 ( %utput of C%$)20R is 2 4""1"5
Counter output is + 211114$ %is output va"ue is given as input to . 5 16 Decoder 2A4 wic se"ects register 0
+
&rom register array$ %e va"ue in register is 111 wic is avai"a!"e in common !us$ %e Instruction decoder
23 5 8 Decoder B4 wi"" use tis data to se"ect te operation $ Data is 111$ ,o( it se"ects ;OAD B operation$
;OAD B operation wi"" ena!"e input &or register B and cange te switc position &rom B to A$
S203 4 ( %utput of C%$)20R is 34""115
Counter output is 3 211114$ %is output va"ue is given as input to . 5 16 Decoder 2A4 wic se"ects register 0
3
&rom register array$ :ow te va"ue 111 is avai"a!e on te common !us$ %is va"ue is moved direct"y to
register B !ecause switc is positioned at A and input to register B is ena!"ed$ A&ter te data trans&er switc
position is canged &rom position A to position B$
S203 5 ( %utput of C%$)20R is 44"1""5
Counter output is . 211114$ %is output va"ue is given as input to . 5 16 Decoder 2A4 wic se"ects register 0
.
&rom register array$ %e va"ue in register is 111 wic is avai"a!"e in common !us$ %e Instruction decoder
23 5 8 Decoder B4 wi"" use tis data to se"ect te operation$ 9a"ue is 111$ ,o( it se"ects ADD operation wic
is to !e per&ormed !y A;U$ %e A;U adds te content o& register A and 0egister B and stores te &ina" va"ue
in register C$
0.ercise 6uestions.
1$ 'it a diagram e#p"ain te wor*ing o& simp"e microprocesor $
+$ 7#p"ain di&&erent pases in process e#ecution$
3$ 'at is microprocessorD 7#p"ain &ew o& its app"ications$
.$ ,o"ve te &o""owing !y writing its opcode and operations$
a$ + > 3
!$ . E 3
c$ 5 > 1 3 3
d$ + F 3 E G
e$ + H 3
&$ 3 I +
g$ + H . 3 3 > .
2-e +"+5 Microprocesor
Microprocessor 8185 is an 8 !it :MO, sing"e cip wit appro# 6+11 transistors on 166 J +++ mi"
cip contained in a .1 pin dua" in "ine pac*age$
/eatures of +"+5 microprocessor are
1$ It is an 8 !it microprocessor$ It can accept( process and provide data simu"taneous"y$
+$ It as 16 !it address !us$ %e "ower 8!it address !us 2A1 to AG4 and 8 !it data !us 2D1 to DG4 are
mu"tip"e#ed and used as address "ines$ An address "atc is used to separate address and data "ines$
3$ As it is aving 16 address "ines( it can access 2+164 6./ memory "ocations$
.$ It re-uires a signa" >59 power supp"y and operates at 3$+ MKL sing"e pase c"oc* wit ma#imum
c"oc* &re-uency 6 MK) and minimum c"oc* &re-uency 511 *K)$
5$ It as on cip c"oc* generator$ %is interna" c"oc* gererator re-uires tuned circuit$ %e interna" c"oc*
generator divides osci""ator &re-uency !y + and geneates c"oc* signa"( wic can !e used to
syncroni)e e#terna" devices$
6$ It supports G. instruction sets$
G$ %e A;U per&orms 8!it addition wit and witout carry( 16 !it addition( + digit BCD addition( 8 !it
su!traction wit and witout !orrow and 8 !it "ogica" operations "i*e O0( A:D( 7J-O0( comp"ement
M !it si&t operations$
8$ It provides 8!it accumu"ator( &"ag register( si# 8-!it genera" purpose register arranged in pairs5 BC(
D7( K;( + si#teen !it specia" purpose registers and instruction register$
N$ It as an a!i"ity to sare system !us wit Direct Memory Access contro""er$ %is &eature a""ows to
trans&er "argr amount o& data &rom IIO device to memory or vice versa$
11$ It provides 5 ardware interrupts 5 %0AP( 0,% 5$5( 0,% 6$5( 0,% G$5( I:%0$
11$ It as seria" IIO contro"s "i*e ,ID and ,OD &or seria" communications$
1+$ It provides signa"s to contro" te !us cyc"es "i*e IOIOP Q0D and '0
13$ %e e#terna" ardware can detect wic macine cyc"e is e#ecuted !y te microprocessor using
status signa"s "i*e IOIM( ,
1
and ,
1
Arc-itecture of +"+5 Microprocessor
fig 2.1 Arc-itecture of +"+5 microprocessor
It consists o& various &unctiona" !"oc*s$ %ey are
1. Registers
%e registers can !e c"assi&ied as
a. 7eneral purpose registers
It as 6 genera" purpose registers B(C(D(7(K(; wic can !e used as a 8 !it registers or in pairs as 16
!it registers BC( D7 and K;$ 'en used in pairs te iger order !yte resides in te &irst register and te
"ower order !yte in te second register$ 7#amp"e Kiger order in B and "ower order !yte in C$
%e specia" K; pair &unctions as a pointer to memory "ocation$ %ese registers is a"so ca""ed scratc
pad registers$ Bus access is not re-uired to store and "oad onto tese registers$ %se can !e used to store
intermediate resu"ts$
1. 2emporary registers
i. 2emporary data registers
%ese registers are nor accesi!"e$ It is interna""y used &or e#ecution o& aritemtic and "ogica"
operations$ %e A;U as + inputs$ One input is supp"ied !y te accumu"ator and anoter &rom te data
registers$
ii. 8 and 9 registers
%ese are 8!it registers wic cannot !e accessi!"e$
%e CA;; instruction is used to trans&er te program
counter to a su! program$ %is instruction puses te content o&
program counter to te stac* and "oads te &irst instruction
address o& te su!routine in to te program counter$ %e given
address is temporari"y stored in ' nad L register and p"aced on
te !us$
During JCKS instruction te data in K M ; is trans&erred to D M 7 register respective"y$ At te time
o& e#cange ' and L registers are used to temporari"y store te data$
c. Special purpose registers.
i. Register A 4Accumulator5
It is a tri state 8 !it register$ It is e#tensive"y used in arirtmetic( "ogic( store "oad and IIO
operations$ %e resu"t o& aritmetic and "ogica" operations are stored in te register A$ It is a"so ca""ed as
accumu"ator$
ii. /lag register
In a 8 !it register( 5 !its carry signi&icant in&ormation in te &orm o& &"ags$ %ey are
D
G
D
6
D
5
D
.
D
3
D
+
D
1
D
1
, L J AC J P J CT
Sign flag 4S5 5 %e DG !it is set 214 a&ter te e#ecution o& aritmetic or "ogica" operations i& te resu"tant is a
negetive num!er$ Cor positive num!ers te va"ue wi"" in DG is 1$
9ero flag 495 ( In te A;U( a&ter an operation i& te resu"t is )ero te D6 !it is set 214$ %e &"ag a"so sets to
)ero i& a certain register content !ecomes )ero a&ter an increment or decrement operation in tat particu"at
register$
Au.illary carry flag 4AC5 ( %is &"ag is set i& tere is an over&"ow out o& !it D3 to D.$ %is &"ag is used in BCD
operations and is not accessi!"e$
3arity flag 435 ( A&ter anaritmetic or "ogica" operation( i& te resu"t as even num!er o& 1Us 2even parity4 $
te D+ !it is set$ I& te parity is odd te parity !it is reset$
Carry flag 4C:5 ( %e &"ag is set i& tere is an over&"ow out o& !it G$ %e carry &"ag a"so serves as a !orrow &"ag
&or su!traction$
iii. nstruction register
%e processor &etces opcode &rom te memory 2It p"aces an address on te address !us and
memory responds !y p"acing data stored at tat particu"ar "ocation4$ %e processor stores tis opcode in a
register ca""ed instruction register$ %is opcode is ten moved to Instruction decoder to se"ect one o& te
+.6 operations according to te opcode$
D. 1! 1it registers
i. 3rogram Counter
Program counter is a 16 !it specia" purpose register$Consider tat an instruction is !eing e#ecuted
!y processor$ As soon as te A;U &inises e#ecuting te instruction( te processor "oo*s &or te ne#t
instruction to !e e#ecuted$ ,o( tere is a necessity &or o"ding te address o& te ne#t instruction to !e
e#ecuted in order to save time$ %is is ta*en care !y te program counter$ A program counter stores te
address o& te ne#t instruction to !e e#ecuted$ Microprocessor increments te program counter depending
on te e#ecuted instruction and points to te memory address o& te ne#t instruction tat is going to !e
e#ecuted$
ii. Stac; 3ointer
,tac* pointer is a 16-!it specia" purpose register wic is used as a memory pointer$ A stac* is
noting !ut te portion o& 0AM 20andom access memory4$ ,tac* pointer maintains te address o& te "ast
!yte tat is entered into stac*$ 7ac time wen te data is "oaded into stac*( ,tac* pointer gets
decremented$ Converse"y it is incremented wen data is retrieved &rom stac*$
2. Arit-metic *ogic $nit
It is a 8 !it mu"ti operationa" com!inationa" "ogic circuit$ It per&orms aritmetic and "ogica"
operations "i*e A:Ding( O0ing( 7J-O0ing(ADDI%O:(,UB%0AC%IO:(etc$ It is not accessi!"e !y user$ It is
a"ways contro""ed !y timing and contro" circuits$ It provides status or resu"t o& &"ag register$
%e A;U contains &o""owing !"oc*s5
Adder5 It per&orms aritmetic operations "i*e addition( su!traction( increment( decrement( etc$ %e resu"t
o& operation is stored into accumu"ator$
S-ifter5 It per&orms "ogica" operations "i*e rotate "e&t( rotate rigt( etc$%e resu"t o& operation is again stored
into accumu"ator$
Status Register5 A"so *nown as &"ag register$ It contains a no$ o& &"ags eiter to indicate conditions arising
a&ter "ast A;U operation or to contro" certain operations$
3. nstruction Decoder
%e instruction decoder decodes te opcode received &rom te instruction register$ Depending
upon te nature o& te instruction it gives timing and contro" signa"s wic contro"s te register ( te data
!u&&er( A;U and te e#terna" peripera" signa"s$ It a"so gives te in&ormation a!out wic macine cyc"e is
current"y e#ecuting in te encoded &orm on te ,
1
( ,
1
and IOIM "ines$
4. Address Buffer
It is an 8 !it unidirectiona" !u&&er$ It is used to drive e#terna" ig order address !us$ 2A
15
3 A
8
4
5. Address < Data Buffer
It is an 8 !it !idirectiona" !u&&er$ It is used to drive mu"tip"e#ed addressIdata !us i$e( "ow order
address !us 2A
G
3 A
1
4 and data !us 2D
G
3 D
1
4$
!. ncrement or decrement address latc-
It is a 16 !it register used to increment or decrement te content o& program counter or stac*
pointer as a part o& instruction e#ecution$
#. nterrupt control
Consider a microprocessor is e#ecuting te main program$ :ow wenever te interrupt signa" is
ena!"ed or re-uested te microprocessor temporari"y stops te e#ecution o& main program and trans&ers
contro" to speci&ic specia" routine *nown as VInterrupt ,ervice 0outineV2I,04$ A&ter te comp"etion o&
re-uest( te contro" goes !ac* to te main program$
%ere are 5 interrupt signa"s present in 8185$%ey are5
I$ I:%0
II$ 0,% G$5
III$ 0,% 6$5
I9$ 0,% 5$5
9$ %0AP
%0AP is a :O:-MA,/AB;7 interrupt contro" and oter tree are mas*a!"e interrupts$ A non-
mas*a!"e interrupt is an interrupt wic is given te igest priority in te order o& interrupts$ :on-
mas*a!"e interrupt cannot !e disa!"ed !y programmer at any point o& time$ 'ereas( te mas*a!"e
interrupts can !e disa!"ed and ena!"ed using 7I and DI instructions$ Among te mas*a!"e interrupts 0,% G$5
is given te igest priority a!ove 0,% 6$5 and "east priority is given to I:%0$
+. Serial % control
In seria" communication one !it is trans&erred at a time over te sing"e "ine$ In tis processor( seria"
IO contro" provides two "ines ,ID and ,OD &or seria" communication$ %e seria" output data "ine 2,ID4 is used
to send te data and seria" input data "ine 2,OD4 is used to receive te data seria""y$
=. 2iming and control circuitry.
%e operation in microprocessor are syncroni)ed using te c"oc* signa"s$ A"ong wit te contro" o&
&etcing and decoding operations and generating appropriate signa"s &or instruction e#ecution( contro"
circuitry a"so generates signa"s re-uired to inter&ace e#terna" devices wit te processor$
3in definition of +"+5
&ig 3$1 8185 Pin Diagram &ig 3$+ Cunctiona" pin diagram
%e signa"s o& 8185 can !e c"assi&ied into G groups according to teir &unctions$
1$ Power supp"y and &re-uency signa"s
+$ Data !us and address !us$
3$ Contro" Bus$
.$ Interrupt signa"s$
5$ ,eria" IIO signa"s$
6$ DMA signa"s$
G$ 0eset signa"s
1. 3o,er supply and fre6uency signals
a. &
CC 5
It re-uires a >59 power supp"y$
1. &
SS (
Sround re&erence
c. >
1
and >
2
( A tuned circuit is connected to tese pins$ %e interna" c"oc* generator divides
osci""ator &re-uency !y +$
d. C*? %$2 ( %is &re-uency is a"& te osci""ator &re-uecy$ %ese signa"s are used as a system c"oc*
&or ote devices$
2. Bus
a. AD
"
to AD
#
( %e 8 !it data !us 2D
1
to D
G
4 is mu"tip"e#ed wit te "ower a"& o& te 16 !it 2 A
1
to
A
G
4address !us$ During te &irst a"& o& te time cyc"e ( "east signigicant 8 !its o& IIO or memory on te !us$
During ne#t time cyc"es tese "ines are used as !idirectiona" to pass te data$
1. A
+
to A
15
( %ese "ines are e#c"usive"y used to tran&er address$ %ese are unidirectiona" !uses$
3. Control and Status signals
a. A*0 4Address *atc- 0na1le5 ( It is an signa" used to give in&ormation o& content in AD1-ADG$ It is a
positive going pu"se generated wen a new operation is started !y microprocessor$ 'en time cyc"e goes
ig it indicates tat AD1-ADG are address and 'en it is "ow it indicates tat te "ine contents data$
1. RD and 8D ( %ese signa"s are !asica""y used to contro" te direction o& te data &"ow !etween
te processor and memory or IIO devices$ A "ow on 0D indicates tat te data must !e read &rom se"ected
device$ A "ow on 'D indicates tat te data must !e written onto te se"ected device$
c. % < M ' S
1
and S
1
( %is is an output status signa" used to give in&o o& operation to !e per&ormed
wit memory or IIO devices$'en IOIM2!ar4?1(te uP is per&orming memory re"ated operation$'en
IOIM2!ar4?1(te uP is per&orming IIO device re"ated operation$%is signa" separates memory and IIO
devices$,1 and ,+ indicates te type o& macine cyc"e in progress
%peration S" S1
OPCode Cetc 2Instruction read &rom memory4 1 1
0ead 2data read &rom memory4 1 1
'rite 1 1
Ka"t 1 1
d. R0AD: ( %is is an active ig input contro" signa"$ It is used !y microprocessor to detect weter
a peripera" as comp"eted 2or is 0eady &or4 te data trans&er or not$ %e main &unction o& tis pin is to
syncroni)e s"ower peripera" to &aster microprocessor$ I& ready pin is ig te microprocessor wi""
comp"ete te operation and proceeds &or te ne#t operation$ I& ready pin is "ow te microprocessor wi""
wait unti" it goes ig$
4. nterrupt Signals
It as 5 ardware interrupt signa"s$
1. 2rap( %is is an active ig( "eve" and edge triggered(non-mas*a!"e iger priority interrupt$
'en %0AP is active( te program counter o& microprocessor Wumps automatica""y at address 11+.$
2. RS2 #.5'RS2 !.5 and RS2 5.5( %ese are active ig( edge 20,% G$54 or "eve" 20,% 6$5 and 0,% 5$54
triggered mas*a!"e interrupts$%e priorities o& tese are %0AP( 0,% G$5( 0,% 6$5( and 0,% 5$5$ 'en 0,% G$5(
0,% 6$5 and 0,% 5$5 are active( te program counter Wumps automatica""y at address 113C( 113.( 11+C
respective"y$
3. )2R and )2A( I:%0 is an active ig( "eve" triggered genera" purpose interrupt$ 'en I:%0 is
active microprocessor generates an interrupt ac*now"edge signa" I:%A$ I& I:%0 is active( te Program
Counter 2PC4 wi"" !e restricted &rom incrementing and an I:%A wi"" !e issued$ During %is cyc"e a 07,%A0%
or CA;; instruction can !e inserted to Wump to te interrupt ,ervice routine$ %e I:%0 is ena!"ed and
disa!"ed !y so&tware$ It is disa!"ed !y 0eset And immediate"y a&ter an interrupt is accepted$
5. Serial <% Signals
a. SD ( %is is an active ig ,eria" input data "ine te data on tis "ine is "oaded into accumu"ator
!it G wenever a 0IM instruction is e#ecuted$ %is signa" is used to accept seria" data !it !y !it &rom te
e#terna" device$
1. S%D ( %is is an active ig ,eria" output data "ine$ %e output ,OD is set or reset as speci&ied !y
te ,IM instruction$ %is signa" ena!"es te transmission o& data seria""y !it !y !it to te e#terna" device$
!. DMA Signal
a. @%*D ( KO;D indicates tat anoter Master is re-uesting te use o& te Address and Data Buses$
%e CPU( upon receiving te Ko"d re-uest( wi"" witdraw te use o& !uses as soon as te comp"etion o& te
current macine cyc"e$ Interna" processing can continue$ %e processor can regain te !uses on"y a&ter te
Ko"d is removed$ 'en te Ko"d is Ac*now"edged( te Address( Data( 0D( '0( and IOIM "ines are tristated$
1. @*DA ( KO;D AC/:O';7DS7 indicates tat te CPU as received te Ko"d re-uest and tat it
wi"" witdraw te !uses in te ne#t c"oc* cyc"e$ K;DA goes "ow a&ter te Ko"d 0e-uest is removed$ %e CPU
ta*es te !uses one a"& c"oc* cyc"es a&ter K;DA goes ;ow$
#. R0S02 Signals
a. R0S02 ) ( 0eset sets te Program Counter to )ero and resets te Interrupt 7na!"e and K;DA C"ip-
&"ops and ma*es address( data and contro" "ines tristated$ %e CPU is e"d in te reset condition as "ong as
0eset is app"ied$ A&ter reset status o& interna" register and &"ag are unpredicta!"e$ A&ter reset
microprocessor starts e#ecuting te instruction &rom 1111K onwards$
1. R0S02 %$2 ( %is is an active ig output signa" used to indicate CPU is !eing reset and can !e
used as a system 07,7%$ %e signa" is syncroni)ed to te processor c"oc*$ %is signa" is a"so used to reset
te peripera"s once te microprocessor is reset$ It is an ac*now"edgement signa" to 07,7% I: $
0.ercise Auestions
1$ 7#p"ain wit diagram te arcitecture o& microprocessor 8185$
+$ 7#p"ain wit diagram te pin diagram o& microprocessor 8185$ 7#p"ain te purpose o& eac pin in
8185 microprocessor$
3$ 'y AD1 to ADG "ines are mu"tip"e#ed$
.$ 'at are te &unctions o& an accumu"ator$
5$ Kow are interrupts c"assi&ied in 8185$