CESC 4095

TRINITY TERM 2012

FIRST PUBLIC EXAMINATION
ELECTRONIC & INFORMATION ENGINEERING (PAPER P2)
Preliminary Examination in Engineering Science
Thursday, 7th June 2012 2.30pm 5.30pm
Attempt ALL questions in Section A and FOUR questions in Section B.
Use separate answer booklets for Sections A and B.
Start each question on a new page.
DO NOT TURN THIS PAGE UNTIL TOLD YOU MAY DO SO
Note that:
Permitted calculator series are: Casio fx-83, Casio fx-85, Sharp EL-531.
A copy of Engineering Tables & Data (HLT) is provided.
Questions in Sections A and B carry 5 and 15 marks respectively.
The likely distribution of marks within B questions is given in the margin.
1
P2 2012
SECTION A
1. Derive the Thvenin equivalent of the circuit in Figure 1 viewed from the terminals A and B.
4
2
1V
2
1.5A
A
B
Figure 1
2. The voltage source V
S
in the circuit of Figure 2 has an angular frequency . Derive an
expression for the capacitance C in terms of R, L and that would cause the total current
I to be in phase with V
S
.
For this condition, and assuming I
1
lags V
s
by 60

, sketch and label a phasor diagram showing

I
1
, I
2
and I, using V
S
as the reference phasor.
V
S
I
I I
C
R
L
1 2
Figure 2
3. Sketch and label a diagram showing both the magnitude and phase parts of the Bode diagram
for the transfer function
H(j) =
j
1 0.1j
.
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P2 2012
4. Show that the transfer function of the circuit in Figure 3 can be written as
V
2
V
1
=
j/CR

2
+ 2j/CR + 1/LC
.
Derive an expression for the Q-factor of the circuit.
R
R
L
V V
1 2
C
Figure 3
5. Assuming the operational amplier is ideal, determine an expression for V
2
in terms of V
1
for
the circuit of Figure 4.
If the supply rails are at 15 V, determine the minimum and maximum values of V
1
which
avoid clipping of the output.
9k
10k
90k
90k
V
V
1
+5V
2
V
+V
Supply
Supply
Figure 4
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P2 2012
6. The BJT in the circuit of Figure 5 has a current gain of .
Sketch and label the small-signal equivalent circuit. Hence, stating any assumptions you
make, show that the output resistance is R
out
h
ie
/.
+V
CC
R
A
E
R
in
V
V
out
R
B
Figure 5
7. The intrinsic carrier concentration in pure Si is 1.4 10
16
m
3
. A sample of pure Si is n-type
doped to a concentration N
D
= 10
21
m
3
.
Suggest a suitable dopant element. For the doped material, estimate (i) the volume density of
holes and (ii) the conductivity given that the electron mobility is 0.14 m
2
s
1
V
1
.
8. Using a Karnaugh map, show that the following expression
X = A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D + A.B.C.D
can be written as the sum of two products.
By applying de Morgans theorem, show that a product P.Q can be implemented using a
single NOR gate. Hence show that X can be implemented using three NOR gates, and draw
and label the circuit.
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SECTION B
1. (a) For the circuit of Figure 6 show that the current I owing out of the op-amp is given by
I =
V
in
R
1
+ jL
1
.
[4 marks]
(b) Hence show that the voltage gain of the circuit is of the form
V
out
V
in
=
R
X
+ jL
X
R
1
+ jL
1
and determine expressions for R
X
and L
X
in terms of R
1
, R
2
, L
1
and L
2
.
[5 marks]
(c) Sketch both the magnitude and phase parts of the Bode diagram for the ampliers
voltage gain when L
1
/R
1
= 10 L
X
/R
X
.
[4 marks]
(d) Determine the relationship between R
1
, R
2
, L
1
, and L
2
, that would eliminate the
frequency dependence of the voltage gain.
[2 marks]
2
L
R
2
1
L
R
1
V
in
V
out
I
Figure 6
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P2 2012
2. (a) List the three key properties of an ideal operational amplier
[3 marks]
(b) Figure 7 shows a lter formed from two op-amps and a simple network of components.
What is the purpose of the two op-amps in this circuit?
[2 marks]
(c) Show that the transfer function for the lter is
V
out
V
in
=
sL/R
(1 + sRC)(1 + sL/R)
.
[4 marks]
(d) An input signal V
in
(t) consisting of a 1 V high unit step is applied to the circuit.
Determine an expression for V
out
(t) when L = 1 H, R = 1 , and C = 0.1 F, and sketch
V
out
(t) for 1 < t < 1 s.
[6 marks]
V
in
V
out
L
C
R
R
Figure 7
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P2 2012
3. (a) For the coupled coils shown in Figure 8(a) write down the two equations relating V
1
and
V
2
to I
1
, I
2
, L
1
, L
2
and M. State what is meant by perfect coupling.
[3 marks]
(b) The autotransformer shown in Figure 8(b) is made using two identical coils whose self-
inductances are both L
0
and which are perfectly coupled.
Find the ratio V
2
/V
1
for the case when the load resistance is removed.
[4 marks]
(c) With the load resistance connected, current I
2
is drawn from the midpoint of the circuit.
Write down the mesh current equations describing this circuit, and solve them to nd
the new ratio V
2
/V
1
.
[5 marks]
(d) Explain the result for V
2
/V
1
found in part (c) with reference to the behaviour of coupled
inductors.
[3 marks]
V
1
I
1
I
2
V
2
M
L L
1 2
I
1
L
0
V
1
I
2
V
2
M
R
L
L
0
(a) (b)
Figure 8
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P2 2012
4. (a) What is the voltage drop across a perfect current source?
[1 mark]
(b) For the circuit of Figure 9:
(i) Which mesh current can be determined immediately?
(ii) What is the relationship between the other two mesh currents?
(iii) Write down the mesh current equations for these two unknown currents and the
unknown voltage drops.
[7 marks]
(c) Solve the equations found in part (b) to nd the three currents and the open-circuit output
voltage V
out
.
[4 marks]
(d) Determine the Thvenin equivalent of this circuit viewed from the terminals A and B.
[3 marks]

i
b
i
c
i
a
3A
10

4V
2A
7
8
16
6
V
out
A
B
Figure 9
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P2 2012
5. The npn transistor in the amplier circuit of Figure 10 has characteristics
= 100, V
BE
= 0.7 V, V
CE
(min) = 0.5 V.
(a) We require the quiescent collector current to be I
C
= 10 mA and the DC output voltage
V
out
to lie half way between the supply rail voltages.
Stating any assumptions you make, determine suitable values for R
C
and R
B
when
R
E
= 200 .
[3 marks]
(b) Draw and label the small-signal equivalent circuit for this amplier. You should denote
the combined impedance of R
E
and C
E
as Z
E
. The capacitor C
E
may not be considered
a short.
[4 marks]
(c) (i) Under the two conditions that ( + 1)

Z
E

h
ie
and 1, show that the
small-signal voltage gain of the amplier is
G(j)
R
C
(R
C
+ R
B
)

1
R
B
Z
E

.
(ii) Hence show that
G(j)
R
C
R
E
(R
C
+ R
B
)

(R
B
R
E
) + jR
E
C
E
R
B

.
[8 marks]
V
out
E
C
in
C
V
in
E
R
B
C
R
R
+12V
0V
Figure 10
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P2 2012
6. (a) CMOS logic is based on MOSFETs made from p- and n-type semiconductors.
Figure 11(a) shows a cross-section through a MOSFET made on a p-type substrate.
Identify the three sections labelled by (i), (ii) and (iii) in the gure, and describe the
rles they play in the operation of the device.
[6 marks]
(b) Figure 11(b) shows the CMOS circuit for a simple gate with inputs A and B, and output
C.
Write out the truth table for the operation of each MOSFET, and determine the logic
function that this gate implements.
[4 marks]
(c) Using the same types of MOSFETS as shown in Figure 11(b), draw the conguration
which implements the NAND logic function
C = A B
[5 marks]
Source (S)
0V
5V
n+ n+
Drain (D)
0 or 5V
Gate (G)
ptype substrate iii
i
ii
A
B
C
+5V
0V
(a) (b)
Figure 11
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P2 2012
7. (a) Figure 12(a) shows a nite state machine made using a PROM and three D-type ip
ops. Explain the purpose of each of these components in the machine and describe
their action on receipt of a clock pulse.
[4 marks]
(b) A nite state machine is to be designed to generate the three pulse streams A, B and C
shown in Figure 12(b).
(i) Determine the number of D-type ip ops that are required.
(ii) Determine the number of memory locations required in the PROM.
(iii) Draw your design, and write down a table showing the PROM contents for each
memory location.
[6 marks]
(c) It is now required that the user be able to reverse the sequence using a single switch.
Describe how you would achieve this, draw the new conguration for the PROM, ip
ops and switch, and show how you would modify the PROM contents.
[5 marks]
D Q
D Q
D Q
D2
A2
A1
A0
D0
D1
CLK
PROM
B
C
CLK
A
(a) (b)
Figure 12
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