Lab 08: SR Flip Flop Fundamentals:

Slide 2 NOR Gate SR Flip Flop.

Slide 3 SR Flip Flop.

Slide 4 SR Flip Flop with a positive edge clock:

Slide 5 SR Flip Flop with a negative edge clock:

Slide 6 Flip Flop waveform diagrams:

Lab 08: NOR Gate SR Flip Flop :
The cross-coupled NOR gates creates an SR Flip Flop. Flip Flops are the
basic elements used in computer memory. The S input is called Set. The R
input is called Reset.

01
01 S R Output
R 00
1 Q settles at
10
0110 Q logic 0
Q changes 0 0 No Change Q stays at
Both
from outputs
1 to 0.
Q changes 0 1 0
settle
Calledto 0.1. Reset: Q changes to 0
from 0 the
to 1 0
01
0 This breaks
reset mode! Set: Q changes to 1
11
001
0 Called the
Q the 1 1
00
1 Set mode! Ambiguous : Not
S definition.
This allowed!
condition is
Output Q and Q are by definition always opposite
not allowed to each other. If Q=1 then
Q =0.
Behaviour Table: Logic gates are defined by Truth Tables. Flip Flops are defined by
behaviour tables. Two different names for tables that do essentially the same job. To
generate the behaviour table you must assume an initial condition at output Q. This is
necessary because the outputs are wired to the inputs. This creates a feedback path
that can only be analyzed when a starting point is assumed.
Start
Next with
S,R =S,R
0,1=: 0,0
1,0
1,1 The:analysis
The analysis
procedure
procedure
worksworks
as follows:
as follows:
1-Place
1-Placethe
theinitial
initialconditions
conditionsatatoutput
outputQQon onthe
thediagram.
diagram.Assume
AssumeQQ=0.
=1.
=0.
2-Place
2-Placethe
theinput
inputconditions
conditionsat atSSand
andR.R.
3-Analyze
3-Analyzethe
thetop
topNOR
NORgate
gateand
andrecord
recordQ.Q.
4-Analyze
4-Analyzethe
thebottom
bottomNORNORgate
gateandandrecord
recordQ.Q.
5-Repeat
5-Repeatsteps
steps33and
and44until
untilQQand
andQQsettle.
settle.
Slide #2
Lab 08: SR Flip Flop :
Cross-coupled NOR gates create an SR Flip Flop. It is easy to remember the
operation of an SR flip flop using only the symbol without repeatedly
analyzing the cross coupled NOR gate system.
The S input is called SET the R input is called reset.
They are both active high. Active high means that S =1
10
0 S Q 10
01 Output sets the flip flop (S =0 does not set). R =1 resets the flip flop
Assume
Output
Q reset
does
reset
SETs
Q
SETs
not
(R =0 does not reset).
starts
: :Q:Qchange
:Q
=1.
Q
=1.
at
=0.
=0.
0.
00
1 R Q 01
10 SET means set output Q to “1”.
RESET means reset output Q to “0”.
Symbol When S =0 and R =0 then Q does not change. Q holds its
logic level (1 or 0). It is equivalent to not issuing either the
: :Hold
S=1 Hold
: R=1
Set
Mode
Mode
Mode
: :: : set or the reset command.
reset Mode :
When S =1 and R =1 then Q is ambiguous. Both Q and Q outputs go to the same logic level which
breaks the definition of a flip flop. You can think of it this way … S =1 says SET and R =1 says reset.
The flip flop does not know whether the output should be Q =1 or Q =0. S=R=1 should never be
used!
There is a second variety of SR flip flop that uses an active low S and R inputs. The internal system is
cross coupled NAND gates. Active low means that S =0 sets the flip flop (S =1 does not set). R =0
resets the flip flop (R =1 does not reset).
When S =1 and R =1 then Q does not change. Q holds its
0 logic level (1 or 0). It is equivalent to not issuing either the
1 S Q 1 Output
0 Assume
Q doesSETs
not
Q set or the reset command.
starts
: Qchange
=1.
at 0.
1 When S =0 and R =0 then Q is ambiguous. The flip flop
0
1 R Q 0
1
does not know whether the output should be Q =1 or Q
=0. S=R=0 should never be used!
S=0 ::reset
SetMode
Mode
R=0
: HOLD ::
Mode
:
Slide #3
Lab 08: SR Flip Flop with a Positive Edge Triggered Clock Input :
A Positive EDGE triggered flip flop has a new input called clock. The clock
requires a transition from 0 to 1 in order that S and R controls output Q.
Holding a constant logic 1 or a constant logic 0 at the clock input does not
allow SR to change output Q.
An edge triggered clock is identified with “>Clk” on the symbol.
1 S Q 0 Assume
1 Output SETs
Q A transition from 0 to 1 at “>Clk” is required in order for the
>Clk starts
: Q =1.
at 0. flip flop to respond to S and R. This is called a” Positive Edge”.
0 R Q 1
0 Watch the animation to see how you would set the flip flop.

Holding “>Clk” at logic 1 will not result in S and R controlling Q.

SR Flip Flop with
Only the 0 to 1 transition at “>Clk“ causes the output Q to
edge triggered clock
change.
S=1 : Set Mode :
Inside the SR Flip Flop with Positive Edge Triggered Clock:

The clock signal is applied to the input.

1/0 S
2 1/0
0 S Q
>Clk 0 The NOT gate delays the signal because
1 it has a propagation delay. Propagation
1/0
0 R delay is the reaction time of the inverter.
1/0 R 3 Q
Let’s use 3 to 10 nanoSec.

3 to 10 nanoSec
delay.
During the 3 to 10 nanoSec interval, AND gate #1 outputs a 1. AND gates #2 and #3 transfer the
logic levels to internal SR and Q responds.
After the 3 to 10 nanoSec interval AND gate #1 outputs a 0. AND gates #2 and #3 transfer the
logic 0 to internal SR and Q holds(S=R=0 is Hold mode). To re-clock the flip flop you need
another positive edge. Clock must return to 0 and re-change back to 1.
Slide #4
Lab 08: SR Flip Flop with a Negative Edge Triggered Clock Input :
A negative edge triggered flip flop requires a transition from 1 to 0 at at the
clock input in order for the flip flop to respond to S and R. This is called a”
Negative Edge”. It is the opposite of a positive edge triggered flip flop.

An edge triggered clock is identified with “o|>Clk” on the symbol.

1 S Q 0 Assume
1 Output SETs
Q Watch the animation to see how you would set the flip flop.
>Clk starts
: Q =1.
at 0.
Holding “o|>Clk” at logic 0 will not result in S and R controlling
0 R Q 1
0
Q. Only the 1 to 0 transition at “o|>Clk“ causes the output Q to
change.
SR Flip Flop with
edge triggered clock
S=1 : Set Mode :

Here is a summary of the flip flop devices

S Q S Q S Q S Q
>Clk >Clk
R Q R Q R Q R Q

Non-Clocked SR Edge Triggered

S and R control the response at Q

S and R control the only when Clk is making a
response at Q transition.
continuously. On the edge of the clock signal.

Slide #5
Note Pack 5 : Flip Flop Waveform Diagrams :
To draw waveforms for flip flops you need to begin with an initial condition at
Q, mark the area where the clock input is asserted and then draw the output
response. Let’s use an initial condition of Q =0.
The initial condition Q =0 is
marked as a dot on the output
waveform diagram.
Set The flip flop has a negative
edge triggered clock. The
Rese clock is asserted when Clk
makes a transition from 1 to
t 0. The asserted zone is
Cloc marked off in yellow.

k Analyze the waveform and

draw Q.
S Q
>Clk
R Q
Until
On this
thenegative
clock changes
edge S=1
S=R=0:
fromand1 to
No
R=0:
0Change
it SET
is NOT
Mode.
Mode.
asserted.
Thus Q sets
holdstoat1.0.No
Noanalysis
analysisisisrequired
requireduntil
untilthe
next
Thus negative
negative
next Q holds
edge. at
edge.
0.

Slide #6