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Digital Design Laboratory (EECS/CSE 31L)

Installation guide and short tutorial for Mentor Graphics
ModelSim PE Student Edition 10.3c
Prepared by: Tarun Prakash

EECS Department
Henry Samueli School of Engineering
University of California, Irvine

October 4, 2014


Introduction
In this document we will cover the basics of Installing ModelSim, compiling and simulating
VHDL/Verilog code.
Please note this tutorial is targeted to Windows users. If you are a MAC user, we suggest you
install a windows virtual machine which lets you run Windows on your MAC. There are many
tutorials available on the internet to install virtual machine.
Installation and Setup
This is a step by step guide for installation and set-up of ModelSim PE Student Edition 10.3c.
1. Download ModelSim PE Student Edition from
http://www.mentor.com/company/higher_ed/modelsim-student-edition


2. After the download is complete, a 243MB .exe file should be available on your PC.


3. Double click on the .exe file to begin installation process.
4. Make sure you agree to Mentor Graphics End-User License agreement during
installation.



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5. At the end of the installation process, click on finish and the browser window will open
with the license request form. The license request form should look like this.


6. Complete all of the form fields with extra attention to email address field and submit the
request form.
7. Once youve submitted your license request form, you will receive an email with the
subject line ModelSim Student Edition License which contains student_license.dat
file.
8. Please note, this student_license.dat file is mapped to a specific .exe file and the host
computer. You will not be able to copy your friends .exe/student_license.dat files and
install in your PC.
9. Last step of installation is to save this student_license.dat file in your top level
installation directory (ex., C:\Modeltech_pe_edu_10.3c).
10. Congratulations you have successfully installed ModelSim PE student edition 10.3c.

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ModelSim Basics
ModelSim is a fantastic digital simulator for both Verilog and VHDL hardware description
languages (HDL).
The following diagram shows the basic steps for simulation in ModelSim.

Create a working directory

Start ModelSim and create a new project

Write your VHDL code or add your code to the project

Compile your VHDL code and debugg errors

Load and run sumulations

Debugging

1. Create a directory for your simulation. For example., D:\EECS31L\ModelSim
ModelSim creates large output files, by creating a project directory it will be easier to
manage all the project files.

2. Start ModelSim, you will be able to find a shortcut on your desktop or else it will be
present in your start menu.

3. To create a new project go to File -> New -> Project
4. A new window will appear.
a. Enter the project name, ex., test
b. Change the project location to your simulation directory ex.,
D:\EECS31L\ModelSim
c. You can leave the default library name as work
d. Click OK.

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5. In the next window you can either add an existing file or create new file. We shall create
a new file for this example.
a. Click on Create New File
b. In the next window, type a file name (for this example we shall design an OR
gate)
c. Make sure the file type is VHDL and the folder is Top Level
d. Click OK.
e. Close Add items to the Project window.
f. Note: you can also add existing VHDL files to your current project by selecting
Add existing file. You can also add multiple files by selecting this option.


6. An empty orgate.vhd should be created in your project window. Double click on the
orgate.vhd file to type the code.

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7. Copy & paste the following code snippet.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY orgate IS
PORT ( IN1 : in STD_LOGIC; -- OR gate input
IN2 : in STD_LOGIC; -- OR gate input
OUT1 : out STD_LOGIC); -- OR gate output
END orgate;
ARCHITECTURE Behavioral of orgate IS
BEGIN
OUT1 <= IN1 or IN2; -- 2 input OR gate
END Behavioral;


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8. Save and compile
To save the code click on the small floppy drive or use the shortcut Ctrl+s
To compile the code click on compile icon , or right click orgare.vhd -> Compile ->
Compile All.



9. If the compilation is successful a message will appear in the transcript window and the
status of the orgate.vhd will be changed.


10. A little more information about the status of the VHLD files:

a. A means that the file has not been compiled since the last edit.
b. A means that the file could not be compiled, it has an error.
Double clicking the will bring up a list of errors with line numbers
c. A means that the file has been compiled successfully.


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11. Simulate.
After compilation, the next step is to simulate the VHDL code. To simulate the
compiled code click on simulate icon or simulate->start Simulation to bring up the
simulation dialog box.




12. Click the plus next to the work library and select your entity (in this case, its orgate).
Click OK.

13. A new window should appear and your design should be loaded and ready to simulate.



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14. Adding signals to the waveform window.
a. Go to the signals window or the signals panel (this window will be in the middle
of the main window). This window will list all the signals in the current instance.
b. To add the signals to your wave window right click on the signals and click Add
Wave.
c. You can shift+select multiple signals and add them together to the wave
window.




15. In the wave window you can force the input signals to either 0 or 1 or you can assign
a clock.
a. To assign a clock to IN1, right click on /orgate/IN1 in you wave window and
click on clock to open a clock definition dialog box.


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b. Please feel free to play with these parameters to get random signal.
c. For this example we will keep the default values for /orgate/IN1. Click OK
d. Next, we shall assign clock to IN2. Right click on /orgate/IN2 and click on clock
to open a clock definition dialog box. Here change the period to 200 and click
OK.
e. Now we have assigned the inputs, we need to simulate to get OUT1
f. To simulate, update the simulation time to 1us and click run
g. You should see the simulated output in the wave window. The output wave can
be verified by comparing it with the truth table on OR gate.



h. You can end simulation by clicking Simulate -> End Simulation
i. Similarly Simulation can be restarted by clicking Simulate -> Restart

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User manual
To find out more about ModelSim please go through the user manual. The user manual is
available in Help -> PDF Documentation -> Users Manual
Also feel free to contact any TAs for more information.